1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_3.h" 26 27 #include "mmhub/mmhub_3_3_0_offset.h" 28 #include "mmhub/mmhub_3_3_0_sh_mask.h" 29 30 #include "navi10_enum.h" 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 #define regDAGB0_L1TLB_REG_RW_3_3 0x00a4 37 #define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX 1 38 #define regDAGB1_L1TLB_REG_RW_3_3 0x0163 39 #define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX 1 40 41 static const char *mmhub_client_ids_v3_3[][2] = { 42 [0][0] = "VMC", 43 [1][0] = "ISPXT", 44 [2][0] = "ISPIXT", 45 [4][0] = "DCEDMC", 46 [6][0] = "MP0", 47 [7][0] = "MP1", 48 [8][0] = "MPM", 49 [9][0] = "ISPPDPRD", 50 [10][0] = "ISPCSTATRD", 51 [11][0] = "ISPBYRPRD", 52 [12][0] = "ISPRGBPRD", 53 [13][0] = "ISPMCFPRD", 54 [14][0] = "ISPMCFPRD1", 55 [15][0] = "ISPYUVPRD", 56 [16][0] = "ISPMCSCRD", 57 [17][0] = "ISPGDCRD", 58 [18][0] = "ISPLMERD", 59 [22][0] = "ISPXT1", 60 [23][0] = "ISPIXT1", 61 [24][0] = "HDP", 62 [25][0] = "LSDMA", 63 [26][0] = "JPEG", 64 [27][0] = "VPE", 65 [28][0] = "VSCH", 66 [29][0] = "VCNU", 67 [30][0] = "VCN", 68 [1][1] = "ISPXT", 69 [2][1] = "ISPIXT", 70 [3][1] = "DCEDWB", 71 [4][1] = "DCEDMC", 72 [5][1] = "ISPCSISWR", 73 [6][1] = "MP0", 74 [7][1] = "MP1", 75 [8][1] = "MPM", 76 [9][1] = "ISPPDPWR", 77 [10][1] = "ISPCSTATWR", 78 [11][1] = "ISPBYRPWR", 79 [12][1] = "ISPRGBPWR", 80 [13][1] = "ISPMCFPWR", 81 [14][1] = "ISPMWR0", 82 [15][1] = "ISPYUVPWR", 83 [16][1] = "ISPMCSCWR", 84 [17][1] = "ISPGDCWR", 85 [18][1] = "ISPLMEWR", 86 [20][1] = "ISPMWR2", 87 [21][1] = "OSSSYS", 88 [22][1] = "ISPXT1", 89 [23][1] = "ISPIXT1", 90 [24][1] = "HDP", 91 [25][1] = "LSDMA", 92 [26][1] = "JPEG", 93 [27][1] = "VPE", 94 [28][1] = "VSCH", 95 [29][1] = "VCNU", 96 [30][1] = "VCN", 97 }; 98 99 static const char *mmhub_client_ids_v3_3_1[][2] = { 100 [0][0] = "VMC", 101 [4][0] = "DCEDMC", 102 [6][0] = "MP0", 103 [7][0] = "MP1", 104 [8][0] = "MPM", 105 [24][0] = "HDP", 106 [25][0] = "LSDMA", 107 [26][0] = "JPEG0", 108 [27][0] = "VPE0", 109 [28][0] = "VSCH", 110 [29][0] = "VCNU0", 111 [30][0] = "VCN0", 112 [32+1][0] = "ISPXT", 113 [32+2][0] = "ISPIXT", 114 [32+9][0] = "ISPPDPRD", 115 [32+10][0] = "ISPCSTATRD", 116 [32+11][0] = "ISPBYRPRD", 117 [32+12][0] = "ISPRGBPRD", 118 [32+13][0] = "ISPMCFPRD", 119 [32+14][0] = "ISPMCFPRD1", 120 [32+15][0] = "ISPYUVPRD", 121 [32+16][0] = "ISPMCSCRD", 122 [32+17][0] = "ISPGDCRD", 123 [32+18][0] = "ISPLMERD", 124 [32+22][0] = "ISPXT1", 125 [32+23][0] = "ISPIXT1", 126 [32+26][0] = "JPEG1", 127 [32+27][0] = "VPE1", 128 [32+29][0] = "VCNU1", 129 [32+30][0] = "VCN1", 130 [3][1] = "DCEDWB", 131 [4][1] = "DCEDMC", 132 [6][1] = "MP0", 133 [7][1] = "MP1", 134 [8][1] = "MPM", 135 [21][1] = "OSSSYS", 136 [24][1] = "HDP", 137 [25][1] = "LSDMA", 138 [26][1] = "JPEG0", 139 [27][1] = "VPE0", 140 [28][1] = "VSCH", 141 [29][1] = "VCNU0", 142 [30][1] = "VCN0", 143 [32+1][1] = "ISPXT", 144 [32+2][1] = "ISPIXT", 145 [32+5][1] = "ISPCSISWR", 146 [32+9][1] = "ISPPDPWR", 147 [32+10][1] = "ISPCSTATWR", 148 [32+11][1] = "ISPBYRPWR", 149 [32+12][1] = "ISPRGBPWR", 150 [32+13][1] = "ISPMCFPWR", 151 [32+14][1] = "ISPMWR0", 152 [32+15][1] = "ISPYUVPWR", 153 [32+16][1] = "ISPMCSCWR", 154 [32+17][1] = "ISPGDCWR", 155 [32+18][1] = "ISPLMEWR", 156 [32+19][1] = "ISPMWR1", 157 [32+20][1] = "ISPMWR2", 158 [32+22][1] = "ISPXT1", 159 [32+23][1] = "ISPIXT1", 160 [32+26][1] = "JPEG1", 161 [32+27][1] = "VPE1", 162 [32+29][1] = "VCNU1", 163 [32+30][1] = "VCN1", 164 }; 165 166 static const char *mmhub_client_ids_v3_4[][2] = { 167 [0][0] = "VMC", 168 [4][0] = "DCEDMC", 169 [5][0] = "MPXSP", 170 [6][0] = "MPASP", 171 [7][0] = "MP1", 172 [8][0] = "MPM", 173 [23][0] = "HDP", 174 [24][0] = "LSDMA", 175 [25][0] = "JPEG", 176 [26][0] = "VPE", 177 [27][0] = "VSCH", 178 [28][0] = "VCNU", 179 [30][0] = "VCNRD", 180 [3][1] = "DCEDWB", 181 [4][1] = "DCEDMC", 182 [5][1] = "MPXSP", 183 [6][1] = "MPASAP", 184 [7][1] = "MP1", 185 [8][1] = "MPM", 186 [21][1] = "OSSSYS", 187 [23][1] = "HDP", 188 [24][1] = "LSDMA", 189 [25][1] = "JPEG", 190 [26][1] = "VPE", 191 [27][1] = "VSCH", 192 [29][1] = "VCNWR", 193 }; 194 195 static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, 196 uint32_t flush_type) 197 { 198 u32 req = 0; 199 200 /* invalidate using legacy mode on vmid*/ 201 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 202 PER_VMID_INVALIDATE_REQ, 1 << vmid); 203 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1); 204 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 205 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 206 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 207 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 208 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 209 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 210 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 211 212 return req; 213 } 214 215 static void 216 mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 217 uint32_t status) 218 { 219 uint32_t cid, rw; 220 const char *mmhub_cid; 221 222 cid = REG_GET_FIELD(status, 223 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 224 rw = REG_GET_FIELD(status, 225 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 226 227 dev_err(adev->dev, 228 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 229 status); 230 if (cid == 0x140) 231 mmhub_cid = "UMSCH"; 232 else 233 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); 234 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 235 mmhub_cid ? mmhub_cid : "unknown", cid); 236 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 237 REG_GET_FIELD(status, 238 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 239 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 240 REG_GET_FIELD(status, 241 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 242 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 243 REG_GET_FIELD(status, 244 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 245 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 246 REG_GET_FIELD(status, 247 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 248 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 249 } 250 251 static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, 252 uint32_t vmid, 253 uint64_t page_table_base) 254 { 255 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 256 257 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 258 hub->ctx_addr_distance * vmid, 259 lower_32_bits(page_table_base)); 260 261 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 262 hub->ctx_addr_distance * vmid, 263 upper_32_bits(page_table_base)); 264 265 } 266 267 static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) 268 { 269 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 270 271 mmhub_v3_3_setup_vm_pt_regs(adev, 0, pt_base); 272 273 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 274 (u32)(adev->gmc.gart_start >> 12)); 275 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 276 (u32)(adev->gmc.gart_start >> 44)); 277 278 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 279 (u32)(adev->gmc.gart_end >> 12)); 280 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 281 (u32)(adev->gmc.gart_end >> 44)); 282 } 283 284 static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) 285 { 286 uint64_t value; 287 uint32_t tmp; 288 289 /* Program the AGP BAR */ 290 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 291 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 292 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 293 294 /* 295 * the new L1 policy will block SRIOV guest from writing 296 * these regs, and they will be programed at host. 297 * so skip programing these regs. 298 */ 299 /* Program the system aperture low logical page number. */ 300 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 301 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 302 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 303 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 304 305 /* Set default page address. */ 306 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 307 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 308 (u32)(value >> 12)); 309 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 310 (u32)(value >> 44)); 311 312 /* Program "protection fault". */ 313 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 314 (u32)(adev->dummy_page_addr >> 12)); 315 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 316 (u32)((u64)adev->dummy_page_addr >> 44)); 317 318 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 319 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 320 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 321 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 322 } 323 324 static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) 325 { 326 uint32_t tmp; 327 328 /* Setup TLB control */ 329 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 330 331 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 332 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 333 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 334 ENABLE_ADVANCED_DRIVER_MODEL, 1); 335 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 336 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 337 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 338 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 339 MTYPE, MTYPE_UC); /* UC, uncached */ 340 341 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 342 } 343 344 static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) 345 { 346 uint32_t tmp; 347 348 /* Setup L2 cache */ 349 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 350 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 351 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 352 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 353 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 354 /* XXX for emulation, Refer to closed source code.*/ 355 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 356 0); 357 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 358 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 359 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 360 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 361 362 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 363 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 364 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 365 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 366 367 tmp = regMMVM_L2_CNTL3_DEFAULT; 368 if (adev->gmc.translate_further) { 369 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 370 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 371 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 372 } else { 373 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 374 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 375 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 376 } 377 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 378 379 tmp = regMMVM_L2_CNTL4_DEFAULT; 380 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 381 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 382 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 383 384 tmp = regMMVM_L2_CNTL5_DEFAULT; 385 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 386 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 387 } 388 389 static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) 390 { 391 uint32_t tmp; 392 393 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 394 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 395 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 396 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 397 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 398 399 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 400 } 401 402 static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) 403 { 404 WREG32_SOC15(MMHUB, 0, 405 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 406 0xFFFFFFFF); 407 WREG32_SOC15(MMHUB, 0, 408 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 409 0x0000000F); 410 411 WREG32_SOC15(MMHUB, 0, 412 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 413 WREG32_SOC15(MMHUB, 0, 414 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 415 416 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 417 0); 418 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 419 0); 420 } 421 422 static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) 423 { 424 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 425 int i; 426 uint32_t tmp; 427 428 for (i = 0; i <= 14; i++) { 429 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 430 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 431 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 432 adev->vm_manager.num_level); 433 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 434 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 435 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 436 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 437 1); 438 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 439 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 440 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 441 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 442 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 443 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 444 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 445 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 446 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 447 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 448 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 449 PAGE_TABLE_BLOCK_SIZE, 450 adev->vm_manager.block_size - 9); 451 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 452 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 453 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 454 !amdgpu_noretry); 455 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 456 i * hub->ctx_distance, tmp); 457 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 458 i * hub->ctx_addr_distance, 0); 459 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 460 i * hub->ctx_addr_distance, 0); 461 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 462 i * hub->ctx_addr_distance, 463 lower_32_bits(adev->vm_manager.max_pfn - 1)); 464 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 465 i * hub->ctx_addr_distance, 466 upper_32_bits(adev->vm_manager.max_pfn - 1)); 467 } 468 469 hub->vm_cntx_cntl = tmp; 470 } 471 472 static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) 473 { 474 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 475 unsigned int i; 476 477 for (i = 0; i < 18; ++i) { 478 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 479 i * hub->eng_addr_distance, 0xffffffff); 480 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 481 i * hub->eng_addr_distance, 0x1f); 482 } 483 } 484 485 static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) 486 { 487 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 488 uint32_t tmp; 489 490 /* Program page table base, gart start, gart end */ 491 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 492 lower_32_bits(pt_base >> 12)); 493 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 494 upper_32_bits(pt_base >> 12)); 495 496 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 497 (u32)(adev->gmc.gart_start >> 12)); 498 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 499 (u32)(adev->gmc.gart_start >> 44)); 500 501 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 502 (u32)(adev->gmc.gart_end >> 12)); 503 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 504 (u32)(adev->gmc.gart_end >> 44)); 505 506 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL); 507 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 508 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 509 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp); 510 511 /* Disable all contexts except context 0 */ 512 tmp = 0xfffe; 513 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp); 514 515 /* Program saw cntl4 */ 516 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); 517 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1); 518 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1); 519 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp); 520 } 521 522 static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev) 523 { 524 WREG32_SOC15(MMHUB, 0, regDAGB0_L1TLB_REG_RW_3_3, 0); 525 WREG32_SOC15(MMHUB, 0, regDAGB1_L1TLB_REG_RW_3_3, 3); 526 } 527 528 static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) 529 { 530 /* GART Enable. */ 531 mmhub_v3_3_init_gart_aperture_regs(adev); 532 mmhub_v3_3_init_system_aperture_regs(adev); 533 mmhub_v3_3_init_tlb_regs(adev); 534 mmhub_v3_3_init_cache_regs(adev); 535 536 mmhub_v3_3_enable_system_domain(adev); 537 mmhub_v3_3_disable_identity_aperture(adev); 538 mmhub_v3_3_setup_vmid_config(adev); 539 mmhub_v3_3_program_invalidation(adev); 540 541 /* standalone alone walker init */ 542 mmhub_v3_3_init_saw_regs(adev); 543 544 /* enable mmhub tls */ 545 mmhub_v3_3_enable_tls(adev); 546 547 return 0; 548 } 549 550 static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) 551 { 552 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 553 u32 tmp; 554 u32 i; 555 556 /* Disable all tables */ 557 for (i = 0; i < 16; i++) 558 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 559 i * hub->ctx_distance, 0); 560 561 /* Setup TLB control */ 562 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 563 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 564 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 565 ENABLE_ADVANCED_DRIVER_MODEL, 0); 566 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 567 568 /* Setup L2 cache */ 569 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 570 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 571 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 572 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 573 } 574 575 /** 576 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling 577 * 578 * @adev: amdgpu_device pointer 579 * @value: true redirects VM faults to the default page 580 */ 581 static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, 582 bool value) 583 { 584 u32 tmp; 585 586 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 587 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 588 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 589 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 590 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 591 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 592 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 593 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 594 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 595 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 596 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 597 value); 598 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 599 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 600 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 601 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 602 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 603 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 604 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 605 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 606 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 607 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 608 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 609 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 610 if (!value) { 611 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 612 CRASH_ON_NO_RETRY_FAULT, 1); 613 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 614 CRASH_ON_RETRY_FAULT, 1); 615 } 616 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 617 } 618 619 static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { 620 .print_l2_protection_fault_status = mmhub_v3_3_print_l2_protection_fault_status, 621 .get_invalidate_req = mmhub_v3_3_get_invalidate_req, 622 }; 623 624 static void mmhub_v3_3_init_client_info(struct amdgpu_device *adev) 625 { 626 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 627 case IP_VERSION(3, 3, 0): 628 case IP_VERSION(3, 3, 2): 629 amdgpu_mmhub_init_client_info(&adev->mmhub, 630 mmhub_client_ids_v3_3, 631 ARRAY_SIZE(mmhub_client_ids_v3_3)); 632 break; 633 case IP_VERSION(3, 3, 1): 634 amdgpu_mmhub_init_client_info(&adev->mmhub, 635 mmhub_client_ids_v3_3_1, 636 ARRAY_SIZE(mmhub_client_ids_v3_3_1)); 637 break; 638 case IP_VERSION(3, 4, 0): 639 amdgpu_mmhub_init_client_info(&adev->mmhub, 640 mmhub_client_ids_v3_4, 641 ARRAY_SIZE(mmhub_client_ids_v3_4)); 642 break; 643 default: 644 break; 645 } 646 } 647 648 static void mmhub_v3_3_init(struct amdgpu_device *adev) 649 { 650 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 651 652 hub->ctx0_ptb_addr_lo32 = 653 SOC15_REG_OFFSET(MMHUB, 0, 654 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 655 hub->ctx0_ptb_addr_hi32 = 656 SOC15_REG_OFFSET(MMHUB, 0, 657 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 658 hub->vm_inv_eng0_sem = 659 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 660 hub->vm_inv_eng0_req = 661 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 662 hub->vm_inv_eng0_ack = 663 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 664 hub->vm_context0_cntl = 665 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 666 hub->vm_l2_pro_fault_status = 667 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 668 hub->vm_l2_pro_fault_cntl = 669 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 670 671 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 672 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 673 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 674 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 675 regMMVM_INVALIDATE_ENG0_REQ; 676 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 677 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 678 679 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 680 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 681 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 682 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 683 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 684 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 685 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 686 687 hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; 688 689 mmhub_v3_3_init_client_info(adev); 690 } 691 692 static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) 693 { 694 u64 base; 695 696 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 697 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 698 base <<= 24; 699 700 return base; 701 } 702 703 static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) 704 { 705 u64 offset; 706 707 offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); 708 offset &= MMMC_VM_FB_OFFSET__FB_OFFSET_MASK; 709 offset <<= 24; 710 711 return offset; 712 } 713 714 static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 715 bool enable) 716 { 717 uint32_t def, data; 718 719 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 720 721 if (enable) 722 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 723 else 724 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 725 726 if (def != data) 727 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 728 } 729 730 static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 731 bool enable) 732 { 733 uint32_t def, data; 734 735 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 736 737 if (enable) 738 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 739 else 740 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 741 742 if (def != data) 743 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 744 } 745 746 static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, 747 enum amd_clockgating_state state) 748 { 749 if (amdgpu_sriov_vf(adev)) 750 return 0; 751 752 mmhub_v3_3_update_medium_grain_clock_gating(adev, 753 state == AMD_CG_STATE_GATE); 754 mmhub_v3_3_update_medium_grain_light_sleep(adev, 755 state == AMD_CG_STATE_GATE); 756 return 0; 757 } 758 759 static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) 760 { 761 u32 data; 762 763 if (amdgpu_sriov_vf(adev)) 764 *flags = 0; 765 766 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 767 768 /* AMD_CG_SUPPORT_MC_MGCG */ 769 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 770 *flags |= AMD_CG_SUPPORT_MC_MGCG; 771 772 /* AMD_CG_SUPPORT_MC_LS */ 773 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 774 *flags |= AMD_CG_SUPPORT_MC_LS; 775 } 776 777 const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = { 778 .init = mmhub_v3_3_init, 779 .get_fb_location = mmhub_v3_3_get_fb_location, 780 .get_mc_fb_offset = mmhub_v3_3_get_mc_fb_offset, 781 .gart_enable = mmhub_v3_3_gart_enable, 782 .set_fault_enable_default = mmhub_v3_3_set_fault_enable_default, 783 .gart_disable = mmhub_v3_3_gart_disable, 784 .set_clockgating = mmhub_v3_3_set_clockgating, 785 .get_clockgating = mmhub_v3_3_get_clockgating, 786 .setup_vm_pt_regs = mmhub_v3_3_setup_vm_pt_regs, 787 }; 788