1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_3.h" 26 27 #include "mmhub/mmhub_3_3_0_offset.h" 28 #include "mmhub/mmhub_3_3_0_sh_mask.h" 29 30 #include "navi10_enum.h" 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 #define regDAGB0_L1TLB_REG_RW_3_3 0x00a4 37 #define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX 1 38 #define regDAGB1_L1TLB_REG_RW_3_3 0x0163 39 #define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX 1 40 41 static const char *mmhub_client_ids_v3_3[][2] = { 42 [0][0] = "VMC", 43 [4][0] = "DCEDMC", 44 [6][0] = "MP0", 45 [7][0] = "MP1", 46 [8][0] = "MPM", 47 [24][0] = "HDP", 48 [25][0] = "LSDMA", 49 [26][0] = "JPEG", 50 [27][0] = "VPE", 51 [29][0] = "VCNU", 52 [30][0] = "VCN", 53 [3][1] = "DCEDWB", 54 [4][1] = "DCEDMC", 55 [6][1] = "MP0", 56 [7][1] = "MP1", 57 [8][1] = "MPM", 58 [21][1] = "OSSSYS", 59 [24][1] = "HDP", 60 [25][1] = "LSDMA", 61 [26][1] = "JPEG", 62 [27][1] = "VPE", 63 [29][1] = "VCNU", 64 [30][1] = "VCN", 65 }; 66 67 static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, 68 uint32_t flush_type) 69 { 70 u32 req = 0; 71 72 /* invalidate using legacy mode on vmid*/ 73 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 74 PER_VMID_INVALIDATE_REQ, 1 << vmid); 75 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1); 76 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 77 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 78 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 79 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 80 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 82 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 83 84 return req; 85 } 86 87 static void 88 mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 89 uint32_t status) 90 { 91 uint32_t cid, rw; 92 const char *mmhub_cid = NULL; 93 94 cid = REG_GET_FIELD(status, 95 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 96 rw = REG_GET_FIELD(status, 97 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 98 99 dev_err(adev->dev, 100 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 101 status); 102 103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 104 case IP_VERSION(3, 3, 0): 105 case IP_VERSION(3, 3, 1): 106 case IP_VERSION(3, 3, 2): 107 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? 108 mmhub_client_ids_v3_3[cid][rw] : 109 cid == 0x140 ? "UMSCH" : NULL; 110 break; 111 default: 112 mmhub_cid = NULL; 113 break; 114 } 115 116 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 117 mmhub_cid ? mmhub_cid : "unknown", cid); 118 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 119 REG_GET_FIELD(status, 120 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 121 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 122 REG_GET_FIELD(status, 123 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 124 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 125 REG_GET_FIELD(status, 126 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 127 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 128 REG_GET_FIELD(status, 129 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 130 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 131 } 132 133 static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, 134 uint32_t vmid, 135 uint64_t page_table_base) 136 { 137 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 138 139 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 140 hub->ctx_addr_distance * vmid, 141 lower_32_bits(page_table_base)); 142 143 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 144 hub->ctx_addr_distance * vmid, 145 upper_32_bits(page_table_base)); 146 147 } 148 149 static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) 150 { 151 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 152 153 mmhub_v3_3_setup_vm_pt_regs(adev, 0, pt_base); 154 155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 156 (u32)(adev->gmc.gart_start >> 12)); 157 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 158 (u32)(adev->gmc.gart_start >> 44)); 159 160 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 161 (u32)(adev->gmc.gart_end >> 12)); 162 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 163 (u32)(adev->gmc.gart_end >> 44)); 164 } 165 166 static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) 167 { 168 uint64_t value; 169 uint32_t tmp; 170 171 /* Program the AGP BAR */ 172 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 175 176 /* 177 * the new L1 policy will block SRIOV guest from writing 178 * these regs, and they will be programed at host. 179 * so skip programing these regs. 180 */ 181 /* Program the system aperture low logical page number. */ 182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 183 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 185 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 186 187 /* Set default page address. */ 188 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 189 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 190 (u32)(value >> 12)); 191 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 192 (u32)(value >> 44)); 193 194 /* Program "protection fault". */ 195 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 196 (u32)(adev->dummy_page_addr >> 12)); 197 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 198 (u32)((u64)adev->dummy_page_addr >> 44)); 199 200 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 201 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 202 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 203 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 204 } 205 206 static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) 207 { 208 uint32_t tmp; 209 210 /* Setup TLB control */ 211 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 212 213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 215 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 216 ENABLE_ADVANCED_DRIVER_MODEL, 1); 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 218 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 220 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 221 MTYPE, MTYPE_UC); /* UC, uncached */ 222 223 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 224 } 225 226 static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) 227 { 228 uint32_t tmp; 229 230 /* Setup L2 cache */ 231 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 232 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 234 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 235 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 236 /* XXX for emulation, Refer to closed source code.*/ 237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 238 0); 239 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 240 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 242 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 243 244 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 245 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 246 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 247 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 248 249 tmp = regMMVM_L2_CNTL3_DEFAULT; 250 if (adev->gmc.translate_further) { 251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 253 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 254 } else { 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 257 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 258 } 259 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 260 261 tmp = regMMVM_L2_CNTL4_DEFAULT; 262 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 263 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 264 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 265 266 tmp = regMMVM_L2_CNTL5_DEFAULT; 267 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 268 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 269 } 270 271 static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) 272 { 273 uint32_t tmp; 274 275 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 276 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 277 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 278 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 279 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 280 281 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 282 } 283 284 static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) 285 { 286 WREG32_SOC15(MMHUB, 0, 287 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 288 0xFFFFFFFF); 289 WREG32_SOC15(MMHUB, 0, 290 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 291 0x0000000F); 292 293 WREG32_SOC15(MMHUB, 0, 294 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 295 WREG32_SOC15(MMHUB, 0, 296 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 297 298 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 299 0); 300 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 301 0); 302 } 303 304 static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) 305 { 306 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 307 int i; 308 uint32_t tmp; 309 310 for (i = 0; i <= 14; i++) { 311 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 312 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 313 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 314 adev->vm_manager.num_level); 315 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 316 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 317 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 318 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 319 1); 320 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 321 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 323 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 325 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 327 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 329 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 331 PAGE_TABLE_BLOCK_SIZE, 332 adev->vm_manager.block_size - 9); 333 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 335 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 336 !amdgpu_noretry); 337 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 338 i * hub->ctx_distance, tmp); 339 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 340 i * hub->ctx_addr_distance, 0); 341 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 342 i * hub->ctx_addr_distance, 0); 343 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 344 i * hub->ctx_addr_distance, 345 lower_32_bits(adev->vm_manager.max_pfn - 1)); 346 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 347 i * hub->ctx_addr_distance, 348 upper_32_bits(adev->vm_manager.max_pfn - 1)); 349 } 350 351 hub->vm_cntx_cntl = tmp; 352 } 353 354 static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) 355 { 356 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 357 unsigned int i; 358 359 for (i = 0; i < 18; ++i) { 360 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 361 i * hub->eng_addr_distance, 0xffffffff); 362 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 363 i * hub->eng_addr_distance, 0x1f); 364 } 365 } 366 367 static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) 368 { 369 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 370 uint32_t tmp; 371 372 /* Program page table base, gart start, gart end */ 373 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 374 lower_32_bits(pt_base >> 12)); 375 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 376 upper_32_bits(pt_base >> 12)); 377 378 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 379 (u32)(adev->gmc.gart_start >> 12)); 380 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 381 (u32)(adev->gmc.gart_start >> 44)); 382 383 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 384 (u32)(adev->gmc.gart_end >> 12)); 385 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 386 (u32)(adev->gmc.gart_end >> 44)); 387 388 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL); 389 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 390 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 391 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp); 392 393 /* Disable all contexts except context 0 */ 394 tmp = 0xfffe; 395 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp); 396 397 /* Program saw cntl4 */ 398 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); 399 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1); 400 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1); 401 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp); 402 } 403 404 static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev) 405 { 406 WREG32_SOC15(MMHUB, 0, regDAGB0_L1TLB_REG_RW_3_3, 0); 407 WREG32_SOC15(MMHUB, 0, regDAGB1_L1TLB_REG_RW_3_3, 3); 408 } 409 410 static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) 411 { 412 /* GART Enable. */ 413 mmhub_v3_3_init_gart_aperture_regs(adev); 414 mmhub_v3_3_init_system_aperture_regs(adev); 415 mmhub_v3_3_init_tlb_regs(adev); 416 mmhub_v3_3_init_cache_regs(adev); 417 418 mmhub_v3_3_enable_system_domain(adev); 419 mmhub_v3_3_disable_identity_aperture(adev); 420 mmhub_v3_3_setup_vmid_config(adev); 421 mmhub_v3_3_program_invalidation(adev); 422 423 /* standalone alone walker init */ 424 mmhub_v3_3_init_saw_regs(adev); 425 426 /* enable mmhub tls */ 427 mmhub_v3_3_enable_tls(adev); 428 429 return 0; 430 } 431 432 static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) 433 { 434 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 435 u32 tmp; 436 u32 i; 437 438 /* Disable all tables */ 439 for (i = 0; i < 16; i++) 440 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 441 i * hub->ctx_distance, 0); 442 443 /* Setup TLB control */ 444 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 445 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 446 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 447 ENABLE_ADVANCED_DRIVER_MODEL, 0); 448 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 449 450 /* Setup L2 cache */ 451 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 452 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 453 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 454 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 455 } 456 457 /** 458 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling 459 * 460 * @adev: amdgpu_device pointer 461 * @value: true redirects VM faults to the default page 462 */ 463 static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, 464 bool value) 465 { 466 u32 tmp; 467 468 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 469 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 470 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 471 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 472 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 473 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 474 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 475 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 476 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 477 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 478 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 479 value); 480 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 481 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 482 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 483 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 484 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 485 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 486 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 487 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 488 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 489 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 490 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 491 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 492 if (!value) { 493 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 494 CRASH_ON_NO_RETRY_FAULT, 1); 495 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 496 CRASH_ON_RETRY_FAULT, 1); 497 } 498 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 499 } 500 501 static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { 502 .print_l2_protection_fault_status = mmhub_v3_3_print_l2_protection_fault_status, 503 .get_invalidate_req = mmhub_v3_3_get_invalidate_req, 504 }; 505 506 static void mmhub_v3_3_init(struct amdgpu_device *adev) 507 { 508 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 509 510 hub->ctx0_ptb_addr_lo32 = 511 SOC15_REG_OFFSET(MMHUB, 0, 512 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 513 hub->ctx0_ptb_addr_hi32 = 514 SOC15_REG_OFFSET(MMHUB, 0, 515 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 516 hub->vm_inv_eng0_sem = 517 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 518 hub->vm_inv_eng0_req = 519 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 520 hub->vm_inv_eng0_ack = 521 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 522 hub->vm_context0_cntl = 523 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 524 hub->vm_l2_pro_fault_status = 525 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 526 hub->vm_l2_pro_fault_cntl = 527 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 528 529 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 530 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 531 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 532 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 533 regMMVM_INVALIDATE_ENG0_REQ; 534 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 535 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 536 537 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 538 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 539 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 540 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 541 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 542 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 543 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 544 545 hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; 546 } 547 548 static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) 549 { 550 u64 base; 551 552 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 553 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 554 base <<= 24; 555 556 return base; 557 } 558 559 static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) 560 { 561 u64 offset; 562 563 offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); 564 offset &= MMMC_VM_FB_OFFSET__FB_OFFSET_MASK; 565 offset <<= 24; 566 567 return offset; 568 } 569 570 static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 571 bool enable) 572 { 573 uint32_t def, data; 574 575 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 576 577 if (enable) 578 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 579 else 580 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 581 582 if (def != data) 583 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 584 } 585 586 static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 587 bool enable) 588 { 589 uint32_t def, data; 590 591 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 592 593 if (enable) 594 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 595 else 596 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 597 598 if (def != data) 599 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 600 } 601 602 static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, 603 enum amd_clockgating_state state) 604 { 605 if (amdgpu_sriov_vf(adev)) 606 return 0; 607 608 mmhub_v3_3_update_medium_grain_clock_gating(adev, 609 state == AMD_CG_STATE_GATE); 610 mmhub_v3_3_update_medium_grain_light_sleep(adev, 611 state == AMD_CG_STATE_GATE); 612 return 0; 613 } 614 615 static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) 616 { 617 u32 data; 618 619 if (amdgpu_sriov_vf(adev)) 620 *flags = 0; 621 622 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 623 624 /* AMD_CG_SUPPORT_MC_MGCG */ 625 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 626 *flags |= AMD_CG_SUPPORT_MC_MGCG; 627 628 /* AMD_CG_SUPPORT_MC_LS */ 629 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 630 *flags |= AMD_CG_SUPPORT_MC_LS; 631 } 632 633 const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = { 634 .init = mmhub_v3_3_init, 635 .get_fb_location = mmhub_v3_3_get_fb_location, 636 .get_mc_fb_offset = mmhub_v3_3_get_mc_fb_offset, 637 .gart_enable = mmhub_v3_3_gart_enable, 638 .set_fault_enable_default = mmhub_v3_3_set_fault_enable_default, 639 .gart_disable = mmhub_v3_3_gart_disable, 640 .set_clockgating = mmhub_v3_3_set_clockgating, 641 .get_clockgating = mmhub_v3_3_get_clockgating, 642 .setup_vm_pt_regs = mmhub_v3_3_setup_vm_pt_regs, 643 }; 644