1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_3.h" 26 27 #include "mmhub/mmhub_3_3_0_offset.h" 28 #include "mmhub/mmhub_3_3_0_sh_mask.h" 29 30 #include "navi10_enum.h" 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 #define regDAGB0_L1TLB_REG_RW_3_3 0x00a4 37 #define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX 1 38 #define regDAGB1_L1TLB_REG_RW_3_3 0x0163 39 #define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX 1 40 41 static const char *mmhub_client_ids_v3_3[][2] = { 42 [0][0] = "VMC", 43 [1][0] = "ISPXT", 44 [2][0] = "ISPIXT", 45 [4][0] = "DCEDMC", 46 [6][0] = "MP0", 47 [7][0] = "MP1", 48 [8][0] = "MPM", 49 [9][0] = "ISPPDPRD", 50 [10][0] = "ISPCSTATRD", 51 [11][0] = "ISPBYRPRD", 52 [12][0] = "ISPRGBPRD", 53 [13][0] = "ISPMCFPRD", 54 [14][0] = "ISPMCFPRD1", 55 [15][0] = "ISPYUVPRD", 56 [16][0] = "ISPMCSCRD", 57 [17][0] = "ISPGDCRD", 58 [18][0] = "ISPLMERD", 59 [22][0] = "ISPXT1", 60 [23][0] = "ISPIXT1", 61 [24][0] = "HDP", 62 [25][0] = "LSDMA", 63 [26][0] = "JPEG", 64 [27][0] = "VPE", 65 [28][0] = "VSCH", 66 [29][0] = "VCNU", 67 [30][0] = "VCN", 68 [1][1] = "ISPXT", 69 [2][1] = "ISPIXT", 70 [3][1] = "DCEDWB", 71 [4][1] = "DCEDMC", 72 [5][1] = "ISPCSISWR", 73 [6][1] = "MP0", 74 [7][1] = "MP1", 75 [8][1] = "MPM", 76 [9][1] = "ISPPDPWR", 77 [10][1] = "ISPCSTATWR", 78 [11][1] = "ISPBYRPWR", 79 [12][1] = "ISPRGBPWR", 80 [13][1] = "ISPMCFPWR", 81 [14][1] = "ISPMWR0", 82 [15][1] = "ISPYUVPWR", 83 [16][1] = "ISPMCSCWR", 84 [17][1] = "ISPGDCWR", 85 [18][1] = "ISPLMEWR", 86 [20][1] = "ISPMWR2", 87 [21][1] = "OSSSYS", 88 [22][1] = "ISPXT1", 89 [23][1] = "ISPIXT1", 90 [24][1] = "HDP", 91 [25][1] = "LSDMA", 92 [26][1] = "JPEG", 93 [27][1] = "VPE", 94 [28][1] = "VSCH", 95 [29][1] = "VCNU", 96 [30][1] = "VCN", 97 }; 98 99 static const char *mmhub_client_ids_v3_3_1[][2] = { 100 [0][0] = "VMC", 101 [4][0] = "DCEDMC", 102 [6][0] = "MP0", 103 [7][0] = "MP1", 104 [8][0] = "MPM", 105 [24][0] = "HDP", 106 [25][0] = "LSDMA", 107 [26][0] = "JPEG0", 108 [27][0] = "VPE0", 109 [28][0] = "VSCH", 110 [29][0] = "VCNU0", 111 [30][0] = "VCN0", 112 [32+1][0] = "ISPXT", 113 [32+2][0] = "ISPIXT", 114 [32+9][0] = "ISPPDPRD", 115 [32+10][0] = "ISPCSTATRD", 116 [32+11][0] = "ISPBYRPRD", 117 [32+12][0] = "ISPRGBPRD", 118 [32+13][0] = "ISPMCFPRD", 119 [32+14][0] = "ISPMCFPRD1", 120 [32+15][0] = "ISPYUVPRD", 121 [32+16][0] = "ISPMCSCRD", 122 [32+17][0] = "ISPGDCRD", 123 [32+18][0] = "ISPLMERD", 124 [32+22][0] = "ISPXT1", 125 [32+23][0] = "ISPIXT1", 126 [32+26][0] = "JPEG1", 127 [32+27][0] = "VPE1", 128 [32+29][0] = "VCNU1", 129 [32+30][0] = "VCN1", 130 [3][1] = "DCEDWB", 131 [4][1] = "DCEDMC", 132 [6][1] = "MP0", 133 [7][1] = "MP1", 134 [8][1] = "MPM", 135 [21][1] = "OSSSYS", 136 [24][1] = "HDP", 137 [25][1] = "LSDMA", 138 [26][1] = "JPEG0", 139 [27][1] = "VPE0", 140 [28][1] = "VSCH", 141 [29][1] = "VCNU0", 142 [30][1] = "VCN0", 143 [32+1][1] = "ISPXT", 144 [32+2][1] = "ISPIXT", 145 [32+5][1] = "ISPCSISWR", 146 [32+9][1] = "ISPPDPWR", 147 [32+10][1] = "ISPCSTATWR", 148 [32+11][1] = "ISPBYRPWR", 149 [32+12][1] = "ISPRGBPWR", 150 [32+13][1] = "ISPMCFPWR", 151 [32+14][1] = "ISPMWR0", 152 [32+15][1] = "ISPYUVPWR", 153 [32+16][1] = "ISPMCSCWR", 154 [32+17][1] = "ISPGDCWR", 155 [32+18][1] = "ISPLMEWR", 156 [32+19][1] = "ISPMWR1", 157 [32+20][1] = "ISPMWR2", 158 [32+22][1] = "ISPXT1", 159 [32+23][1] = "ISPIXT1", 160 [32+26][1] = "JPEG1", 161 [32+27][1] = "VPE1", 162 [32+29][1] = "VCNU1", 163 [32+30][1] = "VCN1", 164 }; 165 166 static const char *mmhub_client_ids_v3_4[][2] = { 167 [0][0] = "VMC", 168 [4][0] = "DCEDMC", 169 [5][0] = "MPXSP", 170 [6][0] = "MPASP", 171 [7][0] = "MP1", 172 [8][0] = "MPM", 173 [23][0] = "HDP", 174 [24][0] = "LSDMA", 175 [25][0] = "JPEG", 176 [26][0] = "VPE", 177 [27][0] = "VSCH", 178 [28][0] = "VCNU", 179 [30][0] = "VCNRD", 180 [3][1] = "DCEDWB", 181 [4][1] = "DCEDMC", 182 [5][1] = "MPXSP", 183 [6][1] = "MPASAP", 184 [7][1] = "MP1", 185 [8][1] = "MPM", 186 [21][1] = "OSSSYS", 187 [23][1] = "HDP", 188 [24][1] = "LSDMA", 189 [25][1] = "JPEG", 190 [26][1] = "VPE", 191 [27][1] = "VSCH", 192 [29][1] = "VCNWR", 193 }; 194 195 static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, 196 uint32_t flush_type) 197 { 198 u32 req = 0; 199 200 /* invalidate using legacy mode on vmid*/ 201 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 202 PER_VMID_INVALIDATE_REQ, 1 << vmid); 203 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1); 204 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 205 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 206 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 207 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 208 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 209 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 210 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 211 212 return req; 213 } 214 215 static void 216 mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 217 uint32_t status) 218 { 219 uint32_t cid, rw; 220 const char *mmhub_cid = NULL; 221 222 cid = REG_GET_FIELD(status, 223 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 224 rw = REG_GET_FIELD(status, 225 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 226 227 dev_err(adev->dev, 228 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 229 status); 230 231 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 232 case IP_VERSION(3, 3, 0): 233 case IP_VERSION(3, 3, 2): 234 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? 235 mmhub_client_ids_v3_3[cid][rw] : 236 cid == 0x140 ? "UMSCH" : NULL; 237 break; 238 case IP_VERSION(3, 3, 1): 239 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3_1) ? 240 mmhub_client_ids_v3_3_1[cid][rw] : 241 cid == 0x140 ? "UMSCH" : NULL; 242 break; 243 case IP_VERSION(3, 4, 0): 244 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_4) ? 245 mmhub_client_ids_v3_4[cid][rw] : 246 cid == 0x140 ? "UMSCH" : NULL; 247 break; 248 default: 249 mmhub_cid = NULL; 250 break; 251 } 252 253 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 254 mmhub_cid ? mmhub_cid : "unknown", cid); 255 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 256 REG_GET_FIELD(status, 257 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 258 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 259 REG_GET_FIELD(status, 260 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 261 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 262 REG_GET_FIELD(status, 263 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 264 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 265 REG_GET_FIELD(status, 266 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 267 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 268 } 269 270 static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, 271 uint32_t vmid, 272 uint64_t page_table_base) 273 { 274 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 275 276 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 277 hub->ctx_addr_distance * vmid, 278 lower_32_bits(page_table_base)); 279 280 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 281 hub->ctx_addr_distance * vmid, 282 upper_32_bits(page_table_base)); 283 284 } 285 286 static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) 287 { 288 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 289 290 mmhub_v3_3_setup_vm_pt_regs(adev, 0, pt_base); 291 292 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 293 (u32)(adev->gmc.gart_start >> 12)); 294 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 295 (u32)(adev->gmc.gart_start >> 44)); 296 297 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 298 (u32)(adev->gmc.gart_end >> 12)); 299 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 300 (u32)(adev->gmc.gart_end >> 44)); 301 } 302 303 static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) 304 { 305 uint64_t value; 306 uint32_t tmp; 307 308 /* Program the AGP BAR */ 309 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 310 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 311 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 312 313 /* 314 * the new L1 policy will block SRIOV guest from writing 315 * these regs, and they will be programed at host. 316 * so skip programing these regs. 317 */ 318 /* Program the system aperture low logical page number. */ 319 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 320 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 321 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 322 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 323 324 /* Set default page address. */ 325 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 326 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 327 (u32)(value >> 12)); 328 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 329 (u32)(value >> 44)); 330 331 /* Program "protection fault". */ 332 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 333 (u32)(adev->dummy_page_addr >> 12)); 334 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 335 (u32)((u64)adev->dummy_page_addr >> 44)); 336 337 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 338 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 339 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 340 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 341 } 342 343 static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) 344 { 345 uint32_t tmp; 346 347 /* Setup TLB control */ 348 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 349 350 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 351 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 352 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 353 ENABLE_ADVANCED_DRIVER_MODEL, 1); 354 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 355 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 356 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 357 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 358 MTYPE, MTYPE_UC); /* UC, uncached */ 359 360 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 361 } 362 363 static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) 364 { 365 uint32_t tmp; 366 367 /* Setup L2 cache */ 368 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 369 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 370 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 371 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 372 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 373 /* XXX for emulation, Refer to closed source code.*/ 374 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 375 0); 376 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 377 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 378 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 379 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 380 381 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 382 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 383 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 384 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 385 386 tmp = regMMVM_L2_CNTL3_DEFAULT; 387 if (adev->gmc.translate_further) { 388 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 389 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 390 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 391 } else { 392 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 393 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 394 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 395 } 396 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 397 398 tmp = regMMVM_L2_CNTL4_DEFAULT; 399 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 400 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 401 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 402 403 tmp = regMMVM_L2_CNTL5_DEFAULT; 404 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 405 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 406 } 407 408 static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) 409 { 410 uint32_t tmp; 411 412 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 413 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 414 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 415 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 416 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 417 418 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 419 } 420 421 static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) 422 { 423 WREG32_SOC15(MMHUB, 0, 424 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 425 0xFFFFFFFF); 426 WREG32_SOC15(MMHUB, 0, 427 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 428 0x0000000F); 429 430 WREG32_SOC15(MMHUB, 0, 431 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 432 WREG32_SOC15(MMHUB, 0, 433 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 434 435 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 436 0); 437 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 438 0); 439 } 440 441 static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) 442 { 443 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 444 int i; 445 uint32_t tmp; 446 447 for (i = 0; i <= 14; i++) { 448 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 449 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 450 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 451 adev->vm_manager.num_level); 452 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 453 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 454 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 455 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 456 1); 457 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 458 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 459 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 460 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 461 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 462 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 463 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 464 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 465 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 466 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 467 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 468 PAGE_TABLE_BLOCK_SIZE, 469 adev->vm_manager.block_size - 9); 470 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 471 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 472 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 473 !amdgpu_noretry); 474 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 475 i * hub->ctx_distance, tmp); 476 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 477 i * hub->ctx_addr_distance, 0); 478 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 479 i * hub->ctx_addr_distance, 0); 480 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 481 i * hub->ctx_addr_distance, 482 lower_32_bits(adev->vm_manager.max_pfn - 1)); 483 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 484 i * hub->ctx_addr_distance, 485 upper_32_bits(adev->vm_manager.max_pfn - 1)); 486 } 487 488 hub->vm_cntx_cntl = tmp; 489 } 490 491 static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) 492 { 493 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 494 unsigned int i; 495 496 for (i = 0; i < 18; ++i) { 497 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 498 i * hub->eng_addr_distance, 0xffffffff); 499 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 500 i * hub->eng_addr_distance, 0x1f); 501 } 502 } 503 504 static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) 505 { 506 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 507 uint32_t tmp; 508 509 /* Program page table base, gart start, gart end */ 510 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 511 lower_32_bits(pt_base >> 12)); 512 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 513 upper_32_bits(pt_base >> 12)); 514 515 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 516 (u32)(adev->gmc.gart_start >> 12)); 517 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 518 (u32)(adev->gmc.gart_start >> 44)); 519 520 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 521 (u32)(adev->gmc.gart_end >> 12)); 522 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 523 (u32)(adev->gmc.gart_end >> 44)); 524 525 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL); 526 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 527 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 528 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp); 529 530 /* Disable all contexts except context 0 */ 531 tmp = 0xfffe; 532 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp); 533 534 /* Program saw cntl4 */ 535 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); 536 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1); 537 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1); 538 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp); 539 } 540 541 static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev) 542 { 543 WREG32_SOC15(MMHUB, 0, regDAGB0_L1TLB_REG_RW_3_3, 0); 544 WREG32_SOC15(MMHUB, 0, regDAGB1_L1TLB_REG_RW_3_3, 3); 545 } 546 547 static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) 548 { 549 /* GART Enable. */ 550 mmhub_v3_3_init_gart_aperture_regs(adev); 551 mmhub_v3_3_init_system_aperture_regs(adev); 552 mmhub_v3_3_init_tlb_regs(adev); 553 mmhub_v3_3_init_cache_regs(adev); 554 555 mmhub_v3_3_enable_system_domain(adev); 556 mmhub_v3_3_disable_identity_aperture(adev); 557 mmhub_v3_3_setup_vmid_config(adev); 558 mmhub_v3_3_program_invalidation(adev); 559 560 /* standalone alone walker init */ 561 mmhub_v3_3_init_saw_regs(adev); 562 563 /* enable mmhub tls */ 564 mmhub_v3_3_enable_tls(adev); 565 566 return 0; 567 } 568 569 static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) 570 { 571 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 572 u32 tmp; 573 u32 i; 574 575 /* Disable all tables */ 576 for (i = 0; i < 16; i++) 577 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 578 i * hub->ctx_distance, 0); 579 580 /* Setup TLB control */ 581 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 582 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 583 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 584 ENABLE_ADVANCED_DRIVER_MODEL, 0); 585 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 586 587 /* Setup L2 cache */ 588 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 589 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 590 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 591 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 592 } 593 594 /** 595 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling 596 * 597 * @adev: amdgpu_device pointer 598 * @value: true redirects VM faults to the default page 599 */ 600 static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, 601 bool value) 602 { 603 u32 tmp; 604 605 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 606 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 607 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 608 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 609 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 610 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 611 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 612 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 613 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 614 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 615 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 616 value); 617 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 618 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 619 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 620 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 621 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 622 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 623 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 624 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 625 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 626 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 627 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 628 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 629 if (!value) { 630 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 631 CRASH_ON_NO_RETRY_FAULT, 1); 632 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 633 CRASH_ON_RETRY_FAULT, 1); 634 } 635 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 636 } 637 638 static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { 639 .print_l2_protection_fault_status = mmhub_v3_3_print_l2_protection_fault_status, 640 .get_invalidate_req = mmhub_v3_3_get_invalidate_req, 641 }; 642 643 static void mmhub_v3_3_init(struct amdgpu_device *adev) 644 { 645 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 646 647 hub->ctx0_ptb_addr_lo32 = 648 SOC15_REG_OFFSET(MMHUB, 0, 649 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 650 hub->ctx0_ptb_addr_hi32 = 651 SOC15_REG_OFFSET(MMHUB, 0, 652 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 653 hub->vm_inv_eng0_sem = 654 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 655 hub->vm_inv_eng0_req = 656 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 657 hub->vm_inv_eng0_ack = 658 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 659 hub->vm_context0_cntl = 660 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 661 hub->vm_l2_pro_fault_status = 662 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 663 hub->vm_l2_pro_fault_cntl = 664 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 665 666 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 667 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 668 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 669 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 670 regMMVM_INVALIDATE_ENG0_REQ; 671 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 672 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 673 674 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 675 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 676 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 677 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 678 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 679 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 680 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 681 682 hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; 683 } 684 685 static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) 686 { 687 u64 base; 688 689 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 690 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 691 base <<= 24; 692 693 return base; 694 } 695 696 static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) 697 { 698 u64 offset; 699 700 offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); 701 offset &= MMMC_VM_FB_OFFSET__FB_OFFSET_MASK; 702 offset <<= 24; 703 704 return offset; 705 } 706 707 static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 708 bool enable) 709 { 710 uint32_t def, data; 711 712 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 713 714 if (enable) 715 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 716 else 717 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 718 719 if (def != data) 720 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 721 } 722 723 static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 724 bool enable) 725 { 726 uint32_t def, data; 727 728 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 729 730 if (enable) 731 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 732 else 733 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 734 735 if (def != data) 736 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 737 } 738 739 static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, 740 enum amd_clockgating_state state) 741 { 742 if (amdgpu_sriov_vf(adev)) 743 return 0; 744 745 mmhub_v3_3_update_medium_grain_clock_gating(adev, 746 state == AMD_CG_STATE_GATE); 747 mmhub_v3_3_update_medium_grain_light_sleep(adev, 748 state == AMD_CG_STATE_GATE); 749 return 0; 750 } 751 752 static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) 753 { 754 u32 data; 755 756 if (amdgpu_sriov_vf(adev)) 757 *flags = 0; 758 759 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 760 761 /* AMD_CG_SUPPORT_MC_MGCG */ 762 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 763 *flags |= AMD_CG_SUPPORT_MC_MGCG; 764 765 /* AMD_CG_SUPPORT_MC_LS */ 766 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 767 *flags |= AMD_CG_SUPPORT_MC_LS; 768 } 769 770 const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = { 771 .init = mmhub_v3_3_init, 772 .get_fb_location = mmhub_v3_3_get_fb_location, 773 .get_mc_fb_offset = mmhub_v3_3_get_mc_fb_offset, 774 .gart_enable = mmhub_v3_3_gart_enable, 775 .set_fault_enable_default = mmhub_v3_3_set_fault_enable_default, 776 .gart_disable = mmhub_v3_3_gart_disable, 777 .set_clockgating = mmhub_v3_3_set_clockgating, 778 .get_clockgating = mmhub_v3_3_get_clockgating, 779 .setup_vm_pt_regs = mmhub_v3_3_setup_vm_pt_regs, 780 }; 781