1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_3.h" 26 27 #include "mmhub/mmhub_3_3_0_offset.h" 28 #include "mmhub/mmhub_3_3_0_sh_mask.h" 29 30 #include "navi10_enum.h" 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 #define regDAGB0_L1TLB_REG_RW_3_3 0x00a4 37 #define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX 1 38 #define regDAGB1_L1TLB_REG_RW_3_3 0x0163 39 #define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX 1 40 41 static const char *mmhub_client_ids_v3_3[][2] = { 42 [0][0] = "VMC", 43 [4][0] = "DCEDMC", 44 [6][0] = "MP0", 45 [7][0] = "MP1", 46 [8][0] = "MPM", 47 [24][0] = "HDP", 48 [25][0] = "LSDMA", 49 [26][0] = "JPEG", 50 [27][0] = "VPE", 51 [29][0] = "VCNU", 52 [30][0] = "VCN", 53 [3][1] = "DCEDWB", 54 [4][1] = "DCEDMC", 55 [6][1] = "MP0", 56 [7][1] = "MP1", 57 [8][1] = "MPM", 58 [21][1] = "OSSSYS", 59 [24][1] = "HDP", 60 [25][1] = "LSDMA", 61 [26][1] = "JPEG", 62 [27][1] = "VPE", 63 [29][1] = "VCNU", 64 [30][1] = "VCN", 65 }; 66 67 static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, 68 uint32_t flush_type) 69 { 70 u32 req = 0; 71 72 /* invalidate using legacy mode on vmid*/ 73 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 74 PER_VMID_INVALIDATE_REQ, 1 << vmid); 75 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1); 76 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 77 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 78 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 79 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 80 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 82 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 83 84 return req; 85 } 86 87 static void 88 mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 89 uint32_t status) 90 { 91 uint32_t cid, rw; 92 const char *mmhub_cid = NULL; 93 94 cid = REG_GET_FIELD(status, 95 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 96 rw = REG_GET_FIELD(status, 97 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 98 99 dev_err(adev->dev, 100 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 101 status); 102 103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 104 case IP_VERSION(3, 3, 0): 105 case IP_VERSION(3, 3, 1): 106 mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? 107 mmhub_client_ids_v3_3[cid][rw] : 108 cid == 0x140 ? "UMSCH" : NULL; 109 break; 110 default: 111 mmhub_cid = NULL; 112 break; 113 } 114 115 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 116 mmhub_cid ? mmhub_cid : "unknown", cid); 117 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 118 REG_GET_FIELD(status, 119 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 120 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 121 REG_GET_FIELD(status, 122 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 123 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 124 REG_GET_FIELD(status, 125 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 126 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 127 REG_GET_FIELD(status, 128 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 129 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 130 } 131 132 static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, 133 uint32_t vmid, 134 uint64_t page_table_base) 135 { 136 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 137 138 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 139 hub->ctx_addr_distance * vmid, 140 lower_32_bits(page_table_base)); 141 142 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 143 hub->ctx_addr_distance * vmid, 144 upper_32_bits(page_table_base)); 145 146 } 147 148 static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) 149 { 150 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 151 152 mmhub_v3_3_setup_vm_pt_regs(adev, 0, pt_base); 153 154 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 155 (u32)(adev->gmc.gart_start >> 12)); 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 157 (u32)(adev->gmc.gart_start >> 44)); 158 159 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 160 (u32)(adev->gmc.gart_end >> 12)); 161 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 162 (u32)(adev->gmc.gart_end >> 44)); 163 } 164 165 static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) 166 { 167 uint64_t value; 168 uint32_t tmp; 169 170 /* Program the AGP BAR */ 171 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 172 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 174 175 /* 176 * the new L1 policy will block SRIOV guest from writing 177 * these regs, and they will be programed at host. 178 * so skip programing these regs. 179 */ 180 /* Program the system aperture low logical page number. */ 181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 182 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 184 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 185 186 /* Set default page address. */ 187 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 188 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 189 (u32)(value >> 12)); 190 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 191 (u32)(value >> 44)); 192 193 /* Program "protection fault". */ 194 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 195 (u32)(adev->dummy_page_addr >> 12)); 196 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 197 (u32)((u64)adev->dummy_page_addr >> 44)); 198 199 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 200 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 201 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 202 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 203 } 204 205 static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) 206 { 207 uint32_t tmp; 208 209 /* Setup TLB control */ 210 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 211 212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 215 ENABLE_ADVANCED_DRIVER_MODEL, 1); 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 217 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 220 MTYPE, MTYPE_UC); /* UC, uncached */ 221 222 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 223 } 224 225 static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) 226 { 227 uint32_t tmp; 228 229 /* Setup L2 cache */ 230 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 231 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 232 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 234 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 235 /* XXX for emulation, Refer to closed source code.*/ 236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 237 0); 238 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 239 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 240 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 241 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 242 243 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 245 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 246 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 247 248 tmp = regMMVM_L2_CNTL3_DEFAULT; 249 if (adev->gmc.translate_further) { 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 252 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 253 } else { 254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 256 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 257 } 258 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 259 260 tmp = regMMVM_L2_CNTL4_DEFAULT; 261 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 262 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 263 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 264 265 tmp = regMMVM_L2_CNTL5_DEFAULT; 266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 267 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 268 } 269 270 static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) 271 { 272 uint32_t tmp; 273 274 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 275 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 276 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 277 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 278 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 279 280 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 281 } 282 283 static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) 284 { 285 WREG32_SOC15(MMHUB, 0, 286 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 287 0xFFFFFFFF); 288 WREG32_SOC15(MMHUB, 0, 289 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 290 0x0000000F); 291 292 WREG32_SOC15(MMHUB, 0, 293 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 294 WREG32_SOC15(MMHUB, 0, 295 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 296 297 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 298 0); 299 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 300 0); 301 } 302 303 static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) 304 { 305 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 306 int i; 307 uint32_t tmp; 308 309 for (i = 0; i <= 14; i++) { 310 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 311 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 312 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 313 adev->vm_manager.num_level); 314 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 315 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 316 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 317 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 318 1); 319 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 320 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 322 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 323 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 324 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 325 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 326 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 327 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 328 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 329 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 330 PAGE_TABLE_BLOCK_SIZE, 331 adev->vm_manager.block_size - 9); 332 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 333 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 334 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 335 !amdgpu_noretry); 336 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 337 i * hub->ctx_distance, tmp); 338 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 339 i * hub->ctx_addr_distance, 0); 340 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 341 i * hub->ctx_addr_distance, 0); 342 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 343 i * hub->ctx_addr_distance, 344 lower_32_bits(adev->vm_manager.max_pfn - 1)); 345 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 346 i * hub->ctx_addr_distance, 347 upper_32_bits(adev->vm_manager.max_pfn - 1)); 348 } 349 350 hub->vm_cntx_cntl = tmp; 351 } 352 353 static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) 354 { 355 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 356 unsigned int i; 357 358 for (i = 0; i < 18; ++i) { 359 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 360 i * hub->eng_addr_distance, 0xffffffff); 361 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 362 i * hub->eng_addr_distance, 0x1f); 363 } 364 } 365 366 static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) 367 { 368 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 369 uint32_t tmp; 370 371 /* Program page table base, gart start, gart end */ 372 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 373 lower_32_bits(pt_base >> 12)); 374 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 375 upper_32_bits(pt_base >> 12)); 376 377 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 378 (u32)(adev->gmc.gart_start >> 12)); 379 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 380 (u32)(adev->gmc.gart_start >> 44)); 381 382 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 383 (u32)(adev->gmc.gart_end >> 12)); 384 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 385 (u32)(adev->gmc.gart_end >> 44)); 386 387 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL); 388 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 389 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 390 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp); 391 392 /* Disable all contexts except context 0 */ 393 tmp = 0xfffe; 394 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp); 395 396 /* Program saw cntl4 */ 397 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); 398 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1); 399 tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1); 400 WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp); 401 } 402 403 static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev) 404 { 405 WREG32_SOC15(MMHUB, 0, regDAGB0_L1TLB_REG_RW_3_3, 0); 406 WREG32_SOC15(MMHUB, 0, regDAGB1_L1TLB_REG_RW_3_3, 3); 407 } 408 409 static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) 410 { 411 /* GART Enable. */ 412 mmhub_v3_3_init_gart_aperture_regs(adev); 413 mmhub_v3_3_init_system_aperture_regs(adev); 414 mmhub_v3_3_init_tlb_regs(adev); 415 mmhub_v3_3_init_cache_regs(adev); 416 417 mmhub_v3_3_enable_system_domain(adev); 418 mmhub_v3_3_disable_identity_aperture(adev); 419 mmhub_v3_3_setup_vmid_config(adev); 420 mmhub_v3_3_program_invalidation(adev); 421 422 /* standalone alone walker init */ 423 mmhub_v3_3_init_saw_regs(adev); 424 425 /* enable mmhub tls */ 426 mmhub_v3_3_enable_tls(adev); 427 428 return 0; 429 } 430 431 static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) 432 { 433 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 434 u32 tmp; 435 u32 i; 436 437 /* Disable all tables */ 438 for (i = 0; i < 16; i++) 439 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 440 i * hub->ctx_distance, 0); 441 442 /* Setup TLB control */ 443 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 444 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 445 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 446 ENABLE_ADVANCED_DRIVER_MODEL, 0); 447 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 448 449 /* Setup L2 cache */ 450 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 451 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 452 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 453 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 454 } 455 456 /** 457 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling 458 * 459 * @adev: amdgpu_device pointer 460 * @value: true redirects VM faults to the default page 461 */ 462 static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, 463 bool value) 464 { 465 u32 tmp; 466 467 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 468 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 469 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 470 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 471 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 472 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 473 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 474 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 475 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 476 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 477 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 478 value); 479 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 480 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 481 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 482 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 483 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 484 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 485 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 486 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 487 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 488 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 489 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 490 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 491 if (!value) { 492 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 493 CRASH_ON_NO_RETRY_FAULT, 1); 494 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 495 CRASH_ON_RETRY_FAULT, 1); 496 } 497 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 498 } 499 500 static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { 501 .print_l2_protection_fault_status = mmhub_v3_3_print_l2_protection_fault_status, 502 .get_invalidate_req = mmhub_v3_3_get_invalidate_req, 503 }; 504 505 static void mmhub_v3_3_init(struct amdgpu_device *adev) 506 { 507 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 508 509 hub->ctx0_ptb_addr_lo32 = 510 SOC15_REG_OFFSET(MMHUB, 0, 511 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 512 hub->ctx0_ptb_addr_hi32 = 513 SOC15_REG_OFFSET(MMHUB, 0, 514 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 515 hub->vm_inv_eng0_sem = 516 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 517 hub->vm_inv_eng0_req = 518 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 519 hub->vm_inv_eng0_ack = 520 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 521 hub->vm_context0_cntl = 522 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 523 hub->vm_l2_pro_fault_status = 524 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 525 hub->vm_l2_pro_fault_cntl = 526 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 527 528 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 529 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 530 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 531 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 532 regMMVM_INVALIDATE_ENG0_REQ; 533 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 534 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 535 536 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 537 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 538 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 539 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 540 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 541 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 542 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 543 544 hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; 545 } 546 547 static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) 548 { 549 u64 base; 550 551 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 552 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 553 base <<= 24; 554 555 return base; 556 } 557 558 static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) 559 { 560 u64 offset; 561 562 offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); 563 offset &= MMMC_VM_FB_OFFSET__FB_OFFSET_MASK; 564 offset <<= 24; 565 566 return offset; 567 } 568 569 static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 570 bool enable) 571 { 572 uint32_t def, data; 573 574 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 575 576 if (enable) 577 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 578 else 579 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 580 581 if (def != data) 582 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 583 } 584 585 static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 586 bool enable) 587 { 588 uint32_t def, data; 589 590 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 591 592 if (enable) 593 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 594 else 595 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 596 597 if (def != data) 598 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 599 } 600 601 static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, 602 enum amd_clockgating_state state) 603 { 604 if (amdgpu_sriov_vf(adev)) 605 return 0; 606 607 mmhub_v3_3_update_medium_grain_clock_gating(adev, 608 state == AMD_CG_STATE_GATE); 609 mmhub_v3_3_update_medium_grain_light_sleep(adev, 610 state == AMD_CG_STATE_GATE); 611 return 0; 612 } 613 614 static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) 615 { 616 u32 data; 617 618 if (amdgpu_sriov_vf(adev)) 619 *flags = 0; 620 621 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 622 623 /* AMD_CG_SUPPORT_MC_MGCG */ 624 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 625 *flags |= AMD_CG_SUPPORT_MC_MGCG; 626 627 /* AMD_CG_SUPPORT_MC_LS */ 628 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 629 *flags |= AMD_CG_SUPPORT_MC_LS; 630 } 631 632 const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = { 633 .init = mmhub_v3_3_init, 634 .get_fb_location = mmhub_v3_3_get_fb_location, 635 .get_mc_fb_offset = mmhub_v3_3_get_mc_fb_offset, 636 .gart_enable = mmhub_v3_3_gart_enable, 637 .set_fault_enable_default = mmhub_v3_3_set_fault_enable_default, 638 .gart_disable = mmhub_v3_3_gart_disable, 639 .set_clockgating = mmhub_v3_3_set_clockgating, 640 .get_clockgating = mmhub_v3_3_get_clockgating, 641 .setup_vm_pt_regs = mmhub_v3_3_setup_vm_pt_regs, 642 }; 643