1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_0_1.h" 26 27 #include "mmhub/mmhub_3_0_1_offset.h" 28 #include "mmhub/mmhub_3_0_1_sh_mask.h" 29 #include "navi10_enum.h" 30 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37 static const char *mmhub_client_ids_v3_0_1[][2] = { 38 [0][0] = "VMC", 39 [1][0] = "ISPXT", 40 [2][0] = "ISPIXT", 41 [4][0] = "DCEDMC", 42 [5][0] = "DCEVGA", 43 [6][0] = "MP0", 44 [7][0] = "MP1", 45 [8][0] = "MPM", 46 [12][0] = "ISPTNR", 47 [14][0] = "ISPCRD0", 48 [15][0] = "ISPCRD1", 49 [16][0] = "ISPCRD2", 50 [22][0] = "HDP", 51 [23][0] = "LSDMA", 52 [24][0] = "JPEG", 53 [27][0] = "VSCH", 54 [28][0] = "VCNU", 55 [29][0] = "VCN", 56 [1][1] = "ISPXT", 57 [2][1] = "ISPIXT", 58 [3][1] = "DCEDWB", 59 [4][1] = "DCEDMC", 60 [5][1] = "DCEVGA", 61 [6][1] = "MP0", 62 [7][1] = "MP1", 63 [8][1] = "MPM", 64 [10][1] = "ISPMWR0", 65 [11][1] = "ISPMWR1", 66 [12][1] = "ISPTNR", 67 [13][1] = "ISPSWR", 68 [14][1] = "ISPCWR0", 69 [15][1] = "ISPCWR1", 70 [16][1] = "ISPCWR2", 71 [17][1] = "ISPCWR3", 72 [18][1] = "XDP", 73 [21][1] = "OSSSYS", 74 [22][1] = "HDP", 75 [23][1] = "LSDMA", 76 [24][1] = "JPEG", 77 [27][1] = "VSCH", 78 [28][1] = "VCNU", 79 [29][1] = "VCN", 80 }; 81 82 static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid, 83 uint32_t flush_type) 84 { 85 u32 req = 0; 86 87 /* invalidate using legacy mode on vmid*/ 88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 89 PER_VMID_INVALIDATE_REQ, 1 << vmid); 90 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 91 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 92 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 93 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 94 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 95 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 96 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 97 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 98 99 return req; 100 } 101 102 static void 103 mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 104 uint32_t status) 105 { 106 uint32_t cid, rw; 107 const char *mmhub_cid = NULL; 108 109 cid = REG_GET_FIELD(status, 110 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 111 rw = REG_GET_FIELD(status, 112 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 113 114 dev_err(adev->dev, 115 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 116 status); 117 118 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 119 case IP_VERSION(3, 0, 1): 120 mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw]; 121 break; 122 default: 123 mmhub_cid = NULL; 124 break; 125 } 126 127 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 128 mmhub_cid ? mmhub_cid : "unknown", cid); 129 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 130 REG_GET_FIELD(status, 131 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 132 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 133 REG_GET_FIELD(status, 134 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 135 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 136 REG_GET_FIELD(status, 137 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 138 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 139 REG_GET_FIELD(status, 140 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 141 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 142 } 143 144 static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev, 145 uint32_t vmid, 146 uint64_t page_table_base) 147 { 148 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 149 150 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 151 hub->ctx_addr_distance * vmid, 152 lower_32_bits(page_table_base)); 153 154 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 155 hub->ctx_addr_distance * vmid, 156 upper_32_bits(page_table_base)); 157 } 158 159 static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev) 160 { 161 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 162 163 mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base); 164 165 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 166 (u32)(adev->gmc.gart_start >> 12)); 167 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 168 (u32)(adev->gmc.gart_start >> 44)); 169 170 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 171 (u32)(adev->gmc.gart_end >> 12)); 172 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 173 (u32)(adev->gmc.gart_end >> 44)); 174 } 175 176 static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev) 177 { 178 uint64_t value; 179 uint32_t tmp; 180 181 /* Program the AGP BAR */ 182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 184 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 185 186 /* 187 * the new L1 policy will block SRIOV guest from writing 188 * these regs, and they will be programed at host. 189 * so skip programing these regs. 190 */ 191 /* Program the system aperture low logical page number. */ 192 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 193 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 194 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 195 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 196 197 /* Set default page address. */ 198 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 199 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 200 (u32)(value >> 12)); 201 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 202 (u32)(value >> 44)); 203 204 /* Program "protection fault". */ 205 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 206 (u32)(adev->dummy_page_addr >> 12)); 207 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 208 (u32)((u64)adev->dummy_page_addr >> 44)); 209 210 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 211 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 212 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 213 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 214 } 215 216 static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev) 217 { 218 uint32_t tmp; 219 220 /* Setup TLB control */ 221 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 222 223 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 224 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 225 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 226 ENABLE_ADVANCED_DRIVER_MODEL, 1); 227 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 228 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 229 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 230 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 231 MTYPE, MTYPE_UC); /* UC, uncached */ 232 233 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 234 } 235 236 static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev) 237 { 238 uint32_t tmp; 239 240 /* Setup L2 cache */ 241 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 245 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 246 /* XXX for emulation, Refer to closed source code.*/ 247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 248 0); 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 252 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 253 254 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 257 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 258 259 tmp = regMMVM_L2_CNTL3_DEFAULT; 260 if (adev->gmc.translate_further) { 261 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 262 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 263 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 264 } else { 265 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 267 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 268 } 269 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 270 271 tmp = regMMVM_L2_CNTL4_DEFAULT; 272 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 273 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 274 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 275 276 tmp = regMMVM_L2_CNTL5_DEFAULT; 277 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 278 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 279 } 280 281 static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev) 282 { 283 uint32_t tmp; 284 285 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 286 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 287 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 288 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 289 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 290 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 291 } 292 293 static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev) 294 { 295 WREG32_SOC15(MMHUB, 0, 296 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 297 0xFFFFFFFF); 298 WREG32_SOC15(MMHUB, 0, 299 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 300 0x0000000F); 301 302 WREG32_SOC15(MMHUB, 0, 303 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 304 WREG32_SOC15(MMHUB, 0, 305 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 306 307 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 308 0); 309 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 310 0); 311 } 312 313 static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev) 314 { 315 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 316 int i; 317 uint32_t tmp; 318 319 for (i = 0; i <= 14; i++) { 320 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 323 adev->vm_manager.num_level); 324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 325 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 327 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 328 1); 329 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 330 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 331 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 332 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 333 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 334 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 336 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 337 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 338 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 339 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 340 PAGE_TABLE_BLOCK_SIZE, 341 adev->vm_manager.block_size - 9); 342 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 343 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 344 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 345 !amdgpu_noretry); 346 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 347 i * hub->ctx_distance, tmp); 348 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 349 i * hub->ctx_addr_distance, 0); 350 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 351 i * hub->ctx_addr_distance, 0); 352 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 353 i * hub->ctx_addr_distance, 354 lower_32_bits(adev->vm_manager.max_pfn - 1)); 355 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 356 i * hub->ctx_addr_distance, 357 upper_32_bits(adev->vm_manager.max_pfn - 1)); 358 } 359 360 hub->vm_cntx_cntl = tmp; 361 } 362 363 static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev) 364 { 365 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 366 unsigned i; 367 368 for (i = 0; i < 18; ++i) { 369 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 370 i * hub->eng_addr_distance, 0xffffffff); 371 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 372 i * hub->eng_addr_distance, 0x1f); 373 } 374 } 375 376 static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev) 377 { 378 /* GART Enable. */ 379 mmhub_v3_0_1_init_gart_aperture_regs(adev); 380 mmhub_v3_0_1_init_system_aperture_regs(adev); 381 mmhub_v3_0_1_init_tlb_regs(adev); 382 mmhub_v3_0_1_init_cache_regs(adev); 383 384 mmhub_v3_0_1_enable_system_domain(adev); 385 mmhub_v3_0_1_disable_identity_aperture(adev); 386 mmhub_v3_0_1_setup_vmid_config(adev); 387 mmhub_v3_0_1_program_invalidation(adev); 388 389 return 0; 390 } 391 392 static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev) 393 { 394 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 395 u32 tmp; 396 u32 i; 397 398 /* Disable all tables */ 399 for (i = 0; i < 16; i++) 400 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 401 i * hub->ctx_distance, 0); 402 403 /* Setup TLB control */ 404 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 405 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 406 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 407 ENABLE_ADVANCED_DRIVER_MODEL, 0); 408 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 409 410 /* Setup L2 cache */ 411 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 412 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 413 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 414 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 415 } 416 417 /** 418 * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling 419 * 420 * @adev: amdgpu_device pointer 421 * @value: true redirects VM faults to the default page 422 */ 423 static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev, 424 bool value) 425 { 426 u32 tmp; 427 428 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 429 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 430 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 431 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 432 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 433 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 434 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 436 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 438 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 439 value); 440 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 441 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 442 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 443 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 444 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 445 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 447 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 449 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 450 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 451 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 452 if (!value) { 453 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 454 CRASH_ON_NO_RETRY_FAULT, 1); 455 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 456 CRASH_ON_RETRY_FAULT, 1); 457 } 458 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 459 } 460 461 static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = { 462 .print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status, 463 .get_invalidate_req = mmhub_v3_0_1_get_invalidate_req, 464 }; 465 466 static void mmhub_v3_0_1_init(struct amdgpu_device *adev) 467 { 468 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 469 470 hub->ctx0_ptb_addr_lo32 = 471 SOC15_REG_OFFSET(MMHUB, 0, 472 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 473 hub->ctx0_ptb_addr_hi32 = 474 SOC15_REG_OFFSET(MMHUB, 0, 475 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 476 hub->vm_inv_eng0_sem = 477 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 478 hub->vm_inv_eng0_req = 479 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 480 hub->vm_inv_eng0_ack = 481 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 482 hub->vm_context0_cntl = 483 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 484 hub->vm_l2_pro_fault_status = 485 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 486 hub->vm_l2_pro_fault_cntl = 487 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 488 489 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 490 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 491 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 492 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 493 regMMVM_INVALIDATE_ENG0_REQ; 494 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 495 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 496 497 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 498 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 499 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 500 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 501 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 502 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 503 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 504 505 hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs; 506 } 507 508 static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev) 509 { 510 u64 base; 511 512 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 513 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 514 base <<= 24; 515 516 return base; 517 } 518 519 static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev) 520 { 521 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; 522 } 523 524 static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 525 bool enable) 526 { 527 uint32_t def, data; 528 529 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 530 531 if (enable) 532 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 533 else 534 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 535 536 if (def != data) 537 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 538 } 539 540 static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 541 bool enable) 542 { 543 uint32_t def, data; 544 545 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 546 547 if (enable) 548 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 549 else 550 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 551 552 if (def != data) 553 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 554 } 555 556 static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev, 557 enum amd_clockgating_state state) 558 { 559 if (amdgpu_sriov_vf(adev)) 560 return 0; 561 562 mmhub_v3_0_1_update_medium_grain_clock_gating(adev, 563 state == AMD_CG_STATE_GATE); 564 mmhub_v3_0_1_update_medium_grain_light_sleep(adev, 565 state == AMD_CG_STATE_GATE); 566 return 0; 567 } 568 569 static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags) 570 { 571 int data; 572 573 if (amdgpu_sriov_vf(adev)) 574 *flags = 0; 575 576 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 577 578 /* AMD_CG_SUPPORT_MC_MGCG */ 579 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 580 *flags |= AMD_CG_SUPPORT_MC_MGCG; 581 582 /* AMD_CG_SUPPORT_MC_LS */ 583 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 584 *flags |= AMD_CG_SUPPORT_MC_LS; 585 } 586 587 const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = { 588 .init = mmhub_v3_0_1_init, 589 .get_fb_location = mmhub_v3_0_1_get_fb_location, 590 .get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset, 591 .gart_enable = mmhub_v3_0_1_gart_enable, 592 .set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default, 593 .gart_disable = mmhub_v3_0_1_gart_disable, 594 .set_clockgating = mmhub_v3_0_1_set_clockgating, 595 .get_clockgating = mmhub_v3_0_1_get_clockgating, 596 .setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs, 597 }; 598