1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev) 35 { 36 uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo); 37 38 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 39 lower_32_bits(value)); 40 41 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 42 upper_32_bits(value)); 43 } 44 45 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 46 { 47 mmhub_v2_0_init_gart_pt_regs(adev); 48 49 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 50 (u32)(adev->gmc.gart_start >> 12)); 51 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 52 (u32)(adev->gmc.gart_start >> 44)); 53 54 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 55 (u32)(adev->gmc.gart_end >> 12)); 56 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 57 (u32)(adev->gmc.gart_end >> 44)); 58 } 59 60 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 61 { 62 uint64_t value; 63 uint32_t tmp; 64 65 /* Disable AGP. */ 66 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 67 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 68 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 69 70 /* Program the system aperture low logical page number. */ 71 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 72 adev->gmc.vram_start >> 18); 73 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 74 adev->gmc.vram_end >> 18); 75 76 /* Set default page address. */ 77 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 78 adev->vm_manager.vram_base_offset; 79 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 80 (u32)(value >> 12)); 81 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 82 (u32)(value >> 44)); 83 84 /* Program "protection fault". */ 85 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 86 (u32)(adev->dummy_page_addr >> 12)); 87 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 88 (u32)((u64)adev->dummy_page_addr >> 44)); 89 90 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 91 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 92 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 93 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 94 } 95 96 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 97 { 98 uint32_t tmp; 99 100 /* Setup TLB control */ 101 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 102 103 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 104 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 105 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 106 ENABLE_ADVANCED_DRIVER_MODEL, 1); 107 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 108 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 109 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 110 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 111 MTYPE, MTYPE_UC); /* UC, uncached */ 112 113 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 114 } 115 116 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 117 { 118 uint32_t tmp; 119 120 /* Setup L2 cache */ 121 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 122 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 123 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 124 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 125 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 126 /* XXX for emulation, Refer to closed source code.*/ 127 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 128 0); 129 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 130 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 131 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 132 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 133 134 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 135 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 136 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 137 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 138 139 tmp = mmMMVM_L2_CNTL3_DEFAULT; 140 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 141 142 tmp = mmMMVM_L2_CNTL4_DEFAULT; 143 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 144 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 145 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 146 } 147 148 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 149 { 150 uint32_t tmp; 151 152 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 153 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 154 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 155 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 156 } 157 158 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 159 { 160 WREG32_SOC15(MMHUB, 0, 161 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 162 0xFFFFFFFF); 163 WREG32_SOC15(MMHUB, 0, 164 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 165 0x0000000F); 166 167 WREG32_SOC15(MMHUB, 0, 168 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 169 WREG32_SOC15(MMHUB, 0, 170 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 171 172 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 173 0); 174 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 175 0); 176 } 177 178 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 179 { 180 int i; 181 uint32_t tmp; 182 183 for (i = 0; i <= 14; i++) { 184 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 185 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 186 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 187 adev->vm_manager.num_level); 188 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 189 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 190 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 191 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 192 1); 193 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 194 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 195 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 196 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 197 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 198 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 199 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 200 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 201 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 202 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 203 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 204 PAGE_TABLE_BLOCK_SIZE, 205 adev->vm_manager.block_size - 9); 206 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 207 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 208 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 209 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); 210 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 211 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 212 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 213 lower_32_bits(adev->vm_manager.max_pfn - 1)); 214 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 215 upper_32_bits(adev->vm_manager.max_pfn - 1)); 216 } 217 } 218 219 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 220 { 221 unsigned i; 222 223 for (i = 0; i < 18; ++i) { 224 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 225 2 * i, 0xffffffff); 226 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 227 2 * i, 0x1f); 228 } 229 } 230 231 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 232 { 233 if (amdgpu_sriov_vf(adev)) { 234 /* 235 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 236 * VF copy registers so vbios post doesn't program them, for 237 * SRIOV driver need to program them 238 */ 239 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE, 240 adev->gmc.vram_start >> 24); 241 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP, 242 adev->gmc.vram_end >> 24); 243 } 244 245 /* GART Enable. */ 246 mmhub_v2_0_init_gart_aperture_regs(adev); 247 mmhub_v2_0_init_system_aperture_regs(adev); 248 mmhub_v2_0_init_tlb_regs(adev); 249 mmhub_v2_0_init_cache_regs(adev); 250 251 mmhub_v2_0_enable_system_domain(adev); 252 mmhub_v2_0_disable_identity_aperture(adev); 253 mmhub_v2_0_setup_vmid_config(adev); 254 mmhub_v2_0_program_invalidation(adev); 255 256 return 0; 257 } 258 259 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 260 { 261 u32 tmp; 262 u32 i; 263 264 /* Disable all tables */ 265 for (i = 0; i < 16; i++) 266 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0); 267 268 /* Setup TLB control */ 269 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 270 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 271 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 272 ENABLE_ADVANCED_DRIVER_MODEL, 0); 273 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 274 275 /* Setup L2 cache */ 276 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 277 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 278 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 279 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 280 } 281 282 /** 283 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 284 * 285 * @adev: amdgpu_device pointer 286 * @value: true redirects VM faults to the default page 287 */ 288 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 289 { 290 u32 tmp; 291 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 292 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 293 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 294 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 295 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 296 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 297 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 298 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 299 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 300 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 301 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 302 value); 303 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 304 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 305 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 306 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 307 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 308 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 309 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 310 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 311 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 312 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 313 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 314 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315 if (!value) { 316 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 317 CRASH_ON_NO_RETRY_FAULT, 1); 318 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 319 CRASH_ON_RETRY_FAULT, 1); 320 } 321 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 322 } 323 324 void mmhub_v2_0_init(struct amdgpu_device *adev) 325 { 326 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; 327 328 hub->ctx0_ptb_addr_lo32 = 329 SOC15_REG_OFFSET(MMHUB, 0, 330 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 331 hub->ctx0_ptb_addr_hi32 = 332 SOC15_REG_OFFSET(MMHUB, 0, 333 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 334 hub->vm_inv_eng0_req = 335 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 336 hub->vm_inv_eng0_ack = 337 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 338 hub->vm_context0_cntl = 339 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 340 hub->vm_l2_pro_fault_status = 341 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 342 hub->vm_l2_pro_fault_cntl = 343 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 344 345 } 346 347 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 348 bool enable) 349 { 350 uint32_t def, data, def1, data1; 351 352 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 353 354 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 355 356 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 357 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 358 359 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 360 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 361 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 362 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 363 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 364 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 365 366 } else { 367 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 368 369 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 370 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 371 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 372 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 373 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 374 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 375 } 376 377 if (def != data) 378 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 379 380 if (def1 != data1) 381 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 382 } 383 384 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 385 bool enable) 386 { 387 uint32_t def, data; 388 389 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 390 391 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 392 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 393 else 394 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 395 396 if (def != data) 397 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 398 } 399 400 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 401 enum amd_clockgating_state state) 402 { 403 if (amdgpu_sriov_vf(adev)) 404 return 0; 405 406 switch (adev->asic_type) { 407 case CHIP_NAVI10: 408 mmhub_v2_0_update_medium_grain_clock_gating(adev, 409 state == AMD_CG_STATE_GATE ? true : false); 410 mmhub_v2_0_update_medium_grain_light_sleep(adev, 411 state == AMD_CG_STATE_GATE ? true : false); 412 break; 413 default: 414 break; 415 } 416 417 return 0; 418 } 419 420 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 421 { 422 int data, data1; 423 424 if (amdgpu_sriov_vf(adev)) 425 *flags = 0; 426 427 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 428 429 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 430 431 /* AMD_CG_SUPPORT_MC_MGCG */ 432 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 433 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 434 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 435 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 436 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 437 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 438 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 439 *flags |= AMD_CG_SUPPORT_MC_MGCG; 440 441 /* AMD_CG_SUPPORT_MC_LS */ 442 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 443 *flags |= AMD_CG_SUPPORT_MC_LS; 444 } 445