1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 35 uint64_t page_table_base) 36 { 37 /* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */ 38 int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 39 - mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 40 41 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 42 offset * vmid, lower_32_bits(page_table_base)); 43 44 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 45 offset * vmid, upper_32_bits(page_table_base)); 46 } 47 48 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 49 { 50 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 51 52 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 53 54 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 55 (u32)(adev->gmc.gart_start >> 12)); 56 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 57 (u32)(adev->gmc.gart_start >> 44)); 58 59 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 60 (u32)(adev->gmc.gart_end >> 12)); 61 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 62 (u32)(adev->gmc.gart_end >> 44)); 63 } 64 65 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 66 { 67 uint64_t value; 68 uint32_t tmp; 69 70 /* Disable AGP. */ 71 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 72 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); 73 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); 74 75 /* Program the system aperture low logical page number. */ 76 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 77 adev->gmc.vram_start >> 18); 78 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 79 adev->gmc.vram_end >> 18); 80 81 /* Set default page address. */ 82 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 83 adev->vm_manager.vram_base_offset; 84 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 85 (u32)(value >> 12)); 86 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 87 (u32)(value >> 44)); 88 89 /* Program "protection fault". */ 90 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 91 (u32)(adev->dummy_page_addr >> 12)); 92 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 93 (u32)((u64)adev->dummy_page_addr >> 44)); 94 95 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 96 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 97 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 98 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 99 } 100 101 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 102 { 103 uint32_t tmp; 104 105 /* Setup TLB control */ 106 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 107 108 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 109 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 110 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 111 ENABLE_ADVANCED_DRIVER_MODEL, 1); 112 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 113 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 114 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 115 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 116 MTYPE, MTYPE_UC); /* UC, uncached */ 117 118 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 119 } 120 121 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 122 { 123 uint32_t tmp; 124 125 /* Setup L2 cache */ 126 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 127 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 128 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 129 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 130 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 131 /* XXX for emulation, Refer to closed source code.*/ 132 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 133 0); 134 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 135 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 136 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 137 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 138 139 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 140 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 141 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 142 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 143 144 tmp = mmMMVM_L2_CNTL3_DEFAULT; 145 if (adev->gmc.translate_further) { 146 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 147 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 148 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 149 } else { 150 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 151 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 152 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 153 } 154 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 155 156 tmp = mmMMVM_L2_CNTL4_DEFAULT; 157 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 158 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 159 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 160 } 161 162 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 163 { 164 uint32_t tmp; 165 166 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 167 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 168 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 169 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 170 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 171 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 172 } 173 174 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 175 { 176 WREG32_SOC15(MMHUB, 0, 177 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 178 0xFFFFFFFF); 179 WREG32_SOC15(MMHUB, 0, 180 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 181 0x0000000F); 182 183 WREG32_SOC15(MMHUB, 0, 184 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 185 WREG32_SOC15(MMHUB, 0, 186 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 187 188 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 189 0); 190 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 191 0); 192 } 193 194 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 195 { 196 int i; 197 uint32_t tmp; 198 199 for (i = 0; i <= 14; i++) { 200 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 201 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 202 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 203 adev->vm_manager.num_level); 204 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 205 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 206 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 207 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 208 1); 209 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 210 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 211 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 212 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 213 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 214 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 215 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 216 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 217 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 218 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 219 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 220 PAGE_TABLE_BLOCK_SIZE, 221 adev->vm_manager.block_size - 9); 222 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 223 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 224 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 225 !amdgpu_noretry); 226 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); 227 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 228 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 229 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 230 lower_32_bits(adev->vm_manager.max_pfn - 1)); 231 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 232 upper_32_bits(adev->vm_manager.max_pfn - 1)); 233 } 234 } 235 236 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 237 { 238 unsigned i; 239 240 for (i = 0; i < 18; ++i) { 241 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 242 2 * i, 0xffffffff); 243 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 244 2 * i, 0x1f); 245 } 246 } 247 248 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 249 { 250 if (amdgpu_sriov_vf(adev)) { 251 /* 252 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 253 * VF copy registers so vbios post doesn't program them, for 254 * SRIOV driver need to program them 255 */ 256 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE, 257 adev->gmc.vram_start >> 24); 258 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP, 259 adev->gmc.vram_end >> 24); 260 } 261 262 /* GART Enable. */ 263 mmhub_v2_0_init_gart_aperture_regs(adev); 264 mmhub_v2_0_init_system_aperture_regs(adev); 265 mmhub_v2_0_init_tlb_regs(adev); 266 mmhub_v2_0_init_cache_regs(adev); 267 268 mmhub_v2_0_enable_system_domain(adev); 269 mmhub_v2_0_disable_identity_aperture(adev); 270 mmhub_v2_0_setup_vmid_config(adev); 271 mmhub_v2_0_program_invalidation(adev); 272 273 return 0; 274 } 275 276 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 277 { 278 u32 tmp; 279 u32 i; 280 281 /* Disable all tables */ 282 for (i = 0; i < 16; i++) 283 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0); 284 285 /* Setup TLB control */ 286 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 287 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 288 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 289 ENABLE_ADVANCED_DRIVER_MODEL, 0); 290 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 291 292 /* Setup L2 cache */ 293 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 294 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 295 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 296 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 297 } 298 299 /** 300 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 301 * 302 * @adev: amdgpu_device pointer 303 * @value: true redirects VM faults to the default page 304 */ 305 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 306 { 307 u32 tmp; 308 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 309 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 310 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 311 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 312 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 313 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 314 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 316 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 317 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 318 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 319 value); 320 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 321 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 322 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 323 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 324 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 325 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 326 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 327 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 328 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 329 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 330 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 331 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 332 if (!value) { 333 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 334 CRASH_ON_NO_RETRY_FAULT, 1); 335 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 336 CRASH_ON_RETRY_FAULT, 1); 337 } 338 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 339 } 340 341 void mmhub_v2_0_init(struct amdgpu_device *adev) 342 { 343 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 344 345 hub->ctx0_ptb_addr_lo32 = 346 SOC15_REG_OFFSET(MMHUB, 0, 347 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 348 hub->ctx0_ptb_addr_hi32 = 349 SOC15_REG_OFFSET(MMHUB, 0, 350 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 351 hub->vm_inv_eng0_sem = 352 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM); 353 hub->vm_inv_eng0_req = 354 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 355 hub->vm_inv_eng0_ack = 356 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 357 hub->vm_context0_cntl = 358 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 359 hub->vm_l2_pro_fault_status = 360 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 361 hub->vm_l2_pro_fault_cntl = 362 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 363 364 } 365 366 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 367 bool enable) 368 { 369 uint32_t def, data, def1, data1; 370 371 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 372 373 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 374 375 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 376 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 377 378 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 379 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 380 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 381 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 382 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 383 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 384 385 } else { 386 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 387 388 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 389 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 390 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 391 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 392 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 393 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 394 } 395 396 if (def != data) 397 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 398 399 if (def1 != data1) 400 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 401 } 402 403 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 404 bool enable) 405 { 406 uint32_t def, data; 407 408 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 409 410 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 411 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 412 else 413 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 414 415 if (def != data) 416 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 417 } 418 419 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 420 enum amd_clockgating_state state) 421 { 422 if (amdgpu_sriov_vf(adev)) 423 return 0; 424 425 switch (adev->asic_type) { 426 case CHIP_NAVI10: 427 case CHIP_NAVI14: 428 case CHIP_NAVI12: 429 mmhub_v2_0_update_medium_grain_clock_gating(adev, 430 state == AMD_CG_STATE_GATE ? true : false); 431 mmhub_v2_0_update_medium_grain_light_sleep(adev, 432 state == AMD_CG_STATE_GATE ? true : false); 433 break; 434 default: 435 break; 436 } 437 438 return 0; 439 } 440 441 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 442 { 443 int data, data1; 444 445 if (amdgpu_sriov_vf(adev)) 446 *flags = 0; 447 448 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 449 450 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 451 452 /* AMD_CG_SUPPORT_MC_MGCG */ 453 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 454 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 455 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 456 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 457 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 458 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 459 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 460 *flags |= AMD_CG_SUPPORT_MC_MGCG; 461 462 /* AMD_CG_SUPPORT_MC_LS */ 463 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 464 *flags |= AMD_CG_SUPPORT_MC_LS; 465 } 466