1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v2_0.h" 26 27 #include "mmhub/mmhub_2_0_0_offset.h" 28 #include "mmhub/mmhub_2_0_0_sh_mask.h" 29 #include "mmhub/mmhub_2_0_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "gc/gc_10_1_0_offset.h" 33 #include "soc15_common.h" 34 35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d 36 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0 37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070 38 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0 39 40 static const char *mmhub_client_ids_navi1x[][2] = { 41 [3][0] = "DCEDMC", 42 [4][0] = "DCEVGA", 43 [5][0] = "MP0", 44 [6][0] = "MP1", 45 [13][0] = "VMC", 46 [14][0] = "HDP", 47 [15][0] = "OSS", 48 [16][0] = "VCNU", 49 [17][0] = "JPEG", 50 [18][0] = "VCN", 51 [3][1] = "DCEDMC", 52 [4][1] = "DCEXFC", 53 [5][1] = "DCEVGA", 54 [6][1] = "DCEDWB", 55 [7][1] = "MP0", 56 [8][1] = "MP1", 57 [9][1] = "DBGU1", 58 [10][1] = "DBGU0", 59 [11][1] = "XDP", 60 [14][1] = "HDP", 61 [15][1] = "OSS", 62 [16][1] = "VCNU", 63 [17][1] = "JPEG", 64 [18][1] = "VCN", 65 }; 66 67 static const char *mmhub_client_ids_sienna_cichlid[][2] = { 68 [3][0] = "DCEDMC", 69 [4][0] = "DCEVGA", 70 [5][0] = "MP0", 71 [6][0] = "MP1", 72 [8][0] = "VMC", 73 [9][0] = "VCNU0", 74 [10][0] = "JPEG", 75 [12][0] = "VCNU1", 76 [13][0] = "VCN1", 77 [14][0] = "HDP", 78 [15][0] = "OSS", 79 [32+11][0] = "VCN0", 80 [0][1] = "DBGU0", 81 [1][1] = "DBGU1", 82 [2][1] = "DCEDWB", 83 [3][1] = "DCEDMC", 84 [4][1] = "DCEVGA", 85 [5][1] = "MP0", 86 [6][1] = "MP1", 87 [7][1] = "XDP", 88 [9][1] = "VCNU0", 89 [10][1] = "JPEG", 90 [11][1] = "VCN0", 91 [12][1] = "VCNU1", 92 [13][1] = "VCN1", 93 [14][1] = "HDP", 94 [15][1] = "OSS", 95 }; 96 97 static const char *mmhub_client_ids_beige_goby[][2] = { 98 [3][0] = "DCEDMC", 99 [4][0] = "DCEVGA", 100 [5][0] = "MP0", 101 [6][0] = "MP1", 102 [8][0] = "VMC", 103 [9][0] = "VCNU0", 104 [11][0] = "VCN0", 105 [14][0] = "HDP", 106 [15][0] = "OSS", 107 [0][1] = "DBGU0", 108 [1][1] = "DBGU1", 109 [2][1] = "DCEDWB", 110 [3][1] = "DCEDMC", 111 [4][1] = "DCEVGA", 112 [5][1] = "MP0", 113 [6][1] = "MP1", 114 [7][1] = "XDP", 115 [9][1] = "VCNU0", 116 [11][1] = "VCN0", 117 [14][1] = "HDP", 118 [15][1] = "OSS", 119 }; 120 121 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid, 122 uint32_t flush_type) 123 { 124 u32 req = 0; 125 126 /* invalidate using legacy mode on vmid*/ 127 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 128 PER_VMID_INVALIDATE_REQ, 1 << vmid); 129 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 130 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 131 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 132 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 133 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 134 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 135 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 136 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 137 138 return req; 139 } 140 141 static void 142 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 143 uint32_t status) 144 { 145 uint32_t cid, rw; 146 const char *mmhub_cid = NULL; 147 148 cid = REG_GET_FIELD(status, 149 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 150 rw = REG_GET_FIELD(status, 151 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 152 153 dev_err(adev->dev, 154 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 155 status); 156 switch (adev->asic_type) { 157 case CHIP_NAVI10: 158 case CHIP_NAVI12: 159 case CHIP_NAVI14: 160 mmhub_cid = mmhub_client_ids_navi1x[cid][rw]; 161 break; 162 case CHIP_SIENNA_CICHLID: 163 case CHIP_NAVY_FLOUNDER: 164 case CHIP_DIMGREY_CAVEFISH: 165 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw]; 166 break; 167 case CHIP_BEIGE_GOBY: 168 mmhub_cid = mmhub_client_ids_beige_goby[cid][rw]; 169 break; 170 default: 171 mmhub_cid = NULL; 172 break; 173 } 174 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 175 mmhub_cid ? mmhub_cid : "unknown", cid); 176 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 177 REG_GET_FIELD(status, 178 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 179 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 180 REG_GET_FIELD(status, 181 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 182 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 183 REG_GET_FIELD(status, 184 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 185 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 186 REG_GET_FIELD(status, 187 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 188 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 189 } 190 191 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 192 uint64_t page_table_base) 193 { 194 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 195 196 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 197 hub->ctx_addr_distance * vmid, 198 lower_32_bits(page_table_base)); 199 200 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 201 hub->ctx_addr_distance * vmid, 202 upper_32_bits(page_table_base)); 203 } 204 205 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 206 { 207 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 208 209 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 210 211 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 212 (u32)(adev->gmc.gart_start >> 12)); 213 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 214 (u32)(adev->gmc.gart_start >> 44)); 215 216 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 217 (u32)(adev->gmc.gart_end >> 12)); 218 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 219 (u32)(adev->gmc.gart_end >> 44)); 220 } 221 222 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 223 { 224 uint64_t value; 225 uint32_t tmp; 226 227 if (!amdgpu_sriov_vf(adev)) { 228 /* Program the AGP BAR */ 229 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 230 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 231 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 232 233 /* Program the system aperture low logical page number. */ 234 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 235 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 236 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 237 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 238 } 239 240 /* Set default page address. */ 241 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 242 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 243 (u32)(value >> 12)); 244 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 245 (u32)(value >> 44)); 246 247 /* Program "protection fault". */ 248 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 249 (u32)(adev->dummy_page_addr >> 12)); 250 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 251 (u32)((u64)adev->dummy_page_addr >> 44)); 252 253 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); 254 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 255 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 256 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 257 } 258 259 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 260 { 261 uint32_t tmp; 262 263 /* Setup TLB control */ 264 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 265 266 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 267 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 268 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 269 ENABLE_ADVANCED_DRIVER_MODEL, 1); 270 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 271 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 272 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 273 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 274 MTYPE, MTYPE_UC); /* UC, uncached */ 275 276 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 277 } 278 279 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 280 { 281 uint32_t tmp; 282 283 /* These registers are not accessible to VF-SRIOV. 284 * The PF will program them instead. 285 */ 286 if (amdgpu_sriov_vf(adev)) 287 return; 288 289 /* Setup L2 cache */ 290 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 291 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 292 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 293 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 294 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 295 /* XXX for emulation, Refer to closed source code.*/ 296 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 297 0); 298 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 299 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 300 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 301 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 302 303 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); 304 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 305 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 306 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); 307 308 tmp = mmMMVM_L2_CNTL3_DEFAULT; 309 if (adev->gmc.translate_further) { 310 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 311 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 312 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 313 } else { 314 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 315 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 316 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 317 } 318 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); 319 320 tmp = mmMMVM_L2_CNTL4_DEFAULT; 321 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 322 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 323 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); 324 325 tmp = mmMMVM_L2_CNTL5_DEFAULT; 326 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 327 WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); 328 } 329 330 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 331 { 332 uint32_t tmp; 333 334 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 336 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 337 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 338 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 339 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); 340 } 341 342 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 343 { 344 /* These registers are not accessible to VF-SRIOV. 345 * The PF will program them instead. 346 */ 347 if (amdgpu_sriov_vf(adev)) 348 return; 349 350 WREG32_SOC15(MMHUB, 0, 351 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 352 0xFFFFFFFF); 353 WREG32_SOC15(MMHUB, 0, 354 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 355 0x0000000F); 356 357 WREG32_SOC15(MMHUB, 0, 358 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 359 WREG32_SOC15(MMHUB, 0, 360 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 361 362 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 363 0); 364 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 365 0); 366 } 367 368 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 369 { 370 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 371 int i; 372 uint32_t tmp; 373 374 for (i = 0; i <= 14; i++) { 375 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); 376 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 377 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 378 adev->vm_manager.num_level); 379 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 380 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 381 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 382 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 383 1); 384 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 385 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 386 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 387 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 388 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 389 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 390 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 391 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 392 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 393 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 394 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 395 PAGE_TABLE_BLOCK_SIZE, 396 adev->vm_manager.block_size - 9); 397 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 398 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 399 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 400 !adev->gmc.noretry); 401 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, 402 i * hub->ctx_distance, tmp); 403 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 404 i * hub->ctx_addr_distance, 0); 405 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 406 i * hub->ctx_addr_distance, 0); 407 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 408 i * hub->ctx_addr_distance, 409 lower_32_bits(adev->vm_manager.max_pfn - 1)); 410 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 411 i * hub->ctx_addr_distance, 412 upper_32_bits(adev->vm_manager.max_pfn - 1)); 413 } 414 } 415 416 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) 417 { 418 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 419 unsigned i; 420 421 for (i = 0; i < 18; ++i) { 422 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 423 i * hub->eng_addr_distance, 0xffffffff); 424 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 425 i * hub->eng_addr_distance, 0x1f); 426 } 427 } 428 429 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) 430 { 431 /* GART Enable. */ 432 mmhub_v2_0_init_gart_aperture_regs(adev); 433 mmhub_v2_0_init_system_aperture_regs(adev); 434 mmhub_v2_0_init_tlb_regs(adev); 435 mmhub_v2_0_init_cache_regs(adev); 436 437 mmhub_v2_0_enable_system_domain(adev); 438 mmhub_v2_0_disable_identity_aperture(adev); 439 mmhub_v2_0_setup_vmid_config(adev); 440 mmhub_v2_0_program_invalidation(adev); 441 442 return 0; 443 } 444 445 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 446 { 447 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 448 u32 tmp; 449 u32 i; 450 451 /* Disable all tables */ 452 for (i = 0; i < AMDGPU_NUM_VMID; i++) 453 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, 454 i * hub->ctx_distance, 0); 455 456 /* Setup TLB control */ 457 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); 458 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 459 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 460 ENABLE_ADVANCED_DRIVER_MODEL, 0); 461 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 462 463 /* Setup L2 cache */ 464 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 465 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 466 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 467 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); 468 } 469 470 /** 471 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling 472 * 473 * @adev: amdgpu_device pointer 474 * @value: true redirects VM faults to the default page 475 */ 476 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 477 { 478 u32 tmp; 479 480 /* These registers are not accessible to VF-SRIOV. 481 * The PF will program them instead. 482 */ 483 if (amdgpu_sriov_vf(adev)) 484 return; 485 486 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 487 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 488 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 489 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 490 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 491 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 492 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 493 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 494 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 495 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 496 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 497 value); 498 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 499 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 500 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 501 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 502 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 503 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 504 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 505 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 506 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 507 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 508 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 509 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 510 if (!value) { 511 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 512 CRASH_ON_NO_RETRY_FAULT, 1); 513 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 514 CRASH_ON_RETRY_FAULT, 1); 515 } 516 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 517 } 518 519 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = { 520 .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status, 521 .get_invalidate_req = mmhub_v2_0_get_invalidate_req, 522 }; 523 524 static void mmhub_v2_0_init(struct amdgpu_device *adev) 525 { 526 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 527 528 hub->ctx0_ptb_addr_lo32 = 529 SOC15_REG_OFFSET(MMHUB, 0, 530 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 531 hub->ctx0_ptb_addr_hi32 = 532 SOC15_REG_OFFSET(MMHUB, 0, 533 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 534 hub->vm_inv_eng0_sem = 535 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM); 536 hub->vm_inv_eng0_req = 537 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); 538 hub->vm_inv_eng0_ack = 539 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); 540 hub->vm_context0_cntl = 541 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); 542 hub->vm_l2_pro_fault_status = 543 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); 544 hub->vm_l2_pro_fault_cntl = 545 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); 546 547 hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL; 548 hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 549 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 550 hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ - 551 mmMMVM_INVALIDATE_ENG0_REQ; 552 hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 553 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 554 555 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 556 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 557 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 558 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 559 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 560 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 561 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 562 563 hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs; 564 } 565 566 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 567 bool enable) 568 { 569 uint32_t def, data, def1, data1; 570 571 switch (adev->asic_type) { 572 case CHIP_SIENNA_CICHLID: 573 case CHIP_NAVY_FLOUNDER: 574 case CHIP_DIMGREY_CAVEFISH: 575 case CHIP_BEIGE_GOBY: 576 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 577 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 578 break; 579 default: 580 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 581 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 582 break; 583 } 584 585 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 586 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 587 588 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 589 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 590 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 591 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 592 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 593 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 594 595 } else { 596 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 597 598 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 599 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 600 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 601 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 602 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 603 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 604 } 605 606 switch (adev->asic_type) { 607 case CHIP_SIENNA_CICHLID: 608 case CHIP_NAVY_FLOUNDER: 609 case CHIP_DIMGREY_CAVEFISH: 610 case CHIP_BEIGE_GOBY: 611 if (def != data) 612 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 613 if (def1 != data1) 614 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1); 615 break; 616 default: 617 if (def != data) 618 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 619 if (def1 != data1) 620 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 621 break; 622 } 623 } 624 625 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 626 bool enable) 627 { 628 uint32_t def, data; 629 630 switch (adev->asic_type) { 631 case CHIP_SIENNA_CICHLID: 632 case CHIP_NAVY_FLOUNDER: 633 case CHIP_DIMGREY_CAVEFISH: 634 case CHIP_BEIGE_GOBY: 635 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 636 break; 637 default: 638 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 639 break; 640 } 641 642 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 643 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 644 else 645 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 646 647 if (def != data) { 648 switch (adev->asic_type) { 649 case CHIP_SIENNA_CICHLID: 650 case CHIP_NAVY_FLOUNDER: 651 case CHIP_DIMGREY_CAVEFISH: 652 case CHIP_BEIGE_GOBY: 653 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); 654 break; 655 default: 656 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); 657 break; 658 } 659 } 660 } 661 662 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 663 enum amd_clockgating_state state) 664 { 665 if (amdgpu_sriov_vf(adev)) 666 return 0; 667 668 switch (adev->asic_type) { 669 case CHIP_NAVI10: 670 case CHIP_NAVI14: 671 case CHIP_NAVI12: 672 case CHIP_SIENNA_CICHLID: 673 case CHIP_NAVY_FLOUNDER: 674 case CHIP_DIMGREY_CAVEFISH: 675 case CHIP_BEIGE_GOBY: 676 mmhub_v2_0_update_medium_grain_clock_gating(adev, 677 state == AMD_CG_STATE_GATE); 678 mmhub_v2_0_update_medium_grain_light_sleep(adev, 679 state == AMD_CG_STATE_GATE); 680 break; 681 default: 682 break; 683 } 684 685 return 0; 686 } 687 688 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 689 { 690 int data, data1; 691 692 if (amdgpu_sriov_vf(adev)) 693 *flags = 0; 694 695 switch (adev->asic_type) { 696 case CHIP_SIENNA_CICHLID: 697 case CHIP_NAVY_FLOUNDER: 698 case CHIP_DIMGREY_CAVEFISH: 699 case CHIP_BEIGE_GOBY: 700 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); 701 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); 702 break; 703 default: 704 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); 705 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 706 break; 707 } 708 709 /* AMD_CG_SUPPORT_MC_MGCG */ 710 if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && 711 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 712 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 713 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 714 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 715 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 716 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 717 *flags |= AMD_CG_SUPPORT_MC_MGCG; 718 719 /* AMD_CG_SUPPORT_MC_LS */ 720 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 721 *flags |= AMD_CG_SUPPORT_MC_LS; 722 } 723 724 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = { 725 .init = mmhub_v2_0_init, 726 .gart_enable = mmhub_v2_0_gart_enable, 727 .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default, 728 .gart_disable = mmhub_v2_0_gart_disable, 729 .set_clockgating = mmhub_v2_0_set_clockgating, 730 .get_clockgating = mmhub_v2_0_get_clockgating, 731 .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs, 732 }; 733