1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "mmhub_v1_0.h" 25 26 #include "mmhub/mmhub_1_0_offset.h" 27 #include "mmhub/mmhub_1_0_sh_mask.h" 28 #include "mmhub/mmhub_1_0_default.h" 29 #include "vega10_enum.h" 30 31 #include "soc15_common.h" 32 33 #define mmDAGB0_CNTL_MISC2_RV 0x008f 34 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 35 36 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 37 { 38 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); 39 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); 40 41 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 42 base <<= 24; 43 44 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 45 top <<= 24; 46 47 adev->gmc.fb_start = base; 48 adev->gmc.fb_end = top; 49 50 return base; 51 } 52 53 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 54 uint64_t page_table_base) 55 { 56 /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */ 57 int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 58 - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 59 60 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 61 offset * vmid, lower_32_bits(page_table_base)); 62 63 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 64 offset * vmid, upper_32_bits(page_table_base)); 65 } 66 67 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 68 { 69 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 70 71 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 72 73 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 74 (u32)(adev->gmc.gart_start >> 12)); 75 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 76 (u32)(adev->gmc.gart_start >> 44)); 77 78 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 79 (u32)(adev->gmc.gart_end >> 12)); 80 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 81 (u32)(adev->gmc.gart_end >> 44)); 82 } 83 84 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 85 { 86 uint64_t value; 87 uint32_t tmp; 88 89 /* Program the AGP BAR */ 90 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); 91 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 93 94 /* Program the system aperture low logical page number. */ 95 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 96 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 97 98 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) 99 /* 100 * Raven2 has a HW issue that it is unable to use the vram which 101 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 102 * workaround that increase system aperture high address (add 1) 103 * to get rid of the VM fault and hardware hang. 104 */ 105 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 106 max((adev->gmc.fb_end >> 18) + 0x1, 107 adev->gmc.agp_end >> 18)); 108 else 109 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 110 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 111 112 if (amdgpu_sriov_vf(adev)) 113 return; 114 115 /* Set default page address. */ 116 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 117 adev->vm_manager.vram_base_offset; 118 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 119 (u32)(value >> 12)); 120 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 121 (u32)(value >> 44)); 122 123 /* Program "protection fault". */ 124 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 125 (u32)(adev->dummy_page_addr >> 12)); 126 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 127 (u32)((u64)adev->dummy_page_addr >> 44)); 128 129 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); 130 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 131 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 132 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); 133 } 134 135 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 136 { 137 uint32_t tmp; 138 139 /* Setup TLB control */ 140 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 141 142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 145 ENABLE_ADVANCED_DRIVER_MODEL, 1); 146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 147 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 149 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 150 MTYPE, MTYPE_UC);/* XXX for emulation. */ 151 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 152 153 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 154 } 155 156 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 157 { 158 uint32_t tmp; 159 160 if (amdgpu_sriov_vf(adev)) 161 return; 162 163 /* Setup L2 cache */ 164 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 165 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 167 /* XXX for emulation, Refer to closed source code.*/ 168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 169 0); 170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 173 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 174 175 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); 176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 178 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 179 180 if (adev->gmc.translate_further) { 181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 183 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 184 } else { 185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 186 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 187 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 188 } 189 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); 190 191 tmp = mmVM_L2_CNTL4_DEFAULT; 192 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 193 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 194 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); 195 } 196 197 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 198 { 199 uint32_t tmp; 200 201 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); 202 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 203 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 204 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); 205 } 206 207 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 208 { 209 if (amdgpu_sriov_vf(adev)) 210 return; 211 212 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 213 0XFFFFFFFF); 214 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 215 0x0000000F); 216 217 WREG32_SOC15(MMHUB, 0, 218 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 219 WREG32_SOC15(MMHUB, 0, 220 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 221 222 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 223 0); 224 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 225 0); 226 } 227 228 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 229 { 230 unsigned num_level, block_size; 231 uint32_t tmp; 232 int i; 233 234 num_level = adev->vm_manager.num_level; 235 block_size = adev->vm_manager.block_size; 236 if (adev->gmc.translate_further) 237 num_level -= 1; 238 else 239 block_size -= 9; 240 241 for (i = 0; i <= 14; i++) { 242 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); 243 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 244 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 245 num_level); 246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 247 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 248 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 249 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 250 1); 251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 252 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 253 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 254 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 255 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 256 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 257 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 258 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 259 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 260 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 261 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 262 PAGE_TABLE_BLOCK_SIZE, 263 block_size); 264 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 265 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 266 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 267 !amdgpu_noretry); 268 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); 269 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 270 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 271 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 272 lower_32_bits(adev->vm_manager.max_pfn - 1)); 273 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 274 upper_32_bits(adev->vm_manager.max_pfn - 1)); 275 } 276 } 277 278 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) 279 { 280 unsigned i; 281 282 for (i = 0; i < 18; ++i) { 283 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 284 2 * i, 0xffffffff); 285 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 286 2 * i, 0x1f); 287 } 288 } 289 290 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 291 bool enable) 292 { 293 if (amdgpu_sriov_vf(adev)) 294 return; 295 296 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { 297 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu) 298 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true); 299 300 } 301 } 302 303 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 304 { 305 if (amdgpu_sriov_vf(adev)) { 306 /* 307 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 308 * VF copy registers so vbios post doesn't program them, for 309 * SRIOV driver need to program them 310 */ 311 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 312 adev->gmc.vram_start >> 24); 313 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 314 adev->gmc.vram_end >> 24); 315 } 316 317 /* GART Enable. */ 318 mmhub_v1_0_init_gart_aperture_regs(adev); 319 mmhub_v1_0_init_system_aperture_regs(adev); 320 mmhub_v1_0_init_tlb_regs(adev); 321 mmhub_v1_0_init_cache_regs(adev); 322 323 mmhub_v1_0_enable_system_domain(adev); 324 mmhub_v1_0_disable_identity_aperture(adev); 325 mmhub_v1_0_setup_vmid_config(adev); 326 mmhub_v1_0_program_invalidation(adev); 327 328 return 0; 329 } 330 331 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 332 { 333 u32 tmp; 334 u32 i; 335 336 /* Disable all tables */ 337 for (i = 0; i < 16; i++) 338 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); 339 340 /* Setup TLB control */ 341 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 342 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 343 tmp = REG_SET_FIELD(tmp, 344 MC_VM_MX_L1_TLB_CNTL, 345 ENABLE_ADVANCED_DRIVER_MODEL, 346 0); 347 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 348 349 if (!amdgpu_sriov_vf(adev)) { 350 /* Setup L2 cache */ 351 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 352 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 353 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 354 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); 355 } 356 } 357 358 /** 359 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 360 * 361 * @adev: amdgpu_device pointer 362 * @value: true redirects VM faults to the default page 363 */ 364 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 365 { 366 u32 tmp; 367 368 if (amdgpu_sriov_vf(adev)) 369 return; 370 371 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 372 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 373 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 374 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 375 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 376 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 377 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 378 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 379 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 380 tmp = REG_SET_FIELD(tmp, 381 VM_L2_PROTECTION_FAULT_CNTL, 382 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 383 value); 384 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 385 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 386 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 387 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 388 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 389 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 391 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 393 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 395 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 if (!value) { 397 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 398 CRASH_ON_NO_RETRY_FAULT, 1); 399 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 400 CRASH_ON_RETRY_FAULT, 1); 401 } 402 403 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 404 } 405 406 void mmhub_v1_0_init(struct amdgpu_device *adev) 407 { 408 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; 409 410 hub->ctx0_ptb_addr_lo32 = 411 SOC15_REG_OFFSET(MMHUB, 0, 412 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 413 hub->ctx0_ptb_addr_hi32 = 414 SOC15_REG_OFFSET(MMHUB, 0, 415 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 416 hub->vm_inv_eng0_req = 417 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); 418 hub->vm_inv_eng0_ack = 419 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); 420 hub->vm_context0_cntl = 421 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); 422 hub->vm_l2_pro_fault_status = 423 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 424 hub->vm_l2_pro_fault_cntl = 425 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 426 427 } 428 429 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 430 bool enable) 431 { 432 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 433 434 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 435 436 if (adev->asic_type != CHIP_RAVEN) { 437 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 438 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 439 } else 440 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); 441 442 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 443 data |= ATC_L2_MISC_CG__ENABLE_MASK; 444 445 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 446 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 447 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 448 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 449 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 450 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 451 452 if (adev->asic_type != CHIP_RAVEN) 453 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 454 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 455 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 456 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 457 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 458 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 459 } else { 460 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 461 462 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 463 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 464 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 465 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 466 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 467 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 468 469 if (adev->asic_type != CHIP_RAVEN) 470 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 471 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 472 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 473 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 474 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 475 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 476 } 477 478 if (def != data) 479 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 480 481 if (def1 != data1) { 482 if (adev->asic_type != CHIP_RAVEN) 483 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 484 else 485 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 486 } 487 488 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 489 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 490 } 491 492 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 493 bool enable) 494 { 495 uint32_t def, data; 496 497 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 498 499 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 500 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 501 else 502 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 503 504 if (def != data) 505 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 506 } 507 508 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 509 enum amd_clockgating_state state) 510 { 511 if (amdgpu_sriov_vf(adev)) 512 return 0; 513 514 switch (adev->asic_type) { 515 case CHIP_VEGA10: 516 case CHIP_VEGA12: 517 case CHIP_VEGA20: 518 case CHIP_RAVEN: 519 mmhub_v1_0_update_medium_grain_clock_gating(adev, 520 state == AMD_CG_STATE_GATE ? true : false); 521 mmhub_v1_0_update_medium_grain_light_sleep(adev, 522 state == AMD_CG_STATE_GATE ? true : false); 523 break; 524 default: 525 break; 526 } 527 528 return 0; 529 } 530 531 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 532 { 533 int data, data1; 534 535 if (amdgpu_sriov_vf(adev)) 536 *flags = 0; 537 538 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 539 540 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 541 542 /* AMD_CG_SUPPORT_MC_MGCG */ 543 if ((data & ATC_L2_MISC_CG__ENABLE_MASK) && 544 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 545 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 546 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 547 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 548 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 549 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 550 *flags |= AMD_CG_SUPPORT_MC_MGCG; 551 552 /* AMD_CG_SUPPORT_MC_LS */ 553 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 554 *flags |= AMD_CG_SUPPORT_MC_LS; 555 } 556 557 static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, 558 void *ras_error_status) 559 { 560 } 561 562 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = { 563 .query_ras_error_count = mmhub_v1_0_query_ras_error_count, 564 }; 565