1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_ras.h" 25 #include "mmhub_v1_0.h" 26 27 #include "mmhub/mmhub_1_0_offset.h" 28 #include "mmhub/mmhub_1_0_sh_mask.h" 29 #include "mmhub/mmhub_1_0_default.h" 30 #include "vega10_enum.h" 31 #include "soc15.h" 32 #include "soc15_common.h" 33 34 #define mmDAGB0_CNTL_MISC2_RV 0x008f 35 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 36 37 static u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 38 { 39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); 40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); 41 42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 43 base <<= 24; 44 45 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 46 top <<= 24; 47 48 adev->gmc.fb_start = base; 49 adev->gmc.fb_end = top; 50 51 return base; 52 } 53 54 static void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 55 uint64_t page_table_base) 56 { 57 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 58 59 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 60 hub->ctx_addr_distance * vmid, 61 lower_32_bits(page_table_base)); 62 63 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 64 hub->ctx_addr_distance * vmid, 65 upper_32_bits(page_table_base)); 66 } 67 68 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 69 { 70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 71 72 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 73 74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 75 (u32)(adev->gmc.gart_start >> 12)); 76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 77 (u32)(adev->gmc.gart_start >> 44)); 78 79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 80 (u32)(adev->gmc.gart_end >> 12)); 81 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 82 (u32)(adev->gmc.gart_end >> 44)); 83 } 84 85 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 86 { 87 uint64_t value; 88 uint32_t tmp; 89 90 /* Program the AGP BAR */ 91 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); 92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 94 95 /* Program the system aperture low logical page number. */ 96 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 98 99 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 100 AMD_APU_IS_RENOIR | 101 AMD_APU_IS_GREEN_SARDINE)) 102 /* 103 * Raven2 has a HW issue that it is unable to use the vram which 104 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 105 * workaround that increase system aperture high address (add 1) 106 * to get rid of the VM fault and hardware hang. 107 */ 108 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 109 max((adev->gmc.fb_end >> 18) + 0x1, 110 adev->gmc.agp_end >> 18)); 111 else 112 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 113 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 114 115 if (amdgpu_sriov_vf(adev)) 116 return; 117 118 /* Set default page address. */ 119 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 120 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 121 (u32)(value >> 12)); 122 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 123 (u32)(value >> 44)); 124 125 /* Program "protection fault". */ 126 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 127 (u32)(adev->dummy_page_addr >> 12)); 128 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 129 (u32)((u64)adev->dummy_page_addr >> 44)); 130 131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); 132 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 133 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 134 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); 135 } 136 137 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 138 { 139 uint32_t tmp; 140 141 /* Setup TLB control */ 142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 143 144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 147 ENABLE_ADVANCED_DRIVER_MODEL, 1); 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 149 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 151 MTYPE, MTYPE_UC);/* XXX for emulation. */ 152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 153 154 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 155 } 156 157 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 158 { 159 uint32_t tmp; 160 161 if (amdgpu_sriov_vf(adev)) 162 return; 163 164 /* Setup L2 cache */ 165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 168 /* XXX for emulation, Refer to closed source code.*/ 169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 170 0); 171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 173 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 174 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 175 176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); 177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 179 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 180 181 tmp = mmVM_L2_CNTL3_DEFAULT; 182 if (adev->gmc.translate_further) { 183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 185 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 186 } else { 187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 189 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 190 } 191 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); 192 193 tmp = mmVM_L2_CNTL4_DEFAULT; 194 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 195 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); 197 } 198 199 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 200 { 201 uint32_t tmp; 202 203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); 204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 205 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 206 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 207 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 208 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); 209 } 210 211 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 212 { 213 if (amdgpu_sriov_vf(adev)) 214 return; 215 216 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 217 0XFFFFFFFF); 218 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 219 0x0000000F); 220 221 WREG32_SOC15(MMHUB, 0, 222 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 223 WREG32_SOC15(MMHUB, 0, 224 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 225 226 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 227 0); 228 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 229 0); 230 } 231 232 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 233 { 234 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 235 unsigned num_level, block_size; 236 uint32_t tmp; 237 int i; 238 239 num_level = adev->vm_manager.num_level; 240 block_size = adev->vm_manager.block_size; 241 if (adev->gmc.translate_further) 242 num_level -= 1; 243 else 244 block_size -= 9; 245 246 for (i = 0; i <= 14; i++) { 247 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance); 248 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 249 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 250 num_level); 251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 252 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 253 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 254 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 255 1); 256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 257 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 258 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 259 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 260 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 261 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 262 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 263 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 264 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 265 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 266 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 267 PAGE_TABLE_BLOCK_SIZE, 268 block_size); 269 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 270 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 271 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 272 !adev->gmc.noretry); 273 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, 274 i * hub->ctx_distance, tmp); 275 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 276 i * hub->ctx_addr_distance, 0); 277 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 278 i * hub->ctx_addr_distance, 0); 279 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 280 i * hub->ctx_addr_distance, 281 lower_32_bits(adev->vm_manager.max_pfn - 1)); 282 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 283 i * hub->ctx_addr_distance, 284 upper_32_bits(adev->vm_manager.max_pfn - 1)); 285 } 286 } 287 288 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) 289 { 290 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 291 unsigned i; 292 293 for (i = 0; i < 18; ++i) { 294 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 295 i * hub->eng_addr_distance, 0xffffffff); 296 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 297 i * hub->eng_addr_distance, 0x1f); 298 } 299 } 300 301 static void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 302 bool enable) 303 { 304 if (amdgpu_sriov_vf(adev)) 305 return; 306 307 if (adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 308 amdgpu_dpm_set_powergating_by_smu(adev, 309 AMD_IP_BLOCK_TYPE_GMC, 310 enable); 311 } 312 313 static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 314 { 315 if (amdgpu_sriov_vf(adev)) { 316 /* 317 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 318 * VF copy registers so vbios post doesn't program them, for 319 * SRIOV driver need to program them 320 */ 321 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 322 adev->gmc.vram_start >> 24); 323 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 324 adev->gmc.vram_end >> 24); 325 } 326 327 /* GART Enable. */ 328 mmhub_v1_0_init_gart_aperture_regs(adev); 329 mmhub_v1_0_init_system_aperture_regs(adev); 330 mmhub_v1_0_init_tlb_regs(adev); 331 mmhub_v1_0_init_cache_regs(adev); 332 333 mmhub_v1_0_enable_system_domain(adev); 334 mmhub_v1_0_disable_identity_aperture(adev); 335 mmhub_v1_0_setup_vmid_config(adev); 336 mmhub_v1_0_program_invalidation(adev); 337 338 return 0; 339 } 340 341 static void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 342 { 343 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 344 u32 tmp; 345 u32 i; 346 347 /* Disable all tables */ 348 for (i = 0; i < AMDGPU_NUM_VMID; i++) 349 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, 350 i * hub->ctx_distance, 0); 351 352 /* Setup TLB control */ 353 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 354 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 355 tmp = REG_SET_FIELD(tmp, 356 MC_VM_MX_L1_TLB_CNTL, 357 ENABLE_ADVANCED_DRIVER_MODEL, 358 0); 359 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 360 361 if (!amdgpu_sriov_vf(adev)) { 362 /* Setup L2 cache */ 363 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 364 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 365 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 366 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); 367 } 368 } 369 370 /** 371 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 372 * 373 * @adev: amdgpu_device pointer 374 * @value: true redirects VM faults to the default page 375 */ 376 static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 377 { 378 u32 tmp; 379 380 if (amdgpu_sriov_vf(adev)) 381 return; 382 383 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 384 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 385 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 386 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 387 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 388 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 389 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 391 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392 tmp = REG_SET_FIELD(tmp, 393 VM_L2_PROTECTION_FAULT_CNTL, 394 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 395 value); 396 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 397 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 399 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 401 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 402 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 403 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 404 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 405 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 406 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 407 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 408 if (!value) { 409 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 410 CRASH_ON_NO_RETRY_FAULT, 1); 411 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 412 CRASH_ON_RETRY_FAULT, 1); 413 } 414 415 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 416 } 417 418 static void mmhub_v1_0_init(struct amdgpu_device *adev) 419 { 420 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 421 422 hub->ctx0_ptb_addr_lo32 = 423 SOC15_REG_OFFSET(MMHUB, 0, 424 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 425 hub->ctx0_ptb_addr_hi32 = 426 SOC15_REG_OFFSET(MMHUB, 0, 427 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 428 hub->vm_inv_eng0_sem = 429 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM); 430 hub->vm_inv_eng0_req = 431 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); 432 hub->vm_inv_eng0_ack = 433 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); 434 hub->vm_context0_cntl = 435 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); 436 hub->vm_l2_pro_fault_status = 437 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 438 hub->vm_l2_pro_fault_cntl = 439 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 440 441 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; 442 hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 443 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 444 hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ; 445 hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 446 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 447 } 448 449 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 450 bool enable) 451 { 452 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 453 454 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 455 456 if (adev->asic_type != CHIP_RAVEN) { 457 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 458 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 459 } else 460 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); 461 462 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 463 data |= ATC_L2_MISC_CG__ENABLE_MASK; 464 465 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 466 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 467 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 468 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 469 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 470 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 471 472 if (adev->asic_type != CHIP_RAVEN) 473 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 474 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 475 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 476 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 477 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 478 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 479 } else { 480 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 481 482 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 483 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 484 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 485 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 486 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 487 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 488 489 if (adev->asic_type != CHIP_RAVEN) 490 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 491 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 492 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 493 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 494 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 495 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 496 } 497 498 if (def != data) 499 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 500 501 if (def1 != data1) { 502 if (adev->asic_type != CHIP_RAVEN) 503 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 504 else 505 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 506 } 507 508 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 509 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 510 } 511 512 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 513 bool enable) 514 { 515 uint32_t def, data; 516 517 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 518 519 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 520 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 521 else 522 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 523 524 if (def != data) 525 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 526 } 527 528 static int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 529 enum amd_clockgating_state state) 530 { 531 if (amdgpu_sriov_vf(adev)) 532 return 0; 533 534 switch (adev->asic_type) { 535 case CHIP_VEGA10: 536 case CHIP_VEGA12: 537 case CHIP_VEGA20: 538 case CHIP_RAVEN: 539 case CHIP_RENOIR: 540 mmhub_v1_0_update_medium_grain_clock_gating(adev, 541 state == AMD_CG_STATE_GATE); 542 mmhub_v1_0_update_medium_grain_light_sleep(adev, 543 state == AMD_CG_STATE_GATE); 544 break; 545 default: 546 break; 547 } 548 549 return 0; 550 } 551 552 static void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 553 { 554 int data, data1; 555 556 if (amdgpu_sriov_vf(adev)) 557 *flags = 0; 558 559 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 560 561 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 562 563 /* AMD_CG_SUPPORT_MC_MGCG */ 564 if ((data & ATC_L2_MISC_CG__ENABLE_MASK) && 565 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 566 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 567 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 568 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 569 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 570 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 571 *flags |= AMD_CG_SUPPORT_MC_MGCG; 572 573 /* AMD_CG_SUPPORT_MC_LS */ 574 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 575 *flags |= AMD_CG_SUPPORT_MC_LS; 576 } 577 578 static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = { 579 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 580 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT), 581 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT), 582 }, 583 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 584 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT), 585 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT), 586 }, 587 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 588 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT), 589 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT), 590 }, 591 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 592 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT), 593 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT), 594 }, 595 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 596 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT), 597 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT), 598 }, 599 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 600 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT), 601 0, 0, 602 }, 603 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 604 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT), 605 0, 0, 606 }, 607 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 608 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT), 609 0, 0, 610 }, 611 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 612 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT), 613 0, 0, 614 }, 615 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 616 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT), 617 0, 0, 618 }, 619 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 620 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT), 621 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT), 622 }, 623 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 624 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT), 625 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT), 626 }, 627 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 628 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT), 629 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT), 630 }, 631 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 632 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT), 633 0, 0, 634 }, 635 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 636 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT), 637 0, 0, 638 }, 639 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 640 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT), 641 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT), 642 }, 643 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 644 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT), 645 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT), 646 }, 647 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 648 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT), 649 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT), 650 }, 651 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 652 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT), 653 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT), 654 }, 655 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 656 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT), 657 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT), 658 }, 659 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 660 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT), 661 0, 0, 662 }, 663 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 664 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT), 665 0, 0, 666 }, 667 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 668 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT), 669 0, 0, 670 }, 671 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 672 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT), 673 0, 0, 674 }, 675 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 676 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT), 677 0, 0, 678 }, 679 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 680 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT), 681 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT), 682 }, 683 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 684 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT), 685 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT), 686 }, 687 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 688 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT), 689 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT), 690 }, 691 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 692 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT), 693 0, 0, 694 }, 695 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 696 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT), 697 0, 0, 698 } 699 }; 700 701 static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = { 702 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0}, 703 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0}, 704 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0}, 705 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0}, 706 }; 707 708 static int mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev, 709 const struct soc15_reg_entry *reg, 710 uint32_t value, uint32_t *sec_count, uint32_t *ded_count) 711 { 712 uint32_t i; 713 uint32_t sec_cnt, ded_cnt; 714 715 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) { 716 if (mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset) 717 continue; 718 719 sec_cnt = (value & 720 mmhub_v1_0_ras_fields[i].sec_count_mask) >> 721 mmhub_v1_0_ras_fields[i].sec_count_shift; 722 if (sec_cnt) { 723 dev_info(adev->dev, 724 "MMHUB SubBlock %s, SEC %d\n", 725 mmhub_v1_0_ras_fields[i].name, 726 sec_cnt); 727 *sec_count += sec_cnt; 728 } 729 730 ded_cnt = (value & 731 mmhub_v1_0_ras_fields[i].ded_count_mask) >> 732 mmhub_v1_0_ras_fields[i].ded_count_shift; 733 if (ded_cnt) { 734 dev_info(adev->dev, 735 "MMHUB SubBlock %s, DED %d\n", 736 mmhub_v1_0_ras_fields[i].name, 737 ded_cnt); 738 *ded_count += ded_cnt; 739 } 740 } 741 742 return 0; 743 } 744 745 static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, 746 void *ras_error_status) 747 { 748 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 749 uint32_t sec_count = 0, ded_count = 0; 750 uint32_t i; 751 uint32_t reg_value; 752 753 err_data->ue_count = 0; 754 err_data->ce_count = 0; 755 756 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) { 757 reg_value = 758 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); 759 if (reg_value) 760 mmhub_v1_0_get_ras_error_count(adev, 761 &mmhub_v1_0_edc_cnt_regs[i], 762 reg_value, &sec_count, &ded_count); 763 } 764 765 err_data->ce_count += sec_count; 766 err_data->ue_count += ded_count; 767 } 768 769 static void mmhub_v1_0_reset_ras_error_count(struct amdgpu_device *adev) 770 { 771 uint32_t i; 772 773 /* read back edc counter registers to reset the counters to 0 */ 774 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) { 775 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) 776 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); 777 } 778 } 779 780 struct amdgpu_ras_block_hw_ops mmhub_v1_0_ras_hw_ops = { 781 .query_ras_error_count = mmhub_v1_0_query_ras_error_count, 782 .reset_ras_error_count = mmhub_v1_0_reset_ras_error_count, 783 }; 784 785 struct amdgpu_mmhub_ras mmhub_v1_0_ras = { 786 .ras_block = { 787 .hw_ops = &mmhub_v1_0_ras_hw_ops, 788 }, 789 }; 790 791 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = { 792 .get_fb_location = mmhub_v1_0_get_fb_location, 793 .init = mmhub_v1_0_init, 794 .gart_enable = mmhub_v1_0_gart_enable, 795 .set_fault_enable_default = mmhub_v1_0_set_fault_enable_default, 796 .gart_disable = mmhub_v1_0_gart_disable, 797 .set_clockgating = mmhub_v1_0_set_clockgating, 798 .get_clockgating = mmhub_v1_0_get_clockgating, 799 .setup_vm_pt_regs = mmhub_v1_0_setup_vm_pt_regs, 800 .update_power_gating = mmhub_v1_0_update_power_gating, 801 }; 802