1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc_v1_0.h" 29 #include "gc/gc_12_1_0_offset.h" 30 #include "gc/gc_12_1_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin"); 38 39 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block); 40 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); 41 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 42 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 43 44 #define MES_EOP_SIZE 2048 45 46 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 47 48 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) 49 { 50 struct amdgpu_device *adev = ring->adev; 51 52 if (ring->use_doorbell) { 53 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 54 ring->wptr); 55 WDOORBELL64(ring->doorbell_index, ring->wptr); 56 } else { 57 BUG(); 58 } 59 } 60 61 static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring) 62 { 63 return *ring->rptr_cpu_addr; 64 } 65 66 static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring) 67 { 68 u64 wptr; 69 70 if (ring->use_doorbell) 71 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 72 else 73 BUG(); 74 return wptr; 75 } 76 77 static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = { 78 .type = AMDGPU_RING_TYPE_MES, 79 .align_mask = 1, 80 .nop = 0, 81 .support_64bit_ptrs = true, 82 .get_rptr = mes_v12_1_ring_get_rptr, 83 .get_wptr = mes_v12_1_ring_get_wptr, 84 .set_wptr = mes_v12_1_ring_set_wptr, 85 .insert_nop = amdgpu_ring_insert_nop, 86 }; 87 88 static const char *mes_v12_1_opcodes[] = { 89 "SET_HW_RSRC", 90 "SET_SCHEDULING_CONFIG", 91 "ADD_QUEUE", 92 "REMOVE_QUEUE", 93 "PERFORM_YIELD", 94 "SET_GANG_PRIORITY_LEVEL", 95 "SUSPEND", 96 "RESUME", 97 "RESET", 98 "SET_LOG_BUFFER", 99 "CHANGE_GANG_PRORITY", 100 "QUERY_SCHEDULER_STATUS", 101 "unused", 102 "SET_DEBUG_VMID", 103 "MISC", 104 "UPDATE_ROOT_PAGE_TABLE", 105 "AMD_LOG", 106 "SET_SE_MODE", 107 "SET_GANG_SUBMIT", 108 "SET_HW_RSRC_1", 109 }; 110 111 static const char *mes_v12_1_misc_opcodes[] = { 112 "WRITE_REG", 113 "INV_GART", 114 "QUERY_STATUS", 115 "READ_REG", 116 "WAIT_REG_MEM", 117 "SET_SHADER_DEBUGGER", 118 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 119 "NOTIFY_TO_UNMAP_PROCESSES", 120 }; 121 122 static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt) 123 { 124 const char *op_str = NULL; 125 126 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes)) 127 op_str = mes_v12_1_opcodes[x_pkt->header.opcode]; 128 129 return op_str; 130 } 131 132 static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt) 133 { 134 const char *op_str = NULL; 135 136 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 137 (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes))) 138 op_str = mes_v12_1_misc_opcodes[x_pkt->opcode]; 139 140 return op_str; 141 } 142 143 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 144 int xcc_id, int pipe, void *pkt, 145 int size, int api_status_off) 146 { 147 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 148 signed long timeout = 2100000; /* 2100 ms */ 149 struct amdgpu_device *adev = mes->adev; 150 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; 151 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; 152 struct MES_API_STATUS *api_status; 153 union MESAPI__MISC *x_pkt = pkt; 154 const char *op_str, *misc_op_str; 155 unsigned long flags; 156 u64 status_gpu_addr; 157 u32 seq, status_offset; 158 u64 *status_ptr; 159 signed long r; 160 int ret; 161 162 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 163 return -EINVAL; 164 165 if (amdgpu_emu_mode) { 166 timeout *= 1000; 167 } else if (amdgpu_sriov_vf(adev)) { 168 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 169 timeout = 15 * 600 * 1000; 170 } 171 172 ret = amdgpu_device_wb_get(adev, &status_offset); 173 if (ret) 174 return ret; 175 176 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 177 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 178 *status_ptr = 0; 179 180 spin_lock_irqsave(ring_lock, flags); 181 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 182 if (r) 183 goto error_unlock_free; 184 185 seq = ++ring->fence_drv.sync_seq; 186 r = amdgpu_fence_wait_polling(ring, 187 seq - ring->fence_drv.num_fences_mask, 188 timeout); 189 if (r < 1) 190 goto error_undo; 191 192 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 193 api_status->api_completion_fence_addr = status_gpu_addr; 194 api_status->api_completion_fence_value = 1; 195 196 amdgpu_ring_write_multiple(ring, pkt, size / 4); 197 198 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 199 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 200 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 201 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 202 mes_status_pkt.api_status.api_completion_fence_addr = 203 ring->fence_drv.gpu_addr; 204 mes_status_pkt.api_status.api_completion_fence_value = seq; 205 206 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 207 sizeof(mes_status_pkt) / 4); 208 209 amdgpu_ring_commit(ring); 210 spin_unlock_irqrestore(ring_lock, flags); 211 212 op_str = mes_v12_1_get_op_string(x_pkt); 213 misc_op_str = mes_v12_1_get_misc_op_string(x_pkt); 214 215 if (misc_op_str) 216 dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n", 217 xcc_id, pipe, op_str, misc_op_str); 218 else if (op_str) 219 dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n", 220 xcc_id, pipe, op_str); 221 else 222 dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n", 223 xcc_id, pipe, x_pkt->header.opcode); 224 225 r = amdgpu_fence_wait_polling(ring, seq, timeout); 226 if (r < 1 || !*status_ptr) { 227 if (misc_op_str) 228 dev_err(adev->dev, 229 "MES(%d, %d) failed to respond to msg=%s (%s)\n", 230 xcc_id, pipe, op_str, misc_op_str); 231 else if (op_str) 232 dev_err(adev->dev, 233 "MES(%d, %d) failed to respond to msg=%s\n", 234 xcc_id, pipe, op_str); 235 else 236 dev_err(adev->dev, 237 "MES(%d, %d) failed to respond to msg=%d\n", 238 xcc_id, pipe, x_pkt->header.opcode); 239 240 while (halt_if_hws_hang) 241 schedule(); 242 243 r = -ETIMEDOUT; 244 goto error_wb_free; 245 } 246 247 amdgpu_device_wb_free(adev, status_offset); 248 return 0; 249 250 error_undo: 251 dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe); 252 amdgpu_ring_undo(ring); 253 254 error_unlock_free: 255 spin_unlock_irqrestore(ring_lock, flags); 256 257 error_wb_free: 258 amdgpu_device_wb_free(adev, status_offset); 259 return r; 260 } 261 262 static int convert_to_mes_queue_type(int queue_type) 263 { 264 if (queue_type == AMDGPU_RING_TYPE_GFX) 265 return MES_QUEUE_TYPE_GFX; 266 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 267 return MES_QUEUE_TYPE_COMPUTE; 268 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 269 return MES_QUEUE_TYPE_SDMA; 270 else if (queue_type == AMDGPU_RING_TYPE_MES) 271 return MES_QUEUE_TYPE_SCHQ; 272 else 273 BUG(); 274 return -1; 275 } 276 277 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, 278 struct mes_add_queue_input *input) 279 { 280 struct amdgpu_device *adev = mes->adev; 281 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 282 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 283 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 284 285 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 286 287 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 288 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 289 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 290 291 mes_add_queue_pkt.process_id = input->process_id; 292 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 293 mes_add_queue_pkt.process_va_start = input->process_va_start; 294 mes_add_queue_pkt.process_va_end = input->process_va_end; 295 mes_add_queue_pkt.process_quantum = input->process_quantum; 296 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 297 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 298 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 299 mes_add_queue_pkt.inprocess_gang_priority = 300 input->inprocess_gang_priority; 301 mes_add_queue_pkt.gang_global_priority_level = 302 input->gang_global_priority_level; 303 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 304 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 305 306 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 307 308 mes_add_queue_pkt.queue_type = 309 convert_to_mes_queue_type(input->queue_type); 310 mes_add_queue_pkt.paging = input->paging; 311 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 312 mes_add_queue_pkt.gws_base = input->gws_base; 313 mes_add_queue_pkt.gws_size = input->gws_size; 314 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 315 mes_add_queue_pkt.tma_addr = input->tma_addr; 316 mes_add_queue_pkt.trap_en = input->trap_en; 317 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 318 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 319 320 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 321 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 322 mes_add_queue_pkt.gds_size = input->queue_size; 323 324 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 325 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 326 mes_add_queue_pkt.gds_size = input->queue_size; 327 328 return mes_v12_1_submit_pkt_and_poll_completion(mes, 329 input->xcc_id, AMDGPU_MES_SCHED_PIPE, 330 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 331 offsetof(union MESAPI__ADD_QUEUE, api_status)); 332 } 333 334 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, 335 struct mes_remove_queue_input *input) 336 { 337 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 338 339 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 340 341 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 342 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 343 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 344 345 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 346 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 347 348 return mes_v12_1_submit_pkt_and_poll_completion(mes, 349 input->xcc_id, AMDGPU_MES_SCHED_PIPE, 350 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 351 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 352 } 353 354 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, 355 struct mes_reset_queue_input *input) 356 { 357 union MESAPI__RESET mes_reset_queue_pkt; 358 int pipe; 359 360 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 361 362 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 363 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 364 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 365 366 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 367 /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ 368 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 369 370 if (mes->adev->enable_uni_mes) 371 pipe = AMDGPU_MES_KIQ_PIPE; 372 else 373 pipe = AMDGPU_MES_SCHED_PIPE; 374 375 return mes_v12_1_submit_pkt_and_poll_completion(mes, 376 input->xcc_id, pipe, 377 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 378 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 379 } 380 381 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, 382 struct mes_map_legacy_queue_input *input) 383 { 384 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 385 int pipe; 386 387 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 388 389 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 390 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 391 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 392 393 mes_add_queue_pkt.pipe_id = input->pipe_id; 394 mes_add_queue_pkt.queue_id = input->queue_id; 395 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 396 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 397 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 398 mes_add_queue_pkt.queue_type = 399 convert_to_mes_queue_type(input->queue_type); 400 mes_add_queue_pkt.map_legacy_kq = 1; 401 402 if (mes->adev->enable_uni_mes) 403 pipe = AMDGPU_MES_KIQ_PIPE; 404 else 405 pipe = AMDGPU_MES_SCHED_PIPE; 406 407 return mes_v12_1_submit_pkt_and_poll_completion(mes, 408 input->xcc_id, pipe, 409 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 410 offsetof(union MESAPI__ADD_QUEUE, api_status)); 411 } 412 413 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, 414 struct mes_unmap_legacy_queue_input *input) 415 { 416 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 417 int pipe; 418 419 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 420 421 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 422 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 423 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 424 425 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 426 mes_remove_queue_pkt.gang_context_addr = 0; 427 428 mes_remove_queue_pkt.pipe_id = input->pipe_id; 429 mes_remove_queue_pkt.queue_id = input->queue_id; 430 431 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 432 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 433 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 434 mes_remove_queue_pkt.tf_data = 435 lower_32_bits(input->trail_fence_data); 436 } else { 437 mes_remove_queue_pkt.unmap_legacy_queue = 1; 438 mes_remove_queue_pkt.queue_type = 439 convert_to_mes_queue_type(input->queue_type); 440 } 441 442 if (mes->adev->enable_uni_mes) 443 pipe = AMDGPU_MES_KIQ_PIPE; 444 else 445 pipe = AMDGPU_MES_SCHED_PIPE; 446 447 return mes_v12_1_submit_pkt_and_poll_completion(mes, 448 input->xcc_id, pipe, 449 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 450 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 451 } 452 453 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, 454 struct mes_suspend_gang_input *input) 455 { 456 return 0; 457 } 458 459 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, 460 struct mes_resume_gang_input *input) 461 { 462 return 0; 463 } 464 465 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, 466 int pipe, int xcc_id) 467 { 468 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 469 470 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 471 472 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 473 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 474 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 475 476 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 477 &mes_status_pkt, sizeof(mes_status_pkt), 478 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 479 } 480 481 static int mes_v12_1_misc_op(struct amdgpu_mes *mes, 482 struct mes_misc_op_input *input) 483 { 484 union MESAPI__MISC misc_pkt; 485 int pipe; 486 487 if (mes->adev->enable_uni_mes) 488 pipe = AMDGPU_MES_KIQ_PIPE; 489 else 490 pipe = AMDGPU_MES_SCHED_PIPE; 491 492 memset(&misc_pkt, 0, sizeof(misc_pkt)); 493 494 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 495 misc_pkt.header.opcode = MES_SCH_API_MISC; 496 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 497 498 switch (input->op) { 499 case MES_MISC_OP_READ_REG: 500 misc_pkt.opcode = MESAPI_MISC__READ_REG; 501 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 502 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 503 break; 504 case MES_MISC_OP_WRITE_REG: 505 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 506 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 507 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 508 break; 509 case MES_MISC_OP_WRM_REG_WAIT: 510 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 511 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 512 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 513 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 514 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 515 misc_pkt.wait_reg_mem.reg_offset2 = 0; 516 break; 517 case MES_MISC_OP_WRM_REG_WR_WAIT: 518 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 519 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 520 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 521 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 522 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 523 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 524 break; 525 case MES_MISC_OP_SET_SHADER_DEBUGGER: 526 pipe = AMDGPU_MES_SCHED_PIPE; 527 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 528 misc_pkt.set_shader_debugger.process_context_addr = 529 input->set_shader_debugger.process_context_addr; 530 misc_pkt.set_shader_debugger.flags.u32all = 531 input->set_shader_debugger.flags.u32all; 532 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 533 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 534 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 535 input->set_shader_debugger.tcp_watch_cntl, 536 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 537 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 538 break; 539 case MES_MISC_OP_CHANGE_CONFIG: 540 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 541 misc_pkt.change_config.opcode = 542 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 543 misc_pkt.change_config.option.bits.limit_single_process = 544 input->change_config.option.limit_single_process; 545 break; 546 default: 547 DRM_ERROR("unsupported misc op (%d) \n", input->op); 548 return -EINVAL; 549 } 550 551 return mes_v12_1_submit_pkt_and_poll_completion(mes, 552 input->xcc_id, pipe, 553 &misc_pkt, sizeof(misc_pkt), 554 offsetof(union MESAPI__MISC, api_status)); 555 } 556 557 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, 558 int pipe, int xcc_id) 559 { 560 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 561 562 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 563 564 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 565 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 566 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 567 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 568 569 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 570 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 571 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 572 } 573 574 static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt) 575 { 576 /* 577 * GFX V12 has only one GFX pipe, but 8 queues in it. 578 * GFX pipe 0 queue 0 is being used by Kernel queue. 579 * Set GFX pipe 0 queue 1-7 for MES scheduling 580 * mask = 1111 1110b 581 */ 582 pkt->gfx_hqd_mask[0] = 0xFE; 583 } 584 585 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, 586 int pipe, int xcc_id) 587 { 588 int i; 589 struct amdgpu_device *adev = mes->adev; 590 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 591 592 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 593 594 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 595 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 596 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 597 598 if (pipe == AMDGPU_MES_SCHED_PIPE) { 599 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 600 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 601 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 602 mes_set_hw_res_pkt.paging_vmid = 0; 603 604 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 605 mes_set_hw_res_pkt.compute_hqd_mask[i] = 606 mes->compute_hqd_mask[i]; 607 608 mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt); 609 610 for (i = 0; i < MAX_SDMA_PIPES; i++) 611 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 612 mes->sdma_hqd_mask[i]; 613 614 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 615 mes_set_hw_res_pkt.aggregated_doorbells[i] = 616 mes->aggregated_doorbells[i]; 617 } 618 619 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 620 mes->sch_ctx_gpu_addr[pipe]; 621 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 622 mes->query_status_fence_gpu_addr[pipe]; 623 624 for (i = 0; i < 5; i++) { 625 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 626 mes_set_hw_res_pkt.mmhub_base[i] = 627 adev->reg_offset[MMHUB_HWIP][0][i]; 628 mes_set_hw_res_pkt.osssys_base[i] = 629 adev->reg_offset[OSSSYS_HWIP][0][i]; 630 } 631 632 mes_set_hw_res_pkt.disable_reset = 1; 633 mes_set_hw_res_pkt.disable_mes_log = 1; 634 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 635 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 636 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 637 638 /* 639 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 640 * handling support, other queue will not use the oversubscribe timer. 641 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 642 */ 643 mes_set_hw_res_pkt.oversubscription_timer = 50; 644 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 645 646 if (amdgpu_mes_log_enable) { 647 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 648 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 649 mes->event_log_gpu_addr + pipe * AMDGPU_MES_LOG_BUFFER_SIZE; 650 } 651 652 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 653 mes_set_hw_res_pkt.limit_single_process = 1; 654 655 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 656 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 657 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 658 } 659 660 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, 661 int xcc_id) 662 { 663 struct amdgpu_device *adev = mes->adev; 664 uint32_t data; 665 666 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1); 667 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 668 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 669 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 670 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 671 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 672 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 673 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data); 674 675 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2); 676 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 677 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 678 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 679 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 680 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 681 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 682 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data); 683 684 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3); 685 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 686 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 687 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 688 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 689 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 690 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 691 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data); 692 693 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4); 694 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 695 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 696 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 697 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 698 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 699 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 700 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data); 701 702 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5); 703 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 704 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 705 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 706 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 707 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 708 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 709 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data); 710 711 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 712 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data); 713 } 714 715 716 static void mes_v12_1_enable_unmapped_doorbell_handling( 717 struct amdgpu_mes *mes, bool enable, int xcc_id) 718 { 719 struct amdgpu_device *adev = mes->adev; 720 uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL); 721 722 /* 723 * The default PROC_LSB settng is 0xc which means doorbell 724 * addr[16:12] gives the doorbell page number. For kfd, each 725 * process will use 2 pages of doorbell, we need to change the 726 * setting to 0xd 727 */ 728 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 729 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 730 731 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 732 733 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data); 734 } 735 736 #if 0 737 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, 738 struct mes_reset_legacy_queue_input *input) 739 { 740 union MESAPI__RESET mes_reset_queue_pkt; 741 int pipe; 742 743 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 744 745 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 746 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 747 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 748 749 mes_reset_queue_pkt.queue_type = 750 convert_to_mes_queue_type(input->queue_type); 751 752 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 753 mes_reset_queue_pkt.reset_legacy_gfx = 1; 754 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 755 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 756 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 757 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 758 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 759 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 760 } else { 761 mes_reset_queue_pkt.reset_queue_only = 1; 762 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 763 } 764 765 if (mes->adev->enable_uni_mes) 766 pipe = AMDGPU_MES_KIQ_PIPE; 767 else 768 pipe = AMDGPU_MES_SCHED_PIPE; 769 770 return mes_v12_1_submit_pkt_and_poll_completion(mes, 771 input->xcc_id, pipe, 772 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 773 offsetof(union MESAPI__RESET, api_status)); 774 } 775 #endif 776 777 static const struct amdgpu_mes_funcs mes_v12_1_funcs = { 778 .add_hw_queue = mes_v12_1_add_hw_queue, 779 .remove_hw_queue = mes_v12_1_remove_hw_queue, 780 .map_legacy_queue = mes_v12_1_map_legacy_queue, 781 .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue, 782 .suspend_gang = mes_v12_1_suspend_gang, 783 .resume_gang = mes_v12_1_resume_gang, 784 .misc_op = mes_v12_1_misc_op, 785 .reset_hw_queue = mes_v12_1_reset_hw_queue, 786 }; 787 788 static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev, 789 enum amdgpu_mes_pipe pipe, 790 int xcc_id) 791 { 792 int r, inst = MES_PIPE_INST(xcc_id, pipe); 793 const struct mes_firmware_header_v1_0 *mes_hdr; 794 const __le32 *fw_data; 795 unsigned fw_size; 796 797 mes_hdr = (const struct mes_firmware_header_v1_0 *) 798 adev->mes.fw[pipe]->data; 799 800 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 801 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 802 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 803 804 r = amdgpu_bo_create_reserved(adev, fw_size, 805 PAGE_SIZE, 806 AMDGPU_GEM_DOMAIN_VRAM, 807 &adev->mes.ucode_fw_obj[inst], 808 &adev->mes.ucode_fw_gpu_addr[inst], 809 (void **)&adev->mes.ucode_fw_ptr[inst]); 810 if (r) { 811 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 812 return r; 813 } 814 815 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size); 816 817 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]); 818 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]); 819 820 return 0; 821 } 822 823 static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 824 enum amdgpu_mes_pipe pipe, 825 int xcc_id) 826 { 827 int r, inst = MES_PIPE_INST(xcc_id, pipe); 828 const struct mes_firmware_header_v1_0 *mes_hdr; 829 const __le32 *fw_data; 830 unsigned fw_size; 831 832 mes_hdr = (const struct mes_firmware_header_v1_0 *) 833 adev->mes.fw[pipe]->data; 834 835 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 836 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 837 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 838 839 r = amdgpu_bo_create_reserved(adev, fw_size, 840 64 * 1024, 841 AMDGPU_GEM_DOMAIN_VRAM, 842 &adev->mes.data_fw_obj[inst], 843 &adev->mes.data_fw_gpu_addr[inst], 844 (void **)&adev->mes.data_fw_ptr[inst]); 845 if (r) { 846 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 847 return r; 848 } 849 850 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size); 851 852 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]); 853 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]); 854 855 return 0; 856 } 857 858 static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev, 859 enum amdgpu_mes_pipe pipe, 860 int xcc_id) 861 { 862 int inst = MES_PIPE_INST(xcc_id, pipe); 863 864 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst], 865 &adev->mes.data_fw_gpu_addr[inst], 866 (void **)&adev->mes.data_fw_ptr[inst]); 867 868 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst], 869 &adev->mes.ucode_fw_gpu_addr[inst], 870 (void **)&adev->mes.ucode_fw_ptr[inst]); 871 } 872 873 static void mes_v12_1_enable(struct amdgpu_device *adev, 874 bool enable, int xcc_id) 875 { 876 uint64_t ucode_addr; 877 uint32_t pipe, data = 0; 878 879 if (enable) { 880 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 881 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 882 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 883 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 884 885 mutex_lock(&adev->srbm_mutex); 886 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 887 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, 888 GET_INST(GC, xcc_id)); 889 890 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 891 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 892 regCP_MES_PRGRM_CNTR_START, 893 lower_32_bits(ucode_addr)); 894 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 895 regCP_MES_PRGRM_CNTR_START_HI, 896 upper_32_bits(ucode_addr)); 897 } 898 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 899 mutex_unlock(&adev->srbm_mutex); 900 901 /* unhalt MES and activate pipe0 */ 902 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 903 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 904 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 905 906 if (amdgpu_emu_mode) 907 msleep(500); 908 else if (adev->enable_uni_mes) 909 udelay(500); 910 else 911 udelay(50); 912 } else { 913 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 914 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 915 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 916 data = REG_SET_FIELD(data, CP_MES_CNTL, 917 MES_INVALIDATE_ICACHE, 1); 918 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 919 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 920 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 921 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 922 } 923 } 924 925 static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev, 926 int xcc_id) 927 { 928 uint64_t ucode_addr; 929 int pipe; 930 931 mes_v12_1_enable(adev, false, xcc_id); 932 933 mutex_lock(&adev->srbm_mutex); 934 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 935 /* me=3, queue=0 */ 936 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 937 938 /* set ucode start address */ 939 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 940 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START, 941 lower_32_bits(ucode_addr)); 942 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI, 943 upper_32_bits(ucode_addr)); 944 945 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 946 } 947 mutex_unlock(&adev->srbm_mutex); 948 } 949 950 /* This function is for backdoor MES firmware */ 951 static int mes_v12_1_load_microcode(struct amdgpu_device *adev, 952 enum amdgpu_mes_pipe pipe, 953 bool prime_icache, int xcc_id) 954 { 955 int r, inst = MES_PIPE_INST(xcc_id, pipe); 956 uint32_t data; 957 958 mes_v12_1_enable(adev, false, xcc_id); 959 960 if (!adev->mes.fw[pipe]) 961 return -EINVAL; 962 963 r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id); 964 if (r) 965 return r; 966 967 r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id); 968 if (r) { 969 mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id); 970 return r; 971 } 972 973 mutex_lock(&adev->srbm_mutex); 974 /* me=3, pipe=0, queue=0 */ 975 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 976 977 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0); 978 979 /* set ucode fimrware address */ 980 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO, 981 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 982 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI, 983 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 984 985 /* set ucode instruction cache boundary to 2M-1 */ 986 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF); 987 988 /* set ucode data firmware address */ 989 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO, 990 lower_32_bits(adev->mes.data_fw_gpu_addr[inst])); 991 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI, 992 upper_32_bits(adev->mes.data_fw_gpu_addr[inst])); 993 994 /* Set data cache boundary CP_MES_MDBOUND_LO */ 995 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF); 996 997 if (prime_icache) { 998 /* invalidate ICACHE */ 999 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1000 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1001 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1002 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1003 1004 /* prime the ICACHE. */ 1005 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1006 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1007 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1008 } 1009 1010 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1011 mutex_unlock(&adev->srbm_mutex); 1012 1013 return 0; 1014 } 1015 1016 static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev, 1017 enum amdgpu_mes_pipe pipe, 1018 int xcc_id) 1019 { 1020 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1021 u32 *eop; 1022 1023 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1024 AMDGPU_GEM_DOMAIN_GTT, 1025 &adev->mes.eop_gpu_obj[inst], 1026 &adev->mes.eop_gpu_addr[inst], 1027 (void **)&eop); 1028 if (r) { 1029 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1030 return r; 1031 } 1032 1033 memset(eop, 0, 1034 adev->mes.eop_gpu_obj[inst]->tbo.base.size); 1035 1036 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]); 1037 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]); 1038 1039 return 0; 1040 } 1041 1042 static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) 1043 { 1044 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1045 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1046 uint32_t tmp; 1047 1048 mqd->header = 0xC0310800; 1049 mqd->compute_pipelinestat_enable = 0x00000001; 1050 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1051 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1052 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1053 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1054 mqd->compute_misc_reserved = 0x00000007; 1055 1056 eop_base_addr = ring->eop_gpu_addr >> 8; 1057 1058 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1059 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1060 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1061 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1062 1063 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1064 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1065 mqd->cp_hqd_eop_control = tmp; 1066 1067 /* disable the queue if it's active */ 1068 ring->wptr = 0; 1069 mqd->cp_hqd_pq_rptr = 0; 1070 mqd->cp_hqd_pq_wptr_lo = 0; 1071 mqd->cp_hqd_pq_wptr_hi = 0; 1072 1073 /* set the pointer to the MQD */ 1074 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1075 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1076 1077 /* set MQD vmid to 0 */ 1078 tmp = regCP_MQD_CONTROL_DEFAULT; 1079 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1080 mqd->cp_mqd_control = tmp; 1081 1082 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1083 hqd_gpu_addr = ring->gpu_addr >> 8; 1084 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1085 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1086 1087 /* set the wb address whether it's enabled or not */ 1088 wb_gpu_addr = ring->rptr_gpu_addr; 1089 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1090 mqd->cp_hqd_pq_rptr_report_addr_hi = 1091 upper_32_bits(wb_gpu_addr) & 0xffff; 1092 1093 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1094 wb_gpu_addr = ring->wptr_gpu_addr; 1095 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1096 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1097 1098 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1099 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1101 (order_base_2(ring->ring_size / 4) - 1)); 1102 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1103 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1104 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1106 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1107 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1108 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1109 mqd->cp_hqd_pq_control = tmp; 1110 1111 /* enable doorbell */ 1112 tmp = 0; 1113 if (ring->use_doorbell) { 1114 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1115 DOORBELL_OFFSET, ring->doorbell_index); 1116 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1117 DOORBELL_EN, 1); 1118 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1119 DOORBELL_SOURCE, 0); 1120 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1121 DOORBELL_HIT, 0); 1122 } else { 1123 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1124 DOORBELL_EN, 0); 1125 } 1126 mqd->cp_hqd_pq_doorbell_control = tmp; 1127 1128 mqd->cp_hqd_vmid = 0; 1129 /* activate the queue */ 1130 mqd->cp_hqd_active = 1; 1131 1132 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1133 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1134 PRELOAD_SIZE, 0x63); 1135 mqd->cp_hqd_persistent_state = tmp; 1136 1137 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT; 1138 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1139 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1140 1141 /* 1142 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1143 * doorbell handling. This is a reserved CP internal register can 1144 * not be accesss by others 1145 */ 1146 //mqd->cp_hqd_gfx_control = BIT(15); 1147 1148 return 0; 1149 } 1150 1151 static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring, 1152 int xcc_id) 1153 { 1154 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1155 struct amdgpu_device *adev = ring->adev; 1156 uint32_t data = 0; 1157 1158 mutex_lock(&adev->srbm_mutex); 1159 soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id)); 1160 1161 /* set CP_HQD_VMID.VMID = 0. */ 1162 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID); 1163 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1164 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data); 1165 1166 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1167 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1168 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1169 DOORBELL_EN, 0); 1170 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1171 1172 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1173 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1174 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1175 1176 /* set CP_MQD_CONTROL.VMID=0 */ 1177 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1178 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1179 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0); 1180 1181 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1183 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1184 1185 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1186 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1187 mqd->cp_hqd_pq_rptr_report_addr_lo); 1188 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1189 mqd->cp_hqd_pq_rptr_report_addr_hi); 1190 1191 /* set CP_HQD_PQ_CONTROL */ 1192 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1193 1194 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1195 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1196 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1197 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1198 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1199 1200 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1201 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1202 mqd->cp_hqd_pq_doorbell_control); 1203 1204 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1205 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1206 1207 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1208 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1209 1210 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1211 mutex_unlock(&adev->srbm_mutex); 1212 } 1213 1214 static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id) 1215 { 1216 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 1217 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; 1218 int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1219 1220 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1221 return -EINVAL; 1222 1223 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1224 if (r) { 1225 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1226 return r; 1227 } 1228 1229 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); 1230 1231 r = amdgpu_ring_test_ring(kiq_ring); 1232 if (r) { 1233 DRM_ERROR("kfq enable failed\n"); 1234 kiq_ring->sched.ready = false; 1235 } 1236 return r; 1237 } 1238 1239 static int mes_v12_1_queue_init(struct amdgpu_device *adev, 1240 enum amdgpu_mes_pipe pipe, 1241 int xcc_id) 1242 { 1243 struct amdgpu_ring *ring; 1244 int r; 1245 1246 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1247 ring = &adev->gfx.kiq[xcc_id].ring; 1248 else 1249 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)]; 1250 1251 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1252 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1253 *(ring->wptr_cpu_addr) = 0; 1254 *(ring->rptr_cpu_addr) = 0; 1255 amdgpu_ring_clear_ring(ring); 1256 } 1257 1258 r = mes_v12_1_mqd_init(ring); 1259 if (r) 1260 return r; 1261 1262 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1263 if (adev->enable_uni_mes) 1264 r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id); 1265 else 1266 r = mes_v12_1_kiq_enable_queue(adev, xcc_id); 1267 if (r) 1268 return r; 1269 } else { 1270 mes_v12_1_queue_init_register(ring, xcc_id); 1271 } 1272 1273 /* get MES scheduler/KIQ versions */ 1274 mutex_lock(&adev->srbm_mutex); 1275 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1276 1277 if (pipe == AMDGPU_MES_SCHED_PIPE) 1278 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 1279 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1280 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 1281 1282 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1283 mutex_unlock(&adev->srbm_mutex); 1284 1285 return 0; 1286 } 1287 1288 static int mes_v12_1_ring_init(struct amdgpu_device *adev, 1289 int xcc_id, int pipe) 1290 { 1291 struct amdgpu_ring *ring; 1292 int inst = MES_PIPE_INST(xcc_id, pipe); 1293 1294 ring = &adev->mes.ring[inst]; 1295 1296 ring->funcs = &mes_v12_1_ring_funcs; 1297 1298 ring->me = 3; 1299 ring->pipe = pipe; 1300 ring->queue = 0; 1301 ring->xcc_id = xcc_id; 1302 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1303 1304 ring->ring_obj = NULL; 1305 ring->use_doorbell = true; 1306 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1307 ring->no_scheduler = true; 1308 snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu", 1309 (unsigned char)xcc_id, (unsigned char)ring->me, 1310 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1311 1312 if (pipe == AMDGPU_MES_SCHED_PIPE) 1313 ring->doorbell_index = 1314 (adev->doorbell_index.mes_ring0 + 1315 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1316 << 1; 1317 else 1318 ring->doorbell_index = 1319 (adev->doorbell_index.mes_ring1 + 1320 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1321 << 1; 1322 1323 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1324 AMDGPU_RING_PRIO_DEFAULT, NULL); 1325 } 1326 1327 static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id) 1328 { 1329 struct amdgpu_ring *ring; 1330 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1331 1332 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); 1333 1334 ring = &adev->gfx.kiq[xcc_id].ring; 1335 1336 ring->me = 3; 1337 ring->pipe = 1; 1338 ring->queue = 0; 1339 ring->xcc_id = xcc_id; 1340 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1341 1342 ring->adev = NULL; 1343 ring->ring_obj = NULL; 1344 ring->use_doorbell = true; 1345 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1346 ring->no_scheduler = true; 1347 ring->doorbell_index = 1348 (adev->doorbell_index.mes_ring1 + 1349 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1350 << 1; 1351 1352 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu", 1353 (unsigned char)xcc_id, (unsigned char)ring->me, 1354 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1355 1356 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1357 AMDGPU_RING_PRIO_DEFAULT, NULL); 1358 } 1359 1360 static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev, 1361 enum amdgpu_mes_pipe pipe, 1362 int xcc_id) 1363 { 1364 int r, mqd_size = sizeof(struct v12_1_mes_mqd); 1365 struct amdgpu_ring *ring; 1366 int inst = MES_PIPE_INST(xcc_id, pipe); 1367 1368 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1369 ring = &adev->gfx.kiq[xcc_id].ring; 1370 else 1371 ring = &adev->mes.ring[inst]; 1372 1373 if (ring->mqd_obj) 1374 return 0; 1375 1376 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1377 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1378 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1379 if (r) { 1380 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1381 return r; 1382 } 1383 1384 memset(ring->mqd_ptr, 0, mqd_size); 1385 1386 /* prepare MQD backup */ 1387 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL); 1388 if (!adev->mes.mqd_backup[inst]) 1389 dev_warn(adev->dev, 1390 "no memory to create MQD backup for ring %s\n", 1391 ring->name); 1392 1393 return 0; 1394 } 1395 1396 static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1397 { 1398 struct amdgpu_device *adev = ip_block->adev; 1399 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1400 1401 adev->mes.funcs = &mes_v12_1_funcs; 1402 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; 1403 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; 1404 adev->mes.enable_legacy_queue_map = true; 1405 1406 adev->mes.event_log_size = 1407 adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE; 1408 1409 r = amdgpu_mes_init(adev); 1410 if (r) 1411 return r; 1412 1413 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1414 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1415 r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id); 1416 if (r) 1417 return r; 1418 1419 r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id); 1420 if (r) 1421 return r; 1422 1423 if (!adev->enable_uni_mes && pipe == 1424 AMDGPU_MES_KIQ_PIPE) 1425 r = mes_v12_1_kiq_ring_init(adev, xcc_id); 1426 else 1427 r = mes_v12_1_ring_init(adev, xcc_id, pipe); 1428 if (r) 1429 return r; 1430 } 1431 } 1432 1433 return 0; 1434 } 1435 1436 static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1437 { 1438 struct amdgpu_device *adev = ip_block->adev; 1439 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1440 1441 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1442 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1443 inst = MES_PIPE_INST(xcc_id, pipe); 1444 1445 kfree(adev->mes.mqd_backup[inst]); 1446 1447 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], 1448 &adev->mes.eop_gpu_addr[inst], 1449 NULL); 1450 amdgpu_ucode_release(&adev->mes.fw[inst]); 1451 1452 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1453 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, 1454 &adev->mes.ring[inst].mqd_gpu_addr, 1455 &adev->mes.ring[inst].mqd_ptr); 1456 amdgpu_ring_fini(&adev->mes.ring[inst]); 1457 } 1458 } 1459 } 1460 1461 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1462 if (!adev->enable_uni_mes) { 1463 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, 1464 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, 1465 &adev->gfx.kiq[xcc_id].ring.mqd_ptr); 1466 amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring); 1467 } 1468 1469 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1470 mes_v12_1_free_ucode_buffers(adev, 1471 AMDGPU_MES_KIQ_PIPE, xcc_id); 1472 mes_v12_1_free_ucode_buffers(adev, 1473 AMDGPU_MES_SCHED_PIPE, xcc_id); 1474 } 1475 } 1476 1477 amdgpu_mes_fini(adev); 1478 return 0; 1479 } 1480 1481 static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev, 1482 int xcc_id) 1483 { 1484 uint32_t data; 1485 int i; 1486 1487 mutex_lock(&adev->srbm_mutex); 1488 soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0, 1489 GET_INST(GC, xcc_id)); 1490 1491 /* disable the queue if it's active */ 1492 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1493 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1494 for (i = 0; i < adev->usec_timeout; i++) { 1495 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1496 break; 1497 udelay(1); 1498 } 1499 } 1500 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1501 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1502 DOORBELL_EN, 0); 1503 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1504 DOORBELL_HIT, 1); 1505 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1506 1507 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1508 1509 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1510 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1511 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1512 1513 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1514 mutex_unlock(&adev->srbm_mutex); 1515 1516 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false; 1517 } 1518 1519 static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1520 { 1521 uint32_t tmp; 1522 struct amdgpu_device *adev = ring->adev; 1523 1524 /* tell RLC which is KIQ queue */ 1525 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1526 tmp &= 0xffffff00; 1527 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1528 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1529 tmp |= 0x80; 1530 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1531 } 1532 1533 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1534 { 1535 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1536 int r = 0; 1537 struct amdgpu_ip_block *ip_block; 1538 1539 if (adev->enable_uni_mes) 1540 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id); 1541 else 1542 mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id); 1543 1544 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1545 1546 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, 1547 false, xcc_id); 1548 if (r) { 1549 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1550 return r; 1551 } 1552 1553 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, 1554 true, xcc_id); 1555 if (r) { 1556 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1557 return r; 1558 } 1559 1560 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1561 1562 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1563 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1564 1565 mes_v12_1_enable(adev, true, xcc_id); 1566 1567 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1568 if (unlikely(!ip_block)) { 1569 dev_err(adev->dev, "Failed to get MES handle\n"); 1570 return -EINVAL; 1571 } 1572 1573 r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id); 1574 if (r) 1575 goto failure; 1576 1577 if (adev->enable_uni_mes) { 1578 r = mes_v12_1_set_hw_resources(&adev->mes, 1579 AMDGPU_MES_KIQ_PIPE, xcc_id); 1580 if (r) 1581 goto failure; 1582 1583 mes_v12_1_set_hw_resources_1(&adev->mes, 1584 AMDGPU_MES_KIQ_PIPE, xcc_id); 1585 } 1586 1587 if (adev->mes.enable_legacy_queue_map) { 1588 r = mes_v12_1_hw_init(ip_block); 1589 if (r) 1590 goto failure; 1591 } 1592 1593 return r; 1594 1595 failure: 1596 mes_v12_1_hw_fini(ip_block); 1597 return r; 1598 } 1599 1600 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1601 { 1602 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1603 1604 if (adev->mes.ring[inst].sched.ready) { 1605 if (adev->enable_uni_mes) 1606 amdgpu_mes_unmap_legacy_queue(adev, 1607 &adev->mes.ring[inst], 1608 RESET_QUEUES, 0, 0, xcc_id); 1609 else 1610 mes_v12_1_kiq_dequeue_sched(adev, xcc_id); 1611 1612 adev->mes.ring[inst].sched.ready = false; 1613 } 1614 1615 mes_v12_1_enable(adev, false, xcc_id); 1616 1617 return 0; 1618 } 1619 1620 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) 1621 { 1622 int r; 1623 struct amdgpu_device *adev = ip_block->adev; 1624 1625 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready) 1626 goto out; 1627 1628 if (!adev->enable_mes_kiq) { 1629 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1630 r = mes_v12_1_load_microcode(adev, 1631 AMDGPU_MES_SCHED_PIPE, true, xcc_id); 1632 if (r) { 1633 DRM_ERROR("failed to MES fw, r=%d\n", r); 1634 return r; 1635 } 1636 1637 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1638 1639 } else if (adev->firmware.load_type == 1640 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1641 1642 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1643 } 1644 1645 mes_v12_1_enable(adev, true, xcc_id); 1646 } 1647 1648 /* Enable the MES to handle doorbell ring on unmapped queue */ 1649 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id); 1650 1651 r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id); 1652 if (r) 1653 goto failure; 1654 1655 r = mes_v12_1_set_hw_resources(&adev->mes, 1656 AMDGPU_MES_SCHED_PIPE, xcc_id); 1657 if (r) 1658 goto failure; 1659 1660 if (adev->enable_uni_mes) 1661 mes_v12_1_set_hw_resources_1(&adev->mes, 1662 AMDGPU_MES_SCHED_PIPE, xcc_id); 1663 1664 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); 1665 1666 r = mes_v12_1_query_sched_status(&adev->mes, 1667 AMDGPU_MES_SCHED_PIPE, xcc_id); 1668 if (r) { 1669 DRM_ERROR("MES is busy\n"); 1670 goto failure; 1671 } 1672 1673 out: 1674 /* 1675 * Disable KIQ ring usage from the driver once MES is enabled. 1676 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1677 * with MES enabled. 1678 */ 1679 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1680 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true; 1681 1682 return 0; 1683 1684 failure: 1685 mes_v12_1_hw_fini(ip_block); 1686 return r; 1687 } 1688 1689 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 1690 { 1691 struct amdgpu_device *adev = ip_block->adev; 1692 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1693 1694 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1695 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1696 if (r) 1697 return r; 1698 } 1699 1700 return 0; 1701 } 1702 1703 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 1704 { 1705 return 0; 1706 } 1707 1708 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) 1709 { 1710 int r; 1711 1712 r = amdgpu_mes_suspend(ip_block->adev); 1713 if (r) 1714 return r; 1715 1716 return mes_v12_1_hw_fini(ip_block); 1717 } 1718 1719 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) 1720 { 1721 int r; 1722 1723 r = mes_v12_1_hw_init(ip_block); 1724 if (r) 1725 return r; 1726 1727 return amdgpu_mes_resume(ip_block->adev); 1728 } 1729 1730 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) 1731 { 1732 struct amdgpu_device *adev = ip_block->adev; 1733 int pipe, r; 1734 1735 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1736 r = amdgpu_mes_init_microcode(adev, pipe); 1737 if (r) 1738 return r; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static const struct amd_ip_funcs mes_v12_1_ip_funcs = { 1745 .name = "mes_v12_1", 1746 .early_init = mes_v12_1_early_init, 1747 .late_init = NULL, 1748 .sw_init = mes_v12_1_sw_init, 1749 .sw_fini = mes_v12_1_sw_fini, 1750 .hw_init = mes_v12_1_hw_init, 1751 .hw_fini = mes_v12_1_hw_fini, 1752 .suspend = mes_v12_1_suspend, 1753 .resume = mes_v12_1_resume, 1754 }; 1755 1756 const struct amdgpu_ip_block_version mes_v12_1_ip_block = { 1757 .type = AMD_IP_BLOCK_TYPE_MES, 1758 .major = 12, 1759 .minor = 1, 1760 .rev = 0, 1761 .funcs = &mes_v12_1_ip_funcs, 1762 }; 1763