1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc_v1_0.h" 29 #include "gc/gc_12_1_0_offset.h" 30 #include "gc/gc_12_1_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 #include "gfx_v12_1_pkt.h" 35 #include "sdma_v7_1_0_pkt_open.h" 36 37 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin"); 40 41 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block); 42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id); 43 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 46 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id); 47 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id); 48 49 #define MES_EOP_SIZE 2048 50 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 #define MES12_HUNG_HQD_INFO_OFFSET 4 52 53 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 54 #define XCC_MID_MASK 0x41000000 55 56 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) 57 { 58 struct amdgpu_device *adev = ring->adev; 59 60 if (ring->use_doorbell) { 61 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 62 ring->wptr); 63 WDOORBELL64(ring->doorbell_index, ring->wptr); 64 } else { 65 BUG(); 66 } 67 } 68 69 static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring) 70 { 71 return *ring->rptr_cpu_addr; 72 } 73 74 static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring) 75 { 76 u64 wptr; 77 78 if (ring->use_doorbell) 79 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 80 else 81 BUG(); 82 return wptr; 83 } 84 85 static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = { 86 .type = AMDGPU_RING_TYPE_MES, 87 .align_mask = 1, 88 .nop = 0, 89 .support_64bit_ptrs = true, 90 .get_rptr = mes_v12_1_ring_get_rptr, 91 .get_wptr = mes_v12_1_ring_get_wptr, 92 .set_wptr = mes_v12_1_ring_set_wptr, 93 .insert_nop = amdgpu_ring_insert_nop, 94 }; 95 96 static const char *mes_v12_1_opcodes[] = { 97 "SET_HW_RSRC", 98 "SET_SCHEDULING_CONFIG", 99 "ADD_QUEUE", 100 "REMOVE_QUEUE", 101 "PERFORM_YIELD", 102 "SET_GANG_PRIORITY_LEVEL", 103 "SUSPEND", 104 "RESUME", 105 "RESET", 106 "SET_LOG_BUFFER", 107 "CHANGE_GANG_PRORITY", 108 "QUERY_SCHEDULER_STATUS", 109 "unused", 110 "SET_DEBUG_VMID", 111 "MISC", 112 "UPDATE_ROOT_PAGE_TABLE", 113 "AMD_LOG", 114 "SET_SE_MODE", 115 "SET_GANG_SUBMIT", 116 "SET_HW_RSRC_1", 117 "INVALIDATE_TLBS", 118 }; 119 120 static const char *mes_v12_1_misc_opcodes[] = { 121 "WRITE_REG", 122 "INV_GART", 123 "QUERY_STATUS", 124 "READ_REG", 125 "WAIT_REG_MEM", 126 "SET_SHADER_DEBUGGER", 127 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 128 "NOTIFY_TO_UNMAP_PROCESSES", 129 }; 130 131 static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt) 132 { 133 const char *op_str = NULL; 134 135 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes)) 136 op_str = mes_v12_1_opcodes[x_pkt->header.opcode]; 137 138 return op_str; 139 } 140 141 static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt) 142 { 143 const char *op_str = NULL; 144 145 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 146 (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes))) 147 op_str = mes_v12_1_misc_opcodes[x_pkt->opcode]; 148 149 return op_str; 150 } 151 152 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 153 int xcc_id, int pipe, void *pkt, 154 int size, int api_status_off) 155 { 156 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 157 signed long timeout = 2100000; /* 2100 ms */ 158 struct amdgpu_device *adev = mes->adev; 159 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; 160 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; 161 struct MES_API_STATUS *api_status; 162 union MESAPI__MISC *x_pkt = pkt; 163 const char *op_str, *misc_op_str; 164 unsigned long flags; 165 u64 status_gpu_addr; 166 u32 seq, status_offset; 167 u64 *status_ptr; 168 signed long r; 169 int ret; 170 171 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 172 return -EINVAL; 173 174 if (amdgpu_emu_mode) { 175 timeout *= 1000; 176 } else if (amdgpu_sriov_vf(adev)) { 177 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 178 timeout = 15 * 600 * 1000; 179 } 180 181 ret = amdgpu_device_wb_get(adev, &status_offset); 182 if (ret) 183 return ret; 184 185 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 186 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 187 *status_ptr = 0; 188 189 spin_lock_irqsave(ring_lock, flags); 190 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 191 if (r) 192 goto error_unlock_free; 193 194 seq = ++ring->fence_drv.sync_seq; 195 r = amdgpu_fence_wait_polling(ring, 196 seq - ring->fence_drv.num_fences_mask, 197 timeout); 198 if (r < 1) 199 goto error_undo; 200 201 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 202 api_status->api_completion_fence_addr = status_gpu_addr; 203 api_status->api_completion_fence_value = 1; 204 205 amdgpu_ring_write_multiple(ring, pkt, size / 4); 206 207 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 208 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 209 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 210 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 211 mes_status_pkt.api_status.api_completion_fence_addr = 212 ring->fence_drv.gpu_addr; 213 mes_status_pkt.api_status.api_completion_fence_value = seq; 214 215 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 216 sizeof(mes_status_pkt) / 4); 217 218 amdgpu_ring_commit(ring); 219 spin_unlock_irqrestore(ring_lock, flags); 220 221 op_str = mes_v12_1_get_op_string(x_pkt); 222 misc_op_str = mes_v12_1_get_misc_op_string(x_pkt); 223 224 if (misc_op_str) 225 dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n", 226 xcc_id, pipe, op_str, misc_op_str); 227 else if (op_str) 228 dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n", 229 xcc_id, pipe, op_str); 230 else 231 dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n", 232 xcc_id, pipe, x_pkt->header.opcode); 233 234 r = amdgpu_fence_wait_polling(ring, seq, timeout); 235 if (r < 1 || !lower_32_bits(*status_ptr)) { 236 if (misc_op_str) 237 dev_err(adev->dev, 238 "MES(%d, %d) failed to respond to msg=%s (%s)\n", 239 xcc_id, pipe, op_str, misc_op_str); 240 else if (op_str) 241 dev_err(adev->dev, 242 "MES(%d, %d) failed to respond to msg=%s\n", 243 xcc_id, pipe, op_str); 244 else 245 dev_err(adev->dev, 246 "MES(%d, %d) failed to respond to msg=%d\n", 247 xcc_id, pipe, x_pkt->header.opcode); 248 249 while (halt_if_hws_hang) 250 schedule(); 251 252 r = -ETIMEDOUT; 253 goto error_wb_free; 254 } 255 256 amdgpu_device_wb_free(adev, status_offset); 257 return 0; 258 259 error_undo: 260 dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe); 261 amdgpu_ring_undo(ring); 262 263 error_unlock_free: 264 spin_unlock_irqrestore(ring_lock, flags); 265 266 error_wb_free: 267 amdgpu_device_wb_free(adev, status_offset); 268 return r; 269 } 270 271 static int convert_to_mes_queue_type(int queue_type) 272 { 273 if (queue_type == AMDGPU_RING_TYPE_GFX) 274 return MES_QUEUE_TYPE_GFX; 275 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 276 return MES_QUEUE_TYPE_COMPUTE; 277 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 278 return MES_QUEUE_TYPE_SDMA; 279 else if (queue_type == AMDGPU_RING_TYPE_MES) 280 return MES_QUEUE_TYPE_SCHQ; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, 287 struct mes_add_queue_input *input) 288 { 289 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 290 int xcc_id = input->xcc_id; 291 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 292 293 if (mes->enable_coop_mode) 294 xcc_id = mes->master_xcc_ids[inst]; 295 296 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 297 298 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 299 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 300 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 301 302 mes_add_queue_pkt.process_id = input->process_id; 303 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 304 mes_add_queue_pkt.process_va_start = input->process_va_start; 305 mes_add_queue_pkt.process_va_end = input->process_va_end; 306 mes_add_queue_pkt.process_quantum = input->process_quantum; 307 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 308 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 309 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 310 mes_add_queue_pkt.inprocess_gang_priority = 311 input->inprocess_gang_priority; 312 mes_add_queue_pkt.gang_global_priority_level = 313 input->gang_global_priority_level; 314 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 315 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 316 317 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 318 319 mes_add_queue_pkt.queue_type = 320 convert_to_mes_queue_type(input->queue_type); 321 mes_add_queue_pkt.paging = input->paging; 322 mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl; 323 mes_add_queue_pkt.gws_base = input->gws_base; 324 mes_add_queue_pkt.gws_size = input->gws_size; 325 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 326 mes_add_queue_pkt.tma_addr = input->tma_addr; 327 mes_add_queue_pkt.trap_en = input->trap_en; 328 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 329 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 330 331 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 332 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 333 mes_add_queue_pkt.gds_size = input->queue_size; 334 335 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 336 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 337 mes_add_queue_pkt.gds_size = input->queue_size; 338 339 mes_add_queue_pkt.full_sh_mem_config_data = input->sh_mem_config_data; 340 341 return mes_v12_1_submit_pkt_and_poll_completion(mes, 342 xcc_id, AMDGPU_MES_SCHED_PIPE, 343 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 344 offsetof(union MESAPI__ADD_QUEUE, api_status)); 345 } 346 347 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, 348 struct mes_remove_queue_input *input) 349 { 350 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 351 int xcc_id = input->xcc_id; 352 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 353 354 if (mes->enable_coop_mode) 355 xcc_id = mes->master_xcc_ids[inst]; 356 357 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 358 359 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 360 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 361 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 362 363 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 364 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 365 mes_remove_queue_pkt.queue_type = 366 convert_to_mes_queue_type(input->queue_type); 367 368 return mes_v12_1_submit_pkt_and_poll_completion(mes, 369 xcc_id, AMDGPU_MES_SCHED_PIPE, 370 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 371 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 372 } 373 374 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, 375 struct mes_reset_queue_input *input) 376 { 377 union MESAPI__RESET mes_reset_queue_pkt; 378 int pipe; 379 380 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 381 382 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 383 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 384 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 385 386 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 387 /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ 388 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 389 390 if (mes->adev->enable_uni_mes) 391 pipe = AMDGPU_MES_KIQ_PIPE; 392 else 393 pipe = AMDGPU_MES_SCHED_PIPE; 394 395 return mes_v12_1_submit_pkt_and_poll_completion(mes, 396 input->xcc_id, pipe, 397 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 398 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 399 } 400 401 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, 402 struct mes_map_legacy_queue_input *input) 403 { 404 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 405 int pipe; 406 407 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 408 409 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 410 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 411 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 412 413 mes_add_queue_pkt.pipe_id = input->pipe_id; 414 mes_add_queue_pkt.queue_id = input->queue_id; 415 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 416 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 417 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 418 mes_add_queue_pkt.queue_type = 419 convert_to_mes_queue_type(input->queue_type); 420 mes_add_queue_pkt.map_legacy_kq = 1; 421 422 if (mes->adev->enable_uni_mes) { 423 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 424 if (input->queue_type == AMDGPU_RING_TYPE_MES) 425 pipe = AMDGPU_MES_KIQ_PIPE; 426 else 427 pipe = AMDGPU_MES_SCHED_PIPE; 428 } else { 429 pipe = AMDGPU_MES_SCHED_PIPE; 430 } 431 432 return mes_v12_1_submit_pkt_and_poll_completion(mes, 433 input->xcc_id, pipe, 434 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 435 offsetof(union MESAPI__ADD_QUEUE, api_status)); 436 } 437 438 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, 439 struct mes_unmap_legacy_queue_input *input) 440 { 441 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 442 int pipe; 443 444 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 445 446 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 447 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 448 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 449 450 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 451 mes_remove_queue_pkt.gang_context_addr = 0; 452 453 mes_remove_queue_pkt.pipe_id = input->pipe_id; 454 mes_remove_queue_pkt.queue_id = input->queue_id; 455 456 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 457 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 458 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 459 mes_remove_queue_pkt.tf_data = 460 lower_32_bits(input->trail_fence_data); 461 } else { 462 mes_remove_queue_pkt.unmap_legacy_queue = 1; 463 mes_remove_queue_pkt.queue_type = 464 convert_to_mes_queue_type(input->queue_type); 465 } 466 467 if (mes->adev->enable_uni_mes) { 468 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 469 if (input->queue_type == AMDGPU_RING_TYPE_MES) 470 pipe = AMDGPU_MES_KIQ_PIPE; 471 else 472 pipe = AMDGPU_MES_SCHED_PIPE; 473 } else { 474 pipe = AMDGPU_MES_SCHED_PIPE; 475 } 476 477 return mes_v12_1_submit_pkt_and_poll_completion(mes, 478 input->xcc_id, pipe, 479 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 480 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 481 } 482 483 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, 484 struct mes_suspend_gang_input *input) 485 { 486 union MESAPI__SUSPEND mes_suspend_gang_pkt; 487 488 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 489 490 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 491 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 492 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 493 494 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 495 mes_suspend_gang_pkt.suspend_all_sdma_gangs = input->suspend_all_sdma_gangs; 496 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 497 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 498 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 499 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 500 501 /* Suspend gang is handled by master MES */ 502 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, 503 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 504 offsetof(union MESAPI__SUSPEND, api_status)); 505 } 506 507 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, 508 struct mes_resume_gang_input *input) 509 { 510 union MESAPI__RESUME mes_resume_gang_pkt; 511 512 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 513 514 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 515 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 516 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 517 518 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 519 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 520 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 521 522 /* Resume gang is handled by master MES */ 523 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, 524 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 525 offsetof(union MESAPI__RESUME, api_status)); 526 } 527 528 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, 529 int pipe, int xcc_id) 530 { 531 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 532 533 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 534 535 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 536 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 537 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 538 539 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 540 &mes_status_pkt, sizeof(mes_status_pkt), 541 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 542 } 543 static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) 544 { 545 return ((reg_offset >> 16) & 0x7); 546 } 547 548 static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, 549 struct RRMT_OPTION *rrmt_opt, 550 uint32_t *out_reg) 551 { 552 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 553 554 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) { 555 rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg); 556 rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? 557 MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; 558 } else { 559 rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID; 560 if (soc_v1_0_mid1_reg_range(reg)) 561 rrmt_opt->mid_die_id = 1; 562 } 563 564 *out_reg = soc_v1_0_normalize_reg_offset(reg); 565 } 566 567 static int mes_v12_1_misc_op(struct amdgpu_mes *mes, 568 struct mes_misc_op_input *input) 569 { 570 struct amdgpu_device *adev = mes->adev; 571 union MESAPI__MISC misc_pkt; 572 int pipe; 573 574 if (mes->adev->enable_uni_mes) 575 pipe = AMDGPU_MES_KIQ_PIPE; 576 else 577 pipe = AMDGPU_MES_SCHED_PIPE; 578 579 memset(&misc_pkt, 0, sizeof(misc_pkt)); 580 581 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 582 misc_pkt.header.opcode = MES_SCH_API_MISC; 583 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 584 585 switch (input->op) { 586 case MES_MISC_OP_READ_REG: 587 misc_pkt.opcode = MESAPI_MISC__READ_REG; 588 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 589 mes_v12_1_get_rrmt(input->read_reg.reg_offset, 590 GET_INST(GC, input->xcc_id), 591 &misc_pkt.read_reg.rrmt_opt, 592 &misc_pkt.read_reg.reg_offset); 593 break; 594 case MES_MISC_OP_WRITE_REG: 595 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 596 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 597 mes_v12_1_get_rrmt(input->write_reg.reg_offset, 598 GET_INST(GC, input->xcc_id), 599 &misc_pkt.write_reg.rrmt_opt, 600 &misc_pkt.write_reg.reg_offset); 601 break; 602 case MES_MISC_OP_WRM_REG_WAIT: 603 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 604 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 605 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 606 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 607 misc_pkt.wait_reg_mem.reg_offset2 = 0; 608 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 609 GET_INST(GC, input->xcc_id), 610 &misc_pkt.wait_reg_mem.rrmt_opt1, 611 &misc_pkt.wait_reg_mem.reg_offset1); 612 break; 613 case MES_MISC_OP_WRM_REG_WR_WAIT: 614 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 615 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 616 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 617 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 618 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 619 GET_INST(GC, input->xcc_id), 620 &misc_pkt.wait_reg_mem.rrmt_opt1, 621 &misc_pkt.wait_reg_mem.reg_offset1); 622 mes_v12_1_get_rrmt(input->wrm_reg.reg1, 623 GET_INST(GC, input->xcc_id), 624 &misc_pkt.wait_reg_mem.rrmt_opt2, 625 &misc_pkt.wait_reg_mem.reg_offset2); 626 break; 627 case MES_MISC_OP_SET_SHADER_DEBUGGER: 628 pipe = AMDGPU_MES_SCHED_PIPE; 629 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 630 misc_pkt.set_shader_debugger.process_context_addr = 631 input->set_shader_debugger.process_context_addr; 632 misc_pkt.set_shader_debugger.flags.u32all = 633 input->set_shader_debugger.flags.u32all; 634 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 635 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 636 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 637 input->set_shader_debugger.tcp_watch_cntl, 638 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 639 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 640 break; 641 case MES_MISC_OP_CHANGE_CONFIG: 642 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 643 misc_pkt.change_config.opcode = 644 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 645 misc_pkt.change_config.option.bits.limit_single_process = 646 input->change_config.option.limit_single_process; 647 break; 648 default: 649 DRM_ERROR("unsupported misc op (%d) \n", input->op); 650 return -EINVAL; 651 } 652 653 return mes_v12_1_submit_pkt_and_poll_completion(mes, 654 input->xcc_id, pipe, 655 &misc_pkt, sizeof(misc_pkt), 656 offsetof(union MESAPI__MISC, api_status)); 657 } 658 659 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, 660 int pipe, int xcc_id) 661 { 662 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 663 int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); 664 665 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 666 667 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 668 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 669 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 670 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 671 672 /* From version 0x74 above, pipe1 support use shared command buffer 673 to distribute some tasks on individual XCCs*/ 674 if (mes->enable_coop_mode && 675 ((pipe == AMDGPU_MES_SCHED_PIPE) || 676 ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) { 677 master_xcc_id = mes->master_xcc_ids[inst]; 678 mes_set_hw_res_1_pkt.mes_coop_mode = 1; 679 mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = 680 mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe]; 681 } 682 683 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 684 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 685 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 686 } 687 688 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, 689 int pipe, int xcc_id) 690 { 691 int i, status; 692 struct amdgpu_device *adev = mes->adev; 693 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 694 695 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 696 697 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 698 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 699 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 700 701 if (pipe == AMDGPU_MES_SCHED_PIPE) { 702 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 703 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 704 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 705 mes_set_hw_res_pkt.paging_vmid = 0; 706 707 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 708 mes_set_hw_res_pkt.compute_hqd_mask[i] = 709 mes->compute_hqd_mask[i]; 710 711 for (i = 0; i < MAX_GFX_PIPES; i++) 712 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 713 mes->gfx_hqd_mask[i]; 714 715 for (i = 0; i < MAX_SDMA_PIPES; i++) 716 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 717 mes->sdma_hqd_mask[i]; 718 719 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 720 mes_set_hw_res_pkt.aggregated_doorbells[i] = 721 mes->aggregated_doorbells[i]; 722 } 723 724 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 725 mes->sch_ctx_gpu_addr[pipe]; 726 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 727 mes->query_status_fence_gpu_addr[pipe]; 728 729 for (i = 0; i < 5; i++) { 730 mes_set_hw_res_pkt.gc_base[i] = 731 adev->reg_offset[GC_HWIP][0][i]; 732 mes_set_hw_res_pkt.mmhub_base[i] = 733 adev->reg_offset[MMHUB_HWIP][0][i]; 734 mes_set_hw_res_pkt.osssys_base[i] = 735 adev->reg_offset[OSSSYS_HWIP][0][i]; 736 } 737 738 mes_set_hw_res_pkt.disable_reset = 1; 739 mes_set_hw_res_pkt.disable_mes_log = 1; 740 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 741 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 742 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 743 744 /* 745 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 746 * handling support, other queue will not use the oversubscribe timer. 747 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 748 */ 749 mes_set_hw_res_pkt.oversubscription_timer = 50; 750 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 751 752 if (amdgpu_mes_log_enable) { 753 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 754 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 755 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE; 756 } 757 758 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 759 mes_set_hw_res_pkt.limit_single_process = 1; 760 761 status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 762 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 763 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 764 765 /* get MES scheduler versions */ 766 mutex_lock(&adev->srbm_mutex); 767 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 768 769 if (pipe == AMDGPU_MES_SCHED_PIPE) 770 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 771 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 772 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 773 774 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 775 mutex_unlock(&adev->srbm_mutex); 776 777 return status; 778 } 779 780 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, 781 int xcc_id) 782 { 783 struct amdgpu_device *adev = mes->adev; 784 uint32_t data; 785 786 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1); 787 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 788 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 789 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 790 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 791 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 792 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 793 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data); 794 795 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2); 796 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 797 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 798 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 799 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 800 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 801 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 802 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data); 803 804 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3); 805 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 806 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 807 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 808 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 809 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 810 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 811 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data); 812 813 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4); 814 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 815 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 816 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 817 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 818 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 819 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 820 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data); 821 822 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5); 823 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 824 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 825 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 826 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 827 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 828 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 829 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data); 830 831 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 832 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data); 833 } 834 835 836 static void mes_v12_1_enable_unmapped_doorbell_handling( 837 struct amdgpu_mes *mes, bool enable, int xcc_id) 838 { 839 struct amdgpu_device *adev = mes->adev; 840 uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL); 841 842 /* 843 * The default PROC_LSB settng is 0xc which means doorbell 844 * addr[16:12] gives the doorbell page number. For kfd, each 845 * process will use 2 pages of doorbell, we need to change the 846 * setting to 0xd 847 */ 848 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 849 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 850 851 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 852 853 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data); 854 } 855 856 #if 0 857 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, 858 struct mes_reset_legacy_queue_input *input) 859 { 860 union MESAPI__RESET mes_reset_queue_pkt; 861 int pipe; 862 863 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 864 865 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 866 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 867 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 868 869 mes_reset_queue_pkt.queue_type = 870 convert_to_mes_queue_type(input->queue_type); 871 872 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 873 mes_reset_queue_pkt.reset_legacy_gfx = 1; 874 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 875 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 876 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 877 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 878 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 879 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 880 } else { 881 mes_reset_queue_pkt.reset_queue_only = 1; 882 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 883 } 884 885 if (mes->adev->enable_uni_mes) 886 pipe = AMDGPU_MES_KIQ_PIPE; 887 else 888 pipe = AMDGPU_MES_SCHED_PIPE; 889 890 return mes_v12_1_submit_pkt_and_poll_completion(mes, 891 input->xcc_id, pipe, 892 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 893 offsetof(union MESAPI__RESET, api_status)); 894 } 895 #endif 896 897 static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 898 struct mes_detect_and_reset_queue_input *input) 899 { 900 union MESAPI__RESET mes_reset_queue_pkt; 901 902 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 903 904 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 905 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 906 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 907 908 mes_reset_queue_pkt.queue_type = 909 convert_to_mes_queue_type(input->queue_type); 910 mes_reset_queue_pkt.doorbell_offset_addr = 911 mes->hung_queue_db_array_gpu_addr[0]; 912 913 if (input->detect_only) 914 mes_reset_queue_pkt.hang_detect_only = 1; 915 else 916 mes_reset_queue_pkt.hang_detect_then_reset = 1; 917 918 return mes_v12_1_submit_pkt_and_poll_completion(mes, 919 input->xcc_id, AMDGPU_MES_SCHED_PIPE, 920 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 921 offsetof(union MESAPI__RESET, api_status)); 922 } 923 924 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 925 { 926 /* 927 * MES doesn't support invalidate gc_hub on slave xcc individually 928 * master xcc will invalidate all gc_hub for the partition 929 */ 930 if (AMDGPU_IS_GFXHUB(id)) 931 return 0; 932 else if (AMDGPU_IS_MMHUB0(id)) 933 return 1; 934 else if (AMDGPU_IS_MMHUB1(id)) 935 return 2; 936 return -EINVAL; 937 938 } 939 940 static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes, 941 struct mes_inv_tlbs_pasid_input *input) 942 { 943 union MESAPI__INV_TLBS mes_inv_tlbs; 944 int xcc_id = input->xcc_id; 945 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 946 int ret; 947 948 if (mes->enable_coop_mode) 949 xcc_id = mes->master_xcc_ids[inst]; 950 951 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 952 953 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 954 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 955 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 956 957 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 958 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 959 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 960 961 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 962 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 963 if (ret < 0) 964 return -EINVAL; 965 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 966 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE, 967 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 968 offsetof(union MESAPI__INV_TLBS, api_status)); 969 970 } 971 972 static const struct amdgpu_mes_funcs mes_v12_1_funcs = { 973 .add_hw_queue = mes_v12_1_add_hw_queue, 974 .remove_hw_queue = mes_v12_1_remove_hw_queue, 975 .map_legacy_queue = mes_v12_1_map_legacy_queue, 976 .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue, 977 .suspend_gang = mes_v12_1_suspend_gang, 978 .resume_gang = mes_v12_1_resume_gang, 979 .misc_op = mes_v12_1_misc_op, 980 .reset_hw_queue = mes_v12_1_reset_hw_queue, 981 .detect_and_reset_hung_queues = mes_v12_1_detect_and_reset_hung_queues, 982 .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, 983 }; 984 985 static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev, 986 enum amdgpu_mes_pipe pipe, 987 int xcc_id) 988 { 989 int r, inst = MES_PIPE_INST(xcc_id, pipe); 990 const struct mes_firmware_header_v1_0 *mes_hdr; 991 const __le32 *fw_data; 992 unsigned fw_size; 993 994 mes_hdr = (const struct mes_firmware_header_v1_0 *) 995 adev->mes.fw[pipe]->data; 996 997 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 998 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 999 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1000 1001 r = amdgpu_bo_create_reserved(adev, fw_size, 1002 PAGE_SIZE, 1003 AMDGPU_GEM_DOMAIN_VRAM, 1004 &adev->mes.ucode_fw_obj[inst], 1005 &adev->mes.ucode_fw_gpu_addr[inst], 1006 (void **)&adev->mes.ucode_fw_ptr[inst]); 1007 if (r) { 1008 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1009 return r; 1010 } 1011 1012 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size); 1013 1014 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]); 1015 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]); 1016 1017 return 0; 1018 } 1019 1020 static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1021 enum amdgpu_mes_pipe pipe, 1022 int xcc_id) 1023 { 1024 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1025 const struct mes_firmware_header_v1_0 *mes_hdr; 1026 const __le32 *fw_data; 1027 unsigned fw_size; 1028 1029 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1030 adev->mes.fw[pipe]->data; 1031 1032 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1033 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1034 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1035 1036 r = amdgpu_bo_create_reserved(adev, fw_size, 1037 64 * 1024, 1038 AMDGPU_GEM_DOMAIN_VRAM, 1039 &adev->mes.data_fw_obj[inst], 1040 &adev->mes.data_fw_gpu_addr[inst], 1041 (void **)&adev->mes.data_fw_ptr[inst]); 1042 if (r) { 1043 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1044 return r; 1045 } 1046 1047 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size); 1048 1049 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]); 1050 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]); 1051 1052 return 0; 1053 } 1054 1055 static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev, 1056 enum amdgpu_mes_pipe pipe, 1057 int xcc_id) 1058 { 1059 int inst = MES_PIPE_INST(xcc_id, pipe); 1060 1061 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst], 1062 &adev->mes.data_fw_gpu_addr[inst], 1063 (void **)&adev->mes.data_fw_ptr[inst]); 1064 1065 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst], 1066 &adev->mes.ucode_fw_gpu_addr[inst], 1067 (void **)&adev->mes.ucode_fw_ptr[inst]); 1068 } 1069 1070 static void mes_v12_1_enable(struct amdgpu_device *adev, 1071 bool enable, int xcc_id) 1072 { 1073 uint64_t ucode_addr; 1074 uint32_t pipe, data = 0; 1075 1076 if (enable) { 1077 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1078 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1079 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1080 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1081 1082 mutex_lock(&adev->srbm_mutex); 1083 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1084 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, 1085 GET_INST(GC, xcc_id)); 1086 1087 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1088 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1089 regCP_MES_PRGRM_CNTR_START, 1090 lower_32_bits(ucode_addr)); 1091 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1092 regCP_MES_PRGRM_CNTR_START_HI, 1093 upper_32_bits(ucode_addr)); 1094 } 1095 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1096 mutex_unlock(&adev->srbm_mutex); 1097 1098 /* unhalt MES and activate pipe0 */ 1099 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1100 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1101 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1102 1103 if (amdgpu_emu_mode) 1104 msleep(500); 1105 else if (adev->enable_uni_mes) 1106 udelay(500); 1107 else 1108 udelay(50); 1109 } else { 1110 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1111 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1112 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1113 data = REG_SET_FIELD(data, CP_MES_CNTL, 1114 MES_INVALIDATE_ICACHE, 1); 1115 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1116 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1117 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1118 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1119 } 1120 } 1121 1122 static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev, 1123 int xcc_id) 1124 { 1125 uint64_t ucode_addr; 1126 int pipe; 1127 1128 mes_v12_1_enable(adev, false, xcc_id); 1129 1130 mutex_lock(&adev->srbm_mutex); 1131 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1132 /* me=3, queue=0 */ 1133 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1134 1135 /* set ucode start address */ 1136 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1137 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START, 1138 lower_32_bits(ucode_addr)); 1139 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI, 1140 upper_32_bits(ucode_addr)); 1141 1142 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1143 } 1144 mutex_unlock(&adev->srbm_mutex); 1145 } 1146 1147 /* This function is for backdoor MES firmware */ 1148 static int mes_v12_1_load_microcode(struct amdgpu_device *adev, 1149 enum amdgpu_mes_pipe pipe, 1150 bool prime_icache, int xcc_id) 1151 { 1152 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1153 uint32_t data; 1154 1155 mes_v12_1_enable(adev, false, xcc_id); 1156 1157 if (!adev->mes.fw[pipe]) 1158 return -EINVAL; 1159 1160 r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id); 1161 if (r) 1162 return r; 1163 1164 r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id); 1165 if (r) { 1166 mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id); 1167 return r; 1168 } 1169 1170 mutex_lock(&adev->srbm_mutex); 1171 /* me=3, pipe=0, queue=0 */ 1172 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1173 1174 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0); 1175 1176 /* set ucode fimrware address */ 1177 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO, 1178 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1179 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI, 1180 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1181 1182 /* set ucode instruction cache boundary to 2M-1 */ 1183 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF); 1184 1185 /* set ucode data firmware address */ 1186 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO, 1187 lower_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1188 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI, 1189 upper_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1190 1191 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1192 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF); 1193 1194 if (prime_icache) { 1195 /* invalidate ICACHE */ 1196 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1197 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1198 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1199 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1200 1201 /* prime the ICACHE. */ 1202 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1203 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1204 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1205 } 1206 1207 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1208 mutex_unlock(&adev->srbm_mutex); 1209 1210 return 0; 1211 } 1212 1213 static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev, 1214 enum amdgpu_mes_pipe pipe, 1215 int xcc_id) 1216 { 1217 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1218 u32 *eop; 1219 1220 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1221 AMDGPU_GEM_DOMAIN_GTT, 1222 &adev->mes.eop_gpu_obj[inst], 1223 &adev->mes.eop_gpu_addr[inst], 1224 (void **)&eop); 1225 if (r) { 1226 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1227 return r; 1228 } 1229 1230 memset(eop, 0, 1231 adev->mes.eop_gpu_obj[inst]->tbo.base.size); 1232 1233 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]); 1234 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]); 1235 1236 return 0; 1237 } 1238 1239 static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, 1240 enum amdgpu_mes_pipe pipe, 1241 int xcc_id) 1242 { 1243 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1244 1245 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1246 AMDGPU_GEM_DOMAIN_VRAM, 1247 &adev->mes.shared_cmd_buf_obj[inst], 1248 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1249 NULL); 1250 if (r) { 1251 dev_err(adev->dev, 1252 "(%d) failed to create shared cmd buf bo\n", r); 1253 return r; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) 1260 { 1261 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1262 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1263 uint32_t tmp; 1264 1265 mqd->header = 0xC0310800; 1266 mqd->compute_pipelinestat_enable = 0x00000001; 1267 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1268 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1269 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1270 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1271 mqd->compute_misc_reserved = 0x00000007; 1272 1273 eop_base_addr = ring->eop_gpu_addr >> 8; 1274 1275 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1276 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1277 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1278 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1279 1280 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1281 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1282 mqd->cp_hqd_eop_control = tmp; 1283 1284 /* disable the queue if it's active */ 1285 ring->wptr = 0; 1286 mqd->cp_hqd_pq_rptr = 0; 1287 mqd->cp_hqd_pq_wptr_lo = 0; 1288 mqd->cp_hqd_pq_wptr_hi = 0; 1289 1290 /* set the pointer to the MQD */ 1291 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1292 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1293 1294 /* set MQD vmid to 0 */ 1295 tmp = regCP_MQD_CONTROL_DEFAULT; 1296 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1297 mqd->cp_mqd_control = tmp; 1298 1299 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1300 hqd_gpu_addr = ring->gpu_addr >> 8; 1301 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1302 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1303 1304 /* set the wb address whether it's enabled or not */ 1305 wb_gpu_addr = ring->rptr_gpu_addr; 1306 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1307 mqd->cp_hqd_pq_rptr_report_addr_hi = 1308 upper_32_bits(wb_gpu_addr) & 0xffff; 1309 1310 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1311 wb_gpu_addr = ring->wptr_gpu_addr; 1312 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1313 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1314 1315 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1316 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1317 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1318 (order_base_2(ring->ring_size / 4) - 1)); 1319 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1320 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1323 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1324 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1325 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1326 mqd->cp_hqd_pq_control = tmp; 1327 1328 /* enable doorbell */ 1329 tmp = 0; 1330 if (ring->use_doorbell) { 1331 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1332 DOORBELL_OFFSET, ring->doorbell_index); 1333 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1334 DOORBELL_EN, 1); 1335 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1336 DOORBELL_SOURCE, 0); 1337 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1338 DOORBELL_HIT, 0); 1339 } else { 1340 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1341 DOORBELL_EN, 0); 1342 } 1343 mqd->cp_hqd_pq_doorbell_control = tmp; 1344 1345 mqd->cp_hqd_vmid = 0; 1346 /* activate the queue */ 1347 mqd->cp_hqd_active = 1; 1348 1349 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1350 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1351 PRELOAD_SIZE, 0x63); 1352 mqd->cp_hqd_persistent_state = tmp; 1353 1354 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT; 1355 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1356 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1357 1358 /* 1359 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1360 * doorbell handling. This is a reserved CP internal register can 1361 * not be accesss by others 1362 */ 1363 mqd->cp_hqd_gfx_control = BIT(15); 1364 1365 return 0; 1366 } 1367 1368 static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring, 1369 int xcc_id) 1370 { 1371 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1372 struct amdgpu_device *adev = ring->adev; 1373 uint32_t data = 0; 1374 1375 mutex_lock(&adev->srbm_mutex); 1376 soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id)); 1377 1378 /* set CP_HQD_VMID.VMID = 0. */ 1379 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID); 1380 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1381 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data); 1382 1383 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1384 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1385 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1386 DOORBELL_EN, 0); 1387 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1388 1389 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1390 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1391 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1392 1393 /* set CP_MQD_CONTROL.VMID=0 */ 1394 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1395 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1396 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0); 1397 1398 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1399 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1400 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1401 1402 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1403 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1404 mqd->cp_hqd_pq_rptr_report_addr_lo); 1405 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1406 mqd->cp_hqd_pq_rptr_report_addr_hi); 1407 1408 /* set CP_HQD_PQ_CONTROL */ 1409 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1410 1411 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1412 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1413 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1414 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1415 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1416 1417 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1419 mqd->cp_hqd_pq_doorbell_control); 1420 1421 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1422 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1423 1424 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1425 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1426 1427 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1428 mutex_unlock(&adev->srbm_mutex); 1429 } 1430 1431 static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id) 1432 { 1433 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 1434 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; 1435 int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1436 1437 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1438 return -EINVAL; 1439 1440 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1441 if (r) { 1442 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1443 return r; 1444 } 1445 1446 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); 1447 1448 r = amdgpu_ring_test_ring(kiq_ring); 1449 if (r) { 1450 DRM_ERROR("kfq enable failed\n"); 1451 kiq_ring->sched.ready = false; 1452 } 1453 return r; 1454 } 1455 1456 static int mes_v12_1_queue_init(struct amdgpu_device *adev, 1457 enum amdgpu_mes_pipe pipe, 1458 int xcc_id) 1459 { 1460 struct amdgpu_ring *ring; 1461 int r; 1462 1463 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1464 ring = &adev->gfx.kiq[xcc_id].ring; 1465 else 1466 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)]; 1467 1468 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1469 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1470 *(ring->wptr_cpu_addr) = 0; 1471 *(ring->rptr_cpu_addr) = 0; 1472 amdgpu_ring_clear_ring(ring); 1473 } 1474 1475 r = mes_v12_1_mqd_init(ring); 1476 if (r) 1477 return r; 1478 1479 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1480 if (adev->enable_uni_mes) 1481 r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id); 1482 else 1483 r = mes_v12_1_kiq_enable_queue(adev, xcc_id); 1484 if (r) 1485 return r; 1486 } else { 1487 mes_v12_1_queue_init_register(ring, xcc_id); 1488 } 1489 1490 return 0; 1491 } 1492 1493 static int mes_v12_1_ring_init(struct amdgpu_device *adev, 1494 int xcc_id, int pipe) 1495 { 1496 struct amdgpu_ring *ring; 1497 int inst = MES_PIPE_INST(xcc_id, pipe); 1498 1499 ring = &adev->mes.ring[inst]; 1500 1501 ring->funcs = &mes_v12_1_ring_funcs; 1502 1503 ring->me = 3; 1504 ring->pipe = pipe; 1505 ring->queue = 0; 1506 ring->xcc_id = xcc_id; 1507 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1508 1509 ring->ring_obj = NULL; 1510 ring->use_doorbell = true; 1511 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1512 ring->no_scheduler = true; 1513 snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu", 1514 (unsigned char)xcc_id, (unsigned char)ring->me, 1515 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1516 1517 if (pipe == AMDGPU_MES_SCHED_PIPE) 1518 ring->doorbell_index = 1519 (adev->doorbell_index.mes_ring0 + 1520 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1521 << 1; 1522 else 1523 ring->doorbell_index = 1524 (adev->doorbell_index.mes_ring1 + 1525 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1526 << 1; 1527 1528 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1529 AMDGPU_RING_PRIO_DEFAULT, NULL); 1530 } 1531 1532 static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id) 1533 { 1534 struct amdgpu_ring *ring; 1535 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1536 1537 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); 1538 1539 ring = &adev->gfx.kiq[xcc_id].ring; 1540 1541 ring->me = 3; 1542 ring->pipe = 1; 1543 ring->queue = 0; 1544 ring->xcc_id = xcc_id; 1545 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1546 1547 ring->adev = NULL; 1548 ring->ring_obj = NULL; 1549 ring->use_doorbell = true; 1550 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1551 ring->no_scheduler = true; 1552 ring->doorbell_index = 1553 (adev->doorbell_index.mes_ring1 + 1554 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1555 << 1; 1556 1557 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu", 1558 (unsigned char)xcc_id, (unsigned char)ring->me, 1559 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1560 1561 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1562 AMDGPU_RING_PRIO_DEFAULT, NULL); 1563 } 1564 1565 static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev, 1566 enum amdgpu_mes_pipe pipe, 1567 int xcc_id) 1568 { 1569 int r, mqd_size = sizeof(struct v12_1_mes_mqd); 1570 struct amdgpu_ring *ring; 1571 int inst = MES_PIPE_INST(xcc_id, pipe); 1572 1573 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1574 ring = &adev->gfx.kiq[xcc_id].ring; 1575 else 1576 ring = &adev->mes.ring[inst]; 1577 1578 if (ring->mqd_obj) 1579 return 0; 1580 1581 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1582 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1583 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1584 if (r) { 1585 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1586 return r; 1587 } 1588 1589 memset(ring->mqd_ptr, 0, mqd_size); 1590 1591 /* prepare MQD backup */ 1592 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL); 1593 if (!adev->mes.mqd_backup[inst]) 1594 dev_warn(adev->dev, 1595 "no memory to create MQD backup for ring %s\n", 1596 ring->name); 1597 1598 return 0; 1599 } 1600 1601 static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1602 { 1603 struct amdgpu_device *adev = ip_block->adev; 1604 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1605 1606 adev->mes.funcs = &mes_v12_1_funcs; 1607 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; 1608 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; 1609 adev->mes.enable_legacy_queue_map = true; 1610 1611 adev->mes.event_log_size = 1612 adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE; 1613 1614 r = amdgpu_mes_init(adev); 1615 if (r) 1616 return r; 1617 1618 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1619 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1620 r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id); 1621 if (r) 1622 return r; 1623 1624 r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id); 1625 if (r) 1626 return r; 1627 1628 if (!adev->enable_uni_mes && pipe == 1629 AMDGPU_MES_KIQ_PIPE) 1630 r = mes_v12_1_kiq_ring_init(adev, xcc_id); 1631 else 1632 r = mes_v12_1_ring_init(adev, xcc_id, pipe); 1633 if (r) 1634 return r; 1635 1636 if (adev->enable_uni_mes && num_xcc > 1) { 1637 r = mes_v12_1_allocate_shared_cmd_buf(adev, 1638 pipe, xcc_id); 1639 if (r) 1640 return r; 1641 } 1642 } 1643 } 1644 1645 return 0; 1646 } 1647 1648 static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1649 { 1650 struct amdgpu_device *adev = ip_block->adev; 1651 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1652 1653 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1654 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1655 inst = MES_PIPE_INST(xcc_id, pipe); 1656 1657 amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst], 1658 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1659 NULL); 1660 1661 kfree(adev->mes.mqd_backup[inst]); 1662 1663 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], 1664 &adev->mes.eop_gpu_addr[inst], 1665 NULL); 1666 1667 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1668 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, 1669 &adev->mes.ring[inst].mqd_gpu_addr, 1670 &adev->mes.ring[inst].mqd_ptr); 1671 amdgpu_ring_fini(&adev->mes.ring[inst]); 1672 } 1673 } 1674 } 1675 1676 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) 1677 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1678 1679 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1680 if (!adev->enable_uni_mes) { 1681 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, 1682 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, 1683 &adev->gfx.kiq[xcc_id].ring.mqd_ptr); 1684 amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring); 1685 } 1686 1687 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1688 mes_v12_1_free_ucode_buffers(adev, 1689 AMDGPU_MES_KIQ_PIPE, xcc_id); 1690 mes_v12_1_free_ucode_buffers(adev, 1691 AMDGPU_MES_SCHED_PIPE, xcc_id); 1692 } 1693 } 1694 1695 amdgpu_mes_fini(adev); 1696 return 0; 1697 } 1698 1699 static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev, 1700 int xcc_id) 1701 { 1702 uint32_t data; 1703 int i; 1704 1705 mutex_lock(&adev->srbm_mutex); 1706 soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0, 1707 GET_INST(GC, xcc_id)); 1708 1709 /* disable the queue if it's active */ 1710 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1711 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1712 for (i = 0; i < adev->usec_timeout; i++) { 1713 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1714 break; 1715 udelay(1); 1716 } 1717 } 1718 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1719 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1720 DOORBELL_EN, 0); 1721 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1722 DOORBELL_HIT, 1); 1723 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1724 1725 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1726 1727 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1728 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1729 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1730 1731 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1732 mutex_unlock(&adev->srbm_mutex); 1733 1734 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false; 1735 } 1736 1737 static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1738 { 1739 uint32_t tmp; 1740 struct amdgpu_device *adev = ring->adev; 1741 1742 /* tell RLC which is KIQ queue */ 1743 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1744 tmp &= 0xffffff00; 1745 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1746 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1747 tmp |= 0x80; 1748 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1749 } 1750 1751 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1752 { 1753 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1754 int r = 0; 1755 struct amdgpu_ip_block *ip_block; 1756 1757 if (adev->enable_uni_mes) 1758 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id); 1759 else 1760 mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id); 1761 1762 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1763 1764 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, 1765 false, xcc_id); 1766 if (r) { 1767 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1768 return r; 1769 } 1770 1771 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, 1772 true, xcc_id); 1773 if (r) { 1774 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1775 return r; 1776 } 1777 1778 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1779 1780 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1781 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1782 1783 mes_v12_1_enable(adev, true, xcc_id); 1784 1785 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1786 if (unlikely(!ip_block)) { 1787 dev_err(adev->dev, "Failed to get MES handle\n"); 1788 return -EINVAL; 1789 } 1790 1791 r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id); 1792 if (r) 1793 goto failure; 1794 1795 if (adev->enable_uni_mes) { 1796 r = mes_v12_1_setup_coop_mode(adev, xcc_id); 1797 if (r) 1798 goto failure; 1799 1800 r = mes_v12_1_set_hw_resources(&adev->mes, 1801 AMDGPU_MES_KIQ_PIPE, xcc_id); 1802 if (r) 1803 goto failure; 1804 1805 mes_v12_1_set_hw_resources_1(&adev->mes, 1806 AMDGPU_MES_KIQ_PIPE, xcc_id); 1807 } 1808 1809 if (adev->mes.enable_legacy_queue_map) { 1810 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1811 if (r) 1812 goto failure; 1813 } 1814 1815 return r; 1816 1817 failure: 1818 mes_v12_1_hw_fini(ip_block); 1819 return r; 1820 } 1821 1822 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1823 { 1824 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1825 1826 if (adev->mes.ring[inst].sched.ready) { 1827 if (adev->enable_uni_mes) 1828 amdgpu_mes_unmap_legacy_queue(adev, 1829 &adev->mes.ring[inst], 1830 RESET_QUEUES, 0, 0, xcc_id); 1831 else 1832 mes_v12_1_kiq_dequeue_sched(adev, xcc_id); 1833 1834 adev->mes.ring[inst].sched.ready = false; 1835 } 1836 1837 mes_v12_1_enable(adev, false, xcc_id); 1838 1839 return 0; 1840 } 1841 1842 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id) 1843 { 1844 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1845 int r = 0; 1846 1847 if (num_xcc == 1) 1848 return r; 1849 1850 if (adev->gfx.funcs && 1851 adev->gfx.funcs->get_xccs_per_xcp) 1852 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 1853 else 1854 return -EINVAL; 1855 1856 switch (adev->xcp_mgr->mode) { 1857 case AMDGPU_SPX_PARTITION_MODE: 1858 adev->mes.enable_coop_mode = 1; 1859 adev->mes.master_xcc_ids[xcc_id] = 0; 1860 break; 1861 case AMDGPU_DPX_PARTITION_MODE: 1862 adev->mes.enable_coop_mode = 1; 1863 adev->mes.master_xcc_ids[xcc_id] = 1864 (xcc_id/num_xcc_per_xcp) * (num_xcc / 2); 1865 break; 1866 case AMDGPU_QPX_PARTITION_MODE: 1867 adev->mes.enable_coop_mode = 1; 1868 adev->mes.master_xcc_ids[xcc_id] = 1869 (xcc_id/num_xcc_per_xcp) * (num_xcc / 4); 1870 break; 1871 case AMDGPU_CPX_PARTITION_MODE: 1872 adev->mes.enable_coop_mode = 0; 1873 break; 1874 default: 1875 r = -EINVAL; 1876 break; 1877 } 1878 return r; 1879 } 1880 1881 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) 1882 { 1883 int r; 1884 struct amdgpu_device *adev = ip_block->adev; 1885 1886 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready) 1887 goto out; 1888 1889 if (!adev->enable_mes_kiq) { 1890 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1891 r = mes_v12_1_load_microcode(adev, 1892 AMDGPU_MES_SCHED_PIPE, true, xcc_id); 1893 if (r) { 1894 DRM_ERROR("failed to MES fw, r=%d\n", r); 1895 return r; 1896 } 1897 1898 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1899 1900 } else if (adev->firmware.load_type == 1901 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1902 1903 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1904 } 1905 1906 mes_v12_1_enable(adev, true, xcc_id); 1907 } 1908 1909 /* Enable the MES to handle doorbell ring on unmapped queue */ 1910 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id); 1911 1912 r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id); 1913 if (r) 1914 goto failure; 1915 1916 r = mes_v12_1_set_hw_resources(&adev->mes, 1917 AMDGPU_MES_SCHED_PIPE, xcc_id); 1918 if (r) 1919 goto failure; 1920 1921 if (adev->enable_uni_mes) { 1922 mes_v12_1_set_hw_resources_1(&adev->mes, 1923 AMDGPU_MES_SCHED_PIPE, xcc_id); 1924 } 1925 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); 1926 1927 r = mes_v12_1_query_sched_status(&adev->mes, 1928 AMDGPU_MES_SCHED_PIPE, xcc_id); 1929 if (r) { 1930 DRM_ERROR("MES is busy\n"); 1931 goto failure; 1932 } 1933 1934 amdgpu_mes_validate_fw_version(adev); 1935 out: 1936 /* 1937 * Disable KIQ ring usage from the driver once MES is enabled. 1938 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1939 * with MES enabled. 1940 */ 1941 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1942 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true; 1943 1944 return 0; 1945 1946 failure: 1947 mes_v12_1_hw_fini(ip_block); 1948 return r; 1949 } 1950 1951 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 1952 { 1953 struct amdgpu_device *adev = ip_block->adev; 1954 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1955 1956 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1957 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1958 if (r) 1959 return r; 1960 } 1961 1962 return 0; 1963 } 1964 1965 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 1966 { 1967 return 0; 1968 } 1969 1970 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) 1971 { 1972 return mes_v12_1_hw_fini(ip_block); 1973 } 1974 1975 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) 1976 { 1977 return mes_v12_1_hw_init(ip_block); 1978 } 1979 1980 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) 1981 { 1982 struct amdgpu_device *adev = ip_block->adev; 1983 int pipe, r; 1984 1985 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1986 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 1987 1988 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1989 r = amdgpu_mes_init_microcode(adev, pipe); 1990 if (r) 1991 return r; 1992 } 1993 1994 return 0; 1995 } 1996 1997 static int mes_v12_1_late_init(struct amdgpu_ip_block *ip_block) 1998 { 1999 struct amdgpu_device *adev = ip_block->adev; 2000 int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2001 2002 /* TODO: remove it if issue fixed. */ 2003 if (adev->mes.enable_coop_mode) 2004 return 0; 2005 2006 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 2007 /* for COOP mode, only test master xcc. */ 2008 if (adev->mes.enable_coop_mode && 2009 adev->mes.master_xcc_ids[xcc_id] != xcc_id) 2010 continue; 2011 2012 mes_v12_1_self_test(adev, xcc_id); 2013 } 2014 2015 return 0; 2016 } 2017 2018 static const struct amd_ip_funcs mes_v12_1_ip_funcs = { 2019 .name = "mes_v12_1", 2020 .early_init = mes_v12_1_early_init, 2021 .late_init = mes_v12_1_late_init, 2022 .sw_init = mes_v12_1_sw_init, 2023 .sw_fini = mes_v12_1_sw_fini, 2024 .hw_init = mes_v12_1_hw_init, 2025 .hw_fini = mes_v12_1_hw_fini, 2026 .suspend = mes_v12_1_suspend, 2027 .resume = mes_v12_1_resume, 2028 }; 2029 2030 const struct amdgpu_ip_block_version mes_v12_1_ip_block = { 2031 .type = AMD_IP_BLOCK_TYPE_MES, 2032 .major = 12, 2033 .minor = 1, 2034 .rev = 0, 2035 .funcs = &mes_v12_1_ip_funcs, 2036 }; 2037 2038 static int mes_v12_1_alloc_test_buf(struct amdgpu_device *adev, 2039 struct amdgpu_bo **bo, uint64_t *addr, 2040 void **ptr, int size) 2041 { 2042 amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2043 bo, addr, ptr); 2044 if (!*bo) { 2045 dev_err(adev->dev, "failed to allocate test buffer bo\n"); 2046 return -ENOMEM; 2047 } 2048 memset(*ptr, 0, size); 2049 return 0; 2050 } 2051 2052 static int mes_v12_1_map_test_bo(struct amdgpu_device *adev, 2053 struct amdgpu_bo *bo, struct amdgpu_vm *vm, 2054 struct amdgpu_bo_va **bo_va, u64 va, int size) 2055 { 2056 struct amdgpu_sync sync; 2057 int r; 2058 2059 r = amdgpu_map_static_csa(adev, vm, bo, bo_va, va, size); 2060 if (r) 2061 return r; 2062 2063 amdgpu_sync_create(&sync); 2064 2065 r = amdgpu_vm_bo_update(adev, *bo_va, false); 2066 if (r) { 2067 dev_err(adev->dev, "failed to do vm_bo_update on meta data\n"); 2068 goto error; 2069 } 2070 amdgpu_sync_fence(&sync, (*bo_va)->last_pt_update, GFP_KERNEL); 2071 2072 r = amdgpu_vm_update_pdes(adev, vm, false); 2073 if (r) { 2074 dev_err(adev->dev, "failed to update pdes on meta data\n"); 2075 goto error; 2076 } 2077 amdgpu_sync_fence(&sync, vm->last_update, GFP_KERNEL); 2078 amdgpu_sync_wait(&sync, false); 2079 2080 error: 2081 amdgpu_sync_free(&sync); 2082 return r; 2083 } 2084 2085 static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id, 2086 u32 *queue_ptr, u64 fence_gpu_addr, 2087 void *fence_cpu_ptr, void *wptr_cpu_addr, 2088 u64 doorbell_idx, int queue_type) 2089 { 2090 volatile uint32_t *cpu_ptr = fence_cpu_ptr; 2091 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2092 int sdma_ring_align = 0x10, compute_ring_align = 0x100; 2093 uint32_t tmp, xcc_offset; 2094 int r = 0, i, j, wptr = 0; 2095 2096 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 2097 if (!adev->mes.enable_coop_mode) { 2098 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2099 regSCRATCH_REG0, 0xCAFEDEAD); 2100 } else { 2101 for (i = 0; i < num_xcc; i++) { 2102 if (adev->mes.master_xcc_ids[i] == xcc_id) 2103 WREG32_SOC15(GC, GET_INST(GC, i), 2104 regSCRATCH_REG0, 0xCAFEDEAD); 2105 } 2106 } 2107 2108 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 2109 queue_ptr[wptr++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2110 queue_ptr[wptr++] = xcc_offset - PACKET3_SET_UCONFIG_REG_START; 2111 queue_ptr[wptr++] = 0xDEADBEEF; 2112 2113 for (i = wptr; i < compute_ring_align; i++) 2114 queue_ptr[wptr++] = PACKET3(PACKET3_NOP, 0x3FFF); 2115 2116 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 2117 *cpu_ptr = 0xCAFEDEAD; 2118 2119 queue_ptr[wptr++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 2120 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 2121 queue_ptr[wptr++] = lower_32_bits(fence_gpu_addr); 2122 queue_ptr[wptr++] = upper_32_bits(fence_gpu_addr); 2123 queue_ptr[wptr++] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 2124 queue_ptr[wptr++] = 0xDEADBEEF; 2125 2126 for (i = wptr; i < sdma_ring_align; i++) 2127 queue_ptr[wptr++] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 2128 2129 wptr <<= 2; 2130 } 2131 2132 atomic64_set((atomic64_t *)wptr_cpu_addr, wptr); 2133 WDOORBELL64(doorbell_idx, wptr); 2134 2135 for (i = 0; i < adev->usec_timeout; i++) { 2136 if (queue_type == AMDGPU_RING_TYPE_SDMA) { 2137 tmp = le32_to_cpu(*cpu_ptr); 2138 } else { 2139 if (!adev->mes.enable_coop_mode) { 2140 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2141 regSCRATCH_REG0); 2142 } else { 2143 for (j = 0; j < num_xcc; j++) { 2144 if (xcc_id != adev->mes.master_xcc_ids[j]) 2145 continue; 2146 2147 tmp = RREG32_SOC15(GC, GET_INST(GC, j), 2148 regSCRATCH_REG0); 2149 if (tmp != 0xDEADBEEF) 2150 break; 2151 } 2152 } 2153 } 2154 2155 if (tmp == 0xDEADBEEF) 2156 break; 2157 2158 if (amdgpu_emu_mode == 1) 2159 msleep(1); 2160 else 2161 udelay(1); 2162 } 2163 2164 if (i >= adev->usec_timeout) { 2165 dev_err(adev->dev, "xcc%d: mes self test (%s) failed\n", xcc_id, 2166 queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); 2167 2168 while (halt_if_hws_hang) 2169 schedule(); 2170 2171 r = -ETIMEDOUT; 2172 } else { 2173 dev_info(adev->dev, "xcc%d: mes self test (%s) pass\n", xcc_id, 2174 queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); 2175 } 2176 2177 return r; 2178 } 2179 2180 #define USER_CTX_SIZE (PAGE_SIZE * 2) 2181 #define USER_CTX_VA AMDGPU_VA_RESERVED_BOTTOM 2182 #define RING_OFFSET(addr) ((addr)) 2183 #define EOP_OFFSET(addr) ((addr) + PAGE_SIZE) 2184 #define WPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64)) 2185 #define RPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 2) 2186 #define FENCE_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 3) 2187 2188 static int mes_v12_1_test_queue(struct amdgpu_device *adev, int xcc_id, 2189 int pasid, struct amdgpu_vm *vm, u64 meta_gpu_addr, 2190 u64 queue_gpu_addr, void *ctx_ptr, int queue_type) 2191 { 2192 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 2193 struct amdgpu_mqd *mqd_mgr = &adev->mqds[queue_type]; 2194 struct amdgpu_mqd_prop mqd_prop = {0}; 2195 struct mes_add_queue_input add_queue = {0}; 2196 struct mes_remove_queue_input remove_queue = {0}; 2197 struct amdgpu_bo *mqd_bo = NULL; 2198 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2199 int i, r, off, mqd_size, mqd_count = 1; 2200 void *mqd_ptr = NULL; 2201 u64 mqd_gpu_addr, doorbell_idx; 2202 2203 /* extra one page size padding for mes fw */ 2204 mqd_size = mqd_mgr->mqd_size + PAGE_SIZE; 2205 2206 if (queue_type == AMDGPU_RING_TYPE_SDMA) { 2207 doorbell_idx = adev->mes.db_start_dw_offset + \ 2208 adev->doorbell_index.sdma_engine[0]; 2209 } else { 2210 doorbell_idx = adev->mes.db_start_dw_offset + \ 2211 adev->doorbell_index.userqueue_start; 2212 } 2213 2214 if (adev->mes.enable_coop_mode && 2215 queue_type == AMDGPU_RING_TYPE_COMPUTE) { 2216 for (i = 0, mqd_count = 0; i < num_xcc; i++) { 2217 if (adev->mes.master_xcc_ids[i] == xcc_id) 2218 mqd_count++; 2219 } 2220 mqd_size *= mqd_count; 2221 } 2222 2223 r = mes_v12_1_alloc_test_buf(adev, &mqd_bo, &mqd_gpu_addr, 2224 &mqd_ptr, mqd_size * mqd_count); 2225 if (r < 0) 2226 return r; 2227 2228 mqd_prop.mqd_gpu_addr = mqd_gpu_addr; 2229 mqd_prop.hqd_base_gpu_addr = RING_OFFSET(USER_CTX_VA); 2230 mqd_prop.eop_gpu_addr = EOP_OFFSET(USER_CTX_VA); 2231 mqd_prop.wptr_gpu_addr = WPTR_OFFSET(USER_CTX_VA); 2232 mqd_prop.rptr_gpu_addr = RPTR_OFFSET(USER_CTX_VA); 2233 mqd_prop.doorbell_index = doorbell_idx; 2234 mqd_prop.queue_size = PAGE_SIZE; 2235 mqd_prop.mqd_stride_size = mqd_size; 2236 mqd_prop.use_doorbell = true; 2237 mqd_prop.hqd_active = false; 2238 2239 mqd_mgr->init_mqd(adev, mqd_ptr, &mqd_prop); 2240 if (mqd_count > 1) { 2241 for (i = 1; i < mqd_count; i++) { 2242 off = mqd_size * i; 2243 mqd_prop.mqd_gpu_addr = mqd_gpu_addr + off; 2244 mqd_mgr->init_mqd(adev, (char *)mqd_ptr + off, 2245 &mqd_prop); 2246 } 2247 } 2248 2249 add_queue.xcc_id = xcc_id; 2250 add_queue.process_id = pasid; 2251 add_queue.page_table_base_addr = adev->vm_manager.vram_base_offset + 2252 amdgpu_bo_gpu_offset(vm->root.bo) - adev->gmc.vram_start; 2253 add_queue.process_va_start = 0; 2254 add_queue.process_va_end = adev->vm_manager.max_pfn - 1; 2255 add_queue.process_context_addr = meta_gpu_addr; 2256 add_queue.gang_context_addr = meta_gpu_addr + AMDGPU_MES_PROC_CTX_SIZE; 2257 add_queue.doorbell_offset = doorbell_idx; 2258 add_queue.mqd_addr = mqd_gpu_addr; 2259 add_queue.wptr_addr = mqd_prop.wptr_gpu_addr; 2260 add_queue.wptr_mc_addr = WPTR_OFFSET(queue_gpu_addr); 2261 add_queue.queue_type = queue_type; 2262 add_queue.vm_cntx_cntl = hub->vm_cntx_cntl; 2263 2264 r = mes_v12_1_add_hw_queue(&adev->mes, &add_queue); 2265 if (r) 2266 goto error; 2267 2268 mes_v12_1_test_ring(adev, xcc_id, (u32 *)RING_OFFSET((char *)ctx_ptr), 2269 FENCE_OFFSET(USER_CTX_VA), 2270 FENCE_OFFSET((char *)ctx_ptr), 2271 WPTR_OFFSET((char *)ctx_ptr), 2272 doorbell_idx, queue_type); 2273 2274 remove_queue.xcc_id = xcc_id; 2275 remove_queue.doorbell_offset = doorbell_idx; 2276 remove_queue.gang_context_addr = add_queue.gang_context_addr; 2277 remove_queue.queue_type = queue_type; 2278 r = mes_v12_1_remove_hw_queue(&adev->mes, &remove_queue); 2279 2280 error: 2281 amdgpu_bo_free_kernel(&mqd_bo, &mqd_gpu_addr, &mqd_ptr); 2282 return r; 2283 } 2284 2285 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id) 2286 { 2287 int queue_types[] = { AMDGPU_RING_TYPE_COMPUTE, 2288 /* AMDGPU_RING_TYPE_SDMA */ }; 2289 struct amdgpu_bo_va *bo_va = NULL; 2290 struct amdgpu_vm *vm = NULL; 2291 struct amdgpu_bo *meta_bo = NULL, *ctx_bo = NULL; 2292 void *meta_ptr = NULL, *ctx_ptr = NULL; 2293 u64 meta_gpu_addr, ctx_gpu_addr; 2294 int size, i, r, pasid; 2295 2296 pasid = amdgpu_pasid_alloc(16); 2297 if (pasid < 0) 2298 pasid = 0; 2299 2300 size = AMDGPU_MES_PROC_CTX_SIZE + AMDGPU_MES_GANG_CTX_SIZE; 2301 r = mes_v12_1_alloc_test_buf(adev, &meta_bo, &meta_gpu_addr, 2302 &meta_ptr, size); 2303 if (r < 0) 2304 goto err2; 2305 2306 r = mes_v12_1_alloc_test_buf(adev, &ctx_bo, &ctx_gpu_addr, 2307 &ctx_ptr, USER_CTX_SIZE); 2308 if (r < 0) 2309 goto err2; 2310 2311 vm = kzalloc(sizeof(*vm), GFP_KERNEL); 2312 if (!vm) { 2313 r = -ENOMEM; 2314 goto err2; 2315 } 2316 2317 r = amdgpu_vm_init(adev, vm, -1, pasid); 2318 if (r) 2319 goto err1; 2320 2321 r = mes_v12_1_map_test_bo(adev, ctx_bo, vm, &bo_va, 2322 USER_CTX_VA, USER_CTX_SIZE); 2323 if (r) 2324 goto err0; 2325 2326 for (i = 0; i < ARRAY_SIZE(queue_types); i++) { 2327 memset(ctx_ptr, 0, USER_CTX_SIZE); 2328 2329 r = mes_v12_1_test_queue(adev, xcc_id, pasid, vm, meta_gpu_addr, 2330 ctx_gpu_addr, ctx_ptr, queue_types[i]); 2331 if (r) 2332 break; 2333 } 2334 2335 amdgpu_unmap_static_csa(adev, vm, ctx_bo, bo_va, USER_CTX_VA); 2336 err0: 2337 amdgpu_vm_fini(adev, vm); 2338 err1: 2339 kfree(vm); 2340 err2: 2341 amdgpu_bo_free_kernel(&meta_bo, &meta_gpu_addr, &meta_ptr); 2342 amdgpu_bo_free_kernel(&ctx_bo, &ctx_gpu_addr, &ctx_ptr); 2343 amdgpu_pasid_free(pasid); 2344 return r; 2345 } 2346 2347