1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc_v1_0.h" 29 #include "gc/gc_12_1_0_offset.h" 30 #include "gc/gc_12_1_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 #include "gfx_v12_1_pkt.h" 35 #include "sdma_v7_1_0_pkt_open.h" 36 37 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin"); 40 41 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block); 42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id); 43 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 46 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id); 47 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id); 48 49 #define MES_EOP_SIZE 2048 50 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 #define MES12_HUNG_HQD_INFO_OFFSET 4 52 53 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 54 #define XCC_MID_MASK 0x41000000 55 56 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) 57 { 58 struct amdgpu_device *adev = ring->adev; 59 60 if (ring->use_doorbell) { 61 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 62 ring->wptr); 63 WDOORBELL64(ring->doorbell_index, ring->wptr); 64 } else { 65 BUG(); 66 } 67 } 68 69 static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring) 70 { 71 return *ring->rptr_cpu_addr; 72 } 73 74 static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring) 75 { 76 u64 wptr; 77 78 if (ring->use_doorbell) 79 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 80 else 81 BUG(); 82 return wptr; 83 } 84 85 static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = { 86 .type = AMDGPU_RING_TYPE_MES, 87 .align_mask = 1, 88 .nop = 0, 89 .support_64bit_ptrs = true, 90 .get_rptr = mes_v12_1_ring_get_rptr, 91 .get_wptr = mes_v12_1_ring_get_wptr, 92 .set_wptr = mes_v12_1_ring_set_wptr, 93 .insert_nop = amdgpu_ring_insert_nop, 94 }; 95 96 static const char *mes_v12_1_opcodes[] = { 97 "SET_HW_RSRC", 98 "SET_SCHEDULING_CONFIG", 99 "ADD_QUEUE", 100 "REMOVE_QUEUE", 101 "PERFORM_YIELD", 102 "SET_GANG_PRIORITY_LEVEL", 103 "SUSPEND", 104 "RESUME", 105 "RESET", 106 "SET_LOG_BUFFER", 107 "CHANGE_GANG_PRORITY", 108 "QUERY_SCHEDULER_STATUS", 109 "unused", 110 "SET_DEBUG_VMID", 111 "MISC", 112 "UPDATE_ROOT_PAGE_TABLE", 113 "AMD_LOG", 114 "SET_SE_MODE", 115 "SET_GANG_SUBMIT", 116 "SET_HW_RSRC_1", 117 "INVALIDATE_TLBS", 118 }; 119 120 static const char *mes_v12_1_misc_opcodes[] = { 121 "WRITE_REG", 122 "INV_GART", 123 "QUERY_STATUS", 124 "READ_REG", 125 "WAIT_REG_MEM", 126 "SET_SHADER_DEBUGGER", 127 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 128 "NOTIFY_TO_UNMAP_PROCESSES", 129 }; 130 131 static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt) 132 { 133 const char *op_str = NULL; 134 135 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes)) 136 op_str = mes_v12_1_opcodes[x_pkt->header.opcode]; 137 138 return op_str; 139 } 140 141 static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt) 142 { 143 const char *op_str = NULL; 144 145 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 146 (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes))) 147 op_str = mes_v12_1_misc_opcodes[x_pkt->opcode]; 148 149 return op_str; 150 } 151 152 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 153 int xcc_id, int pipe, void *pkt, 154 int size, int api_status_off) 155 { 156 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 157 signed long timeout = 2100000; /* 2100 ms */ 158 struct amdgpu_device *adev = mes->adev; 159 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; 160 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; 161 struct MES_API_STATUS *api_status; 162 union MESAPI__MISC *x_pkt = pkt; 163 const char *op_str, *misc_op_str; 164 unsigned long flags; 165 u64 status_gpu_addr; 166 u32 seq, status_offset; 167 u64 *status_ptr; 168 signed long r; 169 int ret; 170 171 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 172 return -EINVAL; 173 174 if (amdgpu_emu_mode) { 175 timeout *= 1000; 176 } else if (amdgpu_sriov_vf(adev)) { 177 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 178 timeout = 15 * 600 * 1000; 179 } 180 181 ret = amdgpu_device_wb_get(adev, &status_offset); 182 if (ret) 183 return ret; 184 185 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 186 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 187 *status_ptr = 0; 188 189 spin_lock_irqsave(ring_lock, flags); 190 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 191 if (r) 192 goto error_unlock_free; 193 194 seq = ++ring->fence_drv.sync_seq; 195 r = amdgpu_fence_wait_polling(ring, 196 seq - ring->fence_drv.num_fences_mask, 197 timeout); 198 if (r < 1) 199 goto error_undo; 200 201 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 202 api_status->api_completion_fence_addr = status_gpu_addr; 203 api_status->api_completion_fence_value = 1; 204 205 amdgpu_ring_write_multiple(ring, pkt, size / 4); 206 207 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 208 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 209 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 210 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 211 mes_status_pkt.api_status.api_completion_fence_addr = 212 ring->fence_drv.gpu_addr; 213 mes_status_pkt.api_status.api_completion_fence_value = seq; 214 215 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 216 sizeof(mes_status_pkt) / 4); 217 218 amdgpu_ring_commit(ring); 219 spin_unlock_irqrestore(ring_lock, flags); 220 221 op_str = mes_v12_1_get_op_string(x_pkt); 222 misc_op_str = mes_v12_1_get_misc_op_string(x_pkt); 223 224 if (misc_op_str) 225 dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n", 226 xcc_id, pipe, op_str, misc_op_str); 227 else if (op_str) 228 dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n", 229 xcc_id, pipe, op_str); 230 else 231 dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n", 232 xcc_id, pipe, x_pkt->header.opcode); 233 234 r = amdgpu_fence_wait_polling(ring, seq, timeout); 235 if (r < 1 || !lower_32_bits(*status_ptr)) { 236 if (misc_op_str) 237 dev_err(adev->dev, 238 "MES(%d, %d) failed to respond to msg=%s (%s)\n", 239 xcc_id, pipe, op_str, misc_op_str); 240 else if (op_str) 241 dev_err(adev->dev, 242 "MES(%d, %d) failed to respond to msg=%s\n", 243 xcc_id, pipe, op_str); 244 else 245 dev_err(adev->dev, 246 "MES(%d, %d) failed to respond to msg=%d\n", 247 xcc_id, pipe, x_pkt->header.opcode); 248 249 while (halt_if_hws_hang) 250 schedule(); 251 252 r = -ETIMEDOUT; 253 goto error_wb_free; 254 } 255 256 amdgpu_device_wb_free(adev, status_offset); 257 return 0; 258 259 error_undo: 260 dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe); 261 amdgpu_ring_undo(ring); 262 263 error_unlock_free: 264 spin_unlock_irqrestore(ring_lock, flags); 265 266 error_wb_free: 267 amdgpu_device_wb_free(adev, status_offset); 268 return r; 269 } 270 271 static int convert_to_mes_queue_type(int queue_type) 272 { 273 if (queue_type == AMDGPU_RING_TYPE_GFX) 274 return MES_QUEUE_TYPE_GFX; 275 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 276 return MES_QUEUE_TYPE_COMPUTE; 277 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 278 return MES_QUEUE_TYPE_SDMA; 279 else if (queue_type == AMDGPU_RING_TYPE_MES) 280 return MES_QUEUE_TYPE_SCHQ; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, 287 struct mes_add_queue_input *input) 288 { 289 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 290 int xcc_id = input->xcc_id; 291 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 292 293 if (mes->enable_coop_mode) 294 xcc_id = mes->master_xcc_ids[inst]; 295 296 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 297 298 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 299 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 300 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 301 302 mes_add_queue_pkt.process_id = input->process_id; 303 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 304 mes_add_queue_pkt.process_va_start = input->process_va_start; 305 mes_add_queue_pkt.process_va_end = input->process_va_end; 306 mes_add_queue_pkt.process_quantum = input->process_quantum; 307 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 308 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 309 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 310 mes_add_queue_pkt.inprocess_gang_priority = 311 input->inprocess_gang_priority; 312 mes_add_queue_pkt.gang_global_priority_level = 313 input->gang_global_priority_level; 314 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 315 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 316 317 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 318 319 mes_add_queue_pkt.queue_type = 320 convert_to_mes_queue_type(input->queue_type); 321 mes_add_queue_pkt.paging = input->paging; 322 mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl; 323 mes_add_queue_pkt.gws_base = input->gws_base; 324 mes_add_queue_pkt.gws_size = input->gws_size; 325 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 326 mes_add_queue_pkt.tma_addr = input->tma_addr; 327 mes_add_queue_pkt.trap_en = input->trap_en; 328 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 329 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 330 331 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 332 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 333 mes_add_queue_pkt.gds_size = input->queue_size; 334 335 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 336 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 337 mes_add_queue_pkt.gds_size = input->queue_size; 338 339 mes_add_queue_pkt.full_sh_mem_config_data = input->sh_mem_config_data; 340 341 return mes_v12_1_submit_pkt_and_poll_completion(mes, 342 xcc_id, AMDGPU_MES_SCHED_PIPE, 343 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 344 offsetof(union MESAPI__ADD_QUEUE, api_status)); 345 } 346 347 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, 348 struct mes_remove_queue_input *input) 349 { 350 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 351 int xcc_id = input->xcc_id; 352 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 353 354 if (mes->enable_coop_mode) 355 xcc_id = mes->master_xcc_ids[inst]; 356 357 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 358 359 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 360 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 361 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 362 363 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 364 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 365 366 return mes_v12_1_submit_pkt_and_poll_completion(mes, 367 xcc_id, AMDGPU_MES_SCHED_PIPE, 368 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 369 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 370 } 371 372 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, 373 struct mes_reset_queue_input *input) 374 { 375 union MESAPI__RESET mes_reset_queue_pkt; 376 int pipe; 377 378 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 379 380 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 381 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 382 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 383 384 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 385 /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ 386 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 387 388 if (mes->adev->enable_uni_mes) 389 pipe = AMDGPU_MES_KIQ_PIPE; 390 else 391 pipe = AMDGPU_MES_SCHED_PIPE; 392 393 return mes_v12_1_submit_pkt_and_poll_completion(mes, 394 input->xcc_id, pipe, 395 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 396 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 397 } 398 399 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, 400 struct mes_map_legacy_queue_input *input) 401 { 402 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 403 int pipe; 404 405 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 406 407 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 408 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 409 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 410 411 mes_add_queue_pkt.pipe_id = input->pipe_id; 412 mes_add_queue_pkt.queue_id = input->queue_id; 413 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 414 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 415 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 416 mes_add_queue_pkt.queue_type = 417 convert_to_mes_queue_type(input->queue_type); 418 mes_add_queue_pkt.map_legacy_kq = 1; 419 420 if (mes->adev->enable_uni_mes) { 421 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 422 if (input->queue_type == AMDGPU_RING_TYPE_MES) 423 pipe = AMDGPU_MES_KIQ_PIPE; 424 else 425 pipe = AMDGPU_MES_SCHED_PIPE; 426 } else { 427 pipe = AMDGPU_MES_SCHED_PIPE; 428 } 429 430 return mes_v12_1_submit_pkt_and_poll_completion(mes, 431 input->xcc_id, pipe, 432 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 433 offsetof(union MESAPI__ADD_QUEUE, api_status)); 434 } 435 436 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, 437 struct mes_unmap_legacy_queue_input *input) 438 { 439 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 440 int pipe; 441 442 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 443 444 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 445 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 446 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 447 448 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 449 mes_remove_queue_pkt.gang_context_addr = 0; 450 451 mes_remove_queue_pkt.pipe_id = input->pipe_id; 452 mes_remove_queue_pkt.queue_id = input->queue_id; 453 454 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 455 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 456 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 457 mes_remove_queue_pkt.tf_data = 458 lower_32_bits(input->trail_fence_data); 459 } else { 460 mes_remove_queue_pkt.unmap_legacy_queue = 1; 461 mes_remove_queue_pkt.queue_type = 462 convert_to_mes_queue_type(input->queue_type); 463 } 464 465 if (mes->adev->enable_uni_mes) { 466 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 467 if (input->queue_type == AMDGPU_RING_TYPE_MES) 468 pipe = AMDGPU_MES_KIQ_PIPE; 469 else 470 pipe = AMDGPU_MES_SCHED_PIPE; 471 } else { 472 pipe = AMDGPU_MES_SCHED_PIPE; 473 } 474 475 return mes_v12_1_submit_pkt_and_poll_completion(mes, 476 input->xcc_id, pipe, 477 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 478 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 479 } 480 481 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, 482 struct mes_suspend_gang_input *input) 483 { 484 union MESAPI__SUSPEND mes_suspend_gang_pkt; 485 486 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 487 488 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 489 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 490 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 491 492 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 493 mes_suspend_gang_pkt.suspend_all_sdma_gangs = input->suspend_all_sdma_gangs; 494 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 495 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 496 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 497 498 /* Suspend gang is handled by master MES */ 499 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, 500 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 501 offsetof(union MESAPI__SUSPEND, api_status)); 502 } 503 504 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, 505 struct mes_resume_gang_input *input) 506 { 507 union MESAPI__RESUME mes_resume_gang_pkt; 508 509 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 510 511 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 512 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 513 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 514 515 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 516 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 517 518 /* Resume gang is handled by master MES */ 519 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, 520 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 521 offsetof(union MESAPI__RESUME, api_status)); 522 } 523 524 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, 525 int pipe, int xcc_id) 526 { 527 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 528 529 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 530 531 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 532 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 533 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 534 535 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 536 &mes_status_pkt, sizeof(mes_status_pkt), 537 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 538 } 539 static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) 540 { 541 return ((reg_offset >> 16) & 0x7); 542 } 543 544 static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, 545 struct RRMT_OPTION *rrmt_opt, 546 uint32_t *out_reg) 547 { 548 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 549 550 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) { 551 rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg); 552 rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? 553 MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; 554 } else { 555 rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID; 556 if (soc_v1_0_mid1_reg_range(reg)) 557 rrmt_opt->mid_die_id = 1; 558 } 559 560 *out_reg = soc_v1_0_normalize_reg_offset(reg); 561 } 562 563 static int mes_v12_1_misc_op(struct amdgpu_mes *mes, 564 struct mes_misc_op_input *input) 565 { 566 struct amdgpu_device *adev = mes->adev; 567 union MESAPI__MISC misc_pkt; 568 int pipe; 569 570 if (mes->adev->enable_uni_mes) 571 pipe = AMDGPU_MES_KIQ_PIPE; 572 else 573 pipe = AMDGPU_MES_SCHED_PIPE; 574 575 memset(&misc_pkt, 0, sizeof(misc_pkt)); 576 577 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 578 misc_pkt.header.opcode = MES_SCH_API_MISC; 579 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 580 581 switch (input->op) { 582 case MES_MISC_OP_READ_REG: 583 misc_pkt.opcode = MESAPI_MISC__READ_REG; 584 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 585 mes_v12_1_get_rrmt(input->read_reg.reg_offset, 586 GET_INST(GC, input->xcc_id), 587 &misc_pkt.read_reg.rrmt_opt, 588 &misc_pkt.read_reg.reg_offset); 589 break; 590 case MES_MISC_OP_WRITE_REG: 591 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 592 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 593 mes_v12_1_get_rrmt(input->write_reg.reg_offset, 594 GET_INST(GC, input->xcc_id), 595 &misc_pkt.write_reg.rrmt_opt, 596 &misc_pkt.write_reg.reg_offset); 597 break; 598 case MES_MISC_OP_WRM_REG_WAIT: 599 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 600 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 601 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 602 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 603 misc_pkt.wait_reg_mem.reg_offset2 = 0; 604 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 605 GET_INST(GC, input->xcc_id), 606 &misc_pkt.wait_reg_mem.rrmt_opt1, 607 &misc_pkt.wait_reg_mem.reg_offset1); 608 break; 609 case MES_MISC_OP_WRM_REG_WR_WAIT: 610 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 611 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 612 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 613 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 614 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 615 GET_INST(GC, input->xcc_id), 616 &misc_pkt.wait_reg_mem.rrmt_opt1, 617 &misc_pkt.wait_reg_mem.reg_offset1); 618 mes_v12_1_get_rrmt(input->wrm_reg.reg1, 619 GET_INST(GC, input->xcc_id), 620 &misc_pkt.wait_reg_mem.rrmt_opt2, 621 &misc_pkt.wait_reg_mem.reg_offset2); 622 break; 623 case MES_MISC_OP_SET_SHADER_DEBUGGER: 624 pipe = AMDGPU_MES_SCHED_PIPE; 625 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 626 misc_pkt.set_shader_debugger.process_context_addr = 627 input->set_shader_debugger.process_context_addr; 628 misc_pkt.set_shader_debugger.flags.u32all = 629 input->set_shader_debugger.flags.u32all; 630 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 631 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 632 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 633 input->set_shader_debugger.tcp_watch_cntl, 634 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 635 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 636 break; 637 case MES_MISC_OP_CHANGE_CONFIG: 638 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 639 misc_pkt.change_config.opcode = 640 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 641 misc_pkt.change_config.option.bits.limit_single_process = 642 input->change_config.option.limit_single_process; 643 break; 644 default: 645 DRM_ERROR("unsupported misc op (%d) \n", input->op); 646 return -EINVAL; 647 } 648 649 return mes_v12_1_submit_pkt_and_poll_completion(mes, 650 input->xcc_id, pipe, 651 &misc_pkt, sizeof(misc_pkt), 652 offsetof(union MESAPI__MISC, api_status)); 653 } 654 655 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, 656 int pipe, int xcc_id) 657 { 658 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 659 int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); 660 661 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 662 663 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 664 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 665 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 666 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 667 668 /* From version 0x74 above, pipe1 support use shared command buffer 669 to distribute some tasks on individual XCCs*/ 670 if (mes->enable_coop_mode && 671 ((pipe == AMDGPU_MES_SCHED_PIPE) || 672 ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) { 673 master_xcc_id = mes->master_xcc_ids[inst]; 674 mes_set_hw_res_1_pkt.mes_coop_mode = 1; 675 mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = 676 mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe]; 677 } 678 679 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 680 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 681 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 682 } 683 684 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, 685 int pipe, int xcc_id) 686 { 687 int i, status; 688 struct amdgpu_device *adev = mes->adev; 689 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 690 691 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 692 693 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 694 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 695 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 696 697 if (pipe == AMDGPU_MES_SCHED_PIPE) { 698 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 699 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 700 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 701 mes_set_hw_res_pkt.paging_vmid = 0; 702 703 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 704 mes_set_hw_res_pkt.compute_hqd_mask[i] = 705 mes->compute_hqd_mask[i]; 706 707 for (i = 0; i < MAX_GFX_PIPES; i++) 708 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 709 mes->gfx_hqd_mask[i]; 710 711 for (i = 0; i < MAX_SDMA_PIPES; i++) 712 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 713 mes->sdma_hqd_mask[i]; 714 715 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 716 mes_set_hw_res_pkt.aggregated_doorbells[i] = 717 mes->aggregated_doorbells[i]; 718 } 719 720 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 721 mes->sch_ctx_gpu_addr[pipe]; 722 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 723 mes->query_status_fence_gpu_addr[pipe]; 724 725 for (i = 0; i < 5; i++) { 726 mes_set_hw_res_pkt.gc_base[i] = 727 adev->reg_offset[GC_HWIP][0][i]; 728 mes_set_hw_res_pkt.mmhub_base[i] = 729 adev->reg_offset[MMHUB_HWIP][0][i]; 730 mes_set_hw_res_pkt.osssys_base[i] = 731 adev->reg_offset[OSSSYS_HWIP][0][i]; 732 } 733 734 mes_set_hw_res_pkt.disable_reset = 1; 735 mes_set_hw_res_pkt.disable_mes_log = 1; 736 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 737 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 738 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 739 740 /* 741 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 742 * handling support, other queue will not use the oversubscribe timer. 743 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 744 */ 745 mes_set_hw_res_pkt.oversubscription_timer = 50; 746 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 747 748 if (amdgpu_mes_log_enable) { 749 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 750 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 751 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE; 752 } 753 754 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 755 mes_set_hw_res_pkt.limit_single_process = 1; 756 757 status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 758 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 759 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 760 761 /* get MES scheduler versions */ 762 mutex_lock(&adev->srbm_mutex); 763 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 764 765 if (pipe == AMDGPU_MES_SCHED_PIPE) 766 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 767 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 768 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 769 770 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 771 mutex_unlock(&adev->srbm_mutex); 772 773 return status; 774 } 775 776 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, 777 int xcc_id) 778 { 779 struct amdgpu_device *adev = mes->adev; 780 uint32_t data; 781 782 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1); 783 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 784 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 785 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 786 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 787 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 788 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 789 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data); 790 791 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2); 792 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 793 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 794 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 795 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 796 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 797 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 798 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data); 799 800 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3); 801 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 802 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 803 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 804 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 805 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 806 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 807 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data); 808 809 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4); 810 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 811 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 812 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 813 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 814 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 815 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 816 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data); 817 818 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5); 819 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 820 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 821 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 822 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 823 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 824 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 825 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data); 826 827 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 828 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data); 829 } 830 831 832 static void mes_v12_1_enable_unmapped_doorbell_handling( 833 struct amdgpu_mes *mes, bool enable, int xcc_id) 834 { 835 struct amdgpu_device *adev = mes->adev; 836 uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL); 837 838 /* 839 * The default PROC_LSB settng is 0xc which means doorbell 840 * addr[16:12] gives the doorbell page number. For kfd, each 841 * process will use 2 pages of doorbell, we need to change the 842 * setting to 0xd 843 */ 844 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 845 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 846 847 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 848 849 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data); 850 } 851 852 #if 0 853 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, 854 struct mes_reset_legacy_queue_input *input) 855 { 856 union MESAPI__RESET mes_reset_queue_pkt; 857 int pipe; 858 859 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 860 861 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 862 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 863 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 864 865 mes_reset_queue_pkt.queue_type = 866 convert_to_mes_queue_type(input->queue_type); 867 868 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 869 mes_reset_queue_pkt.reset_legacy_gfx = 1; 870 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 871 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 872 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 873 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 874 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 875 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 876 } else { 877 mes_reset_queue_pkt.reset_queue_only = 1; 878 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 879 } 880 881 if (mes->adev->enable_uni_mes) 882 pipe = AMDGPU_MES_KIQ_PIPE; 883 else 884 pipe = AMDGPU_MES_SCHED_PIPE; 885 886 return mes_v12_1_submit_pkt_and_poll_completion(mes, 887 input->xcc_id, pipe, 888 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 889 offsetof(union MESAPI__RESET, api_status)); 890 } 891 #endif 892 893 static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 894 struct mes_detect_and_reset_queue_input *input) 895 { 896 union MESAPI__RESET mes_reset_queue_pkt; 897 898 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 899 900 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 901 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 902 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 903 904 mes_reset_queue_pkt.queue_type = 905 convert_to_mes_queue_type(input->queue_type); 906 mes_reset_queue_pkt.doorbell_offset_addr = 907 mes->hung_queue_db_array_gpu_addr[0]; 908 909 if (input->detect_only) 910 mes_reset_queue_pkt.hang_detect_only = 1; 911 else 912 mes_reset_queue_pkt.hang_detect_then_reset = 1; 913 914 return mes_v12_1_submit_pkt_and_poll_completion(mes, 915 input->xcc_id, AMDGPU_MES_SCHED_PIPE, 916 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 917 offsetof(union MESAPI__RESET, api_status)); 918 } 919 920 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 921 { 922 /* 923 * MES doesn't support invalidate gc_hub on slave xcc individually 924 * master xcc will invalidate all gc_hub for the partition 925 */ 926 if (AMDGPU_IS_GFXHUB(id)) 927 return 0; 928 else if (AMDGPU_IS_MMHUB0(id)) 929 return 1; 930 else if (AMDGPU_IS_MMHUB1(id)) 931 return 2; 932 return -EINVAL; 933 934 } 935 936 static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes, 937 struct mes_inv_tlbs_pasid_input *input) 938 { 939 union MESAPI__INV_TLBS mes_inv_tlbs; 940 int xcc_id = input->xcc_id; 941 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 942 int ret; 943 944 if (mes->enable_coop_mode) 945 xcc_id = mes->master_xcc_ids[inst]; 946 947 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 948 949 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 950 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 951 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 952 953 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 954 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 955 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 956 957 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 958 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 959 if (ret < 0) 960 return -EINVAL; 961 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 962 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE, 963 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 964 offsetof(union MESAPI__INV_TLBS, api_status)); 965 966 } 967 968 static const struct amdgpu_mes_funcs mes_v12_1_funcs = { 969 .add_hw_queue = mes_v12_1_add_hw_queue, 970 .remove_hw_queue = mes_v12_1_remove_hw_queue, 971 .map_legacy_queue = mes_v12_1_map_legacy_queue, 972 .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue, 973 .suspend_gang = mes_v12_1_suspend_gang, 974 .resume_gang = mes_v12_1_resume_gang, 975 .misc_op = mes_v12_1_misc_op, 976 .reset_hw_queue = mes_v12_1_reset_hw_queue, 977 .detect_and_reset_hung_queues = mes_v12_1_detect_and_reset_hung_queues, 978 .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, 979 }; 980 981 static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev, 982 enum amdgpu_mes_pipe pipe, 983 int xcc_id) 984 { 985 int r, inst = MES_PIPE_INST(xcc_id, pipe); 986 const struct mes_firmware_header_v1_0 *mes_hdr; 987 const __le32 *fw_data; 988 unsigned fw_size; 989 990 mes_hdr = (const struct mes_firmware_header_v1_0 *) 991 adev->mes.fw[pipe]->data; 992 993 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 994 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 995 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 996 997 r = amdgpu_bo_create_reserved(adev, fw_size, 998 PAGE_SIZE, 999 AMDGPU_GEM_DOMAIN_VRAM, 1000 &adev->mes.ucode_fw_obj[inst], 1001 &adev->mes.ucode_fw_gpu_addr[inst], 1002 (void **)&adev->mes.ucode_fw_ptr[inst]); 1003 if (r) { 1004 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1005 return r; 1006 } 1007 1008 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size); 1009 1010 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]); 1011 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]); 1012 1013 return 0; 1014 } 1015 1016 static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1017 enum amdgpu_mes_pipe pipe, 1018 int xcc_id) 1019 { 1020 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1021 const struct mes_firmware_header_v1_0 *mes_hdr; 1022 const __le32 *fw_data; 1023 unsigned fw_size; 1024 1025 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1026 adev->mes.fw[pipe]->data; 1027 1028 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1029 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1030 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1031 1032 r = amdgpu_bo_create_reserved(adev, fw_size, 1033 64 * 1024, 1034 AMDGPU_GEM_DOMAIN_VRAM, 1035 &adev->mes.data_fw_obj[inst], 1036 &adev->mes.data_fw_gpu_addr[inst], 1037 (void **)&adev->mes.data_fw_ptr[inst]); 1038 if (r) { 1039 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1040 return r; 1041 } 1042 1043 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size); 1044 1045 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]); 1046 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]); 1047 1048 return 0; 1049 } 1050 1051 static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev, 1052 enum amdgpu_mes_pipe pipe, 1053 int xcc_id) 1054 { 1055 int inst = MES_PIPE_INST(xcc_id, pipe); 1056 1057 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst], 1058 &adev->mes.data_fw_gpu_addr[inst], 1059 (void **)&adev->mes.data_fw_ptr[inst]); 1060 1061 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst], 1062 &adev->mes.ucode_fw_gpu_addr[inst], 1063 (void **)&adev->mes.ucode_fw_ptr[inst]); 1064 } 1065 1066 static void mes_v12_1_enable(struct amdgpu_device *adev, 1067 bool enable, int xcc_id) 1068 { 1069 uint64_t ucode_addr; 1070 uint32_t pipe, data = 0; 1071 1072 if (enable) { 1073 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1074 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1075 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1076 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1077 1078 mutex_lock(&adev->srbm_mutex); 1079 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1080 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, 1081 GET_INST(GC, xcc_id)); 1082 1083 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1084 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1085 regCP_MES_PRGRM_CNTR_START, 1086 lower_32_bits(ucode_addr)); 1087 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1088 regCP_MES_PRGRM_CNTR_START_HI, 1089 upper_32_bits(ucode_addr)); 1090 } 1091 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1092 mutex_unlock(&adev->srbm_mutex); 1093 1094 /* unhalt MES and activate pipe0 */ 1095 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1096 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1097 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1098 1099 if (amdgpu_emu_mode) 1100 msleep(500); 1101 else if (adev->enable_uni_mes) 1102 udelay(500); 1103 else 1104 udelay(50); 1105 } else { 1106 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1107 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1108 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1109 data = REG_SET_FIELD(data, CP_MES_CNTL, 1110 MES_INVALIDATE_ICACHE, 1); 1111 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1112 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1113 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1114 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1115 } 1116 } 1117 1118 static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev, 1119 int xcc_id) 1120 { 1121 uint64_t ucode_addr; 1122 int pipe; 1123 1124 mes_v12_1_enable(adev, false, xcc_id); 1125 1126 mutex_lock(&adev->srbm_mutex); 1127 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1128 /* me=3, queue=0 */ 1129 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1130 1131 /* set ucode start address */ 1132 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1133 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START, 1134 lower_32_bits(ucode_addr)); 1135 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI, 1136 upper_32_bits(ucode_addr)); 1137 1138 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1139 } 1140 mutex_unlock(&adev->srbm_mutex); 1141 } 1142 1143 /* This function is for backdoor MES firmware */ 1144 static int mes_v12_1_load_microcode(struct amdgpu_device *adev, 1145 enum amdgpu_mes_pipe pipe, 1146 bool prime_icache, int xcc_id) 1147 { 1148 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1149 uint32_t data; 1150 1151 mes_v12_1_enable(adev, false, xcc_id); 1152 1153 if (!adev->mes.fw[pipe]) 1154 return -EINVAL; 1155 1156 r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id); 1157 if (r) 1158 return r; 1159 1160 r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id); 1161 if (r) { 1162 mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id); 1163 return r; 1164 } 1165 1166 mutex_lock(&adev->srbm_mutex); 1167 /* me=3, pipe=0, queue=0 */ 1168 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1169 1170 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0); 1171 1172 /* set ucode fimrware address */ 1173 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO, 1174 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1175 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI, 1176 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1177 1178 /* set ucode instruction cache boundary to 2M-1 */ 1179 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF); 1180 1181 /* set ucode data firmware address */ 1182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO, 1183 lower_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1184 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI, 1185 upper_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1186 1187 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1188 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF); 1189 1190 if (prime_icache) { 1191 /* invalidate ICACHE */ 1192 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1193 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1194 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1195 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1196 1197 /* prime the ICACHE. */ 1198 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1199 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1200 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1201 } 1202 1203 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1204 mutex_unlock(&adev->srbm_mutex); 1205 1206 return 0; 1207 } 1208 1209 static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev, 1210 enum amdgpu_mes_pipe pipe, 1211 int xcc_id) 1212 { 1213 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1214 u32 *eop; 1215 1216 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1217 AMDGPU_GEM_DOMAIN_GTT, 1218 &adev->mes.eop_gpu_obj[inst], 1219 &adev->mes.eop_gpu_addr[inst], 1220 (void **)&eop); 1221 if (r) { 1222 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1223 return r; 1224 } 1225 1226 memset(eop, 0, 1227 adev->mes.eop_gpu_obj[inst]->tbo.base.size); 1228 1229 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]); 1230 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]); 1231 1232 return 0; 1233 } 1234 1235 static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, 1236 enum amdgpu_mes_pipe pipe, 1237 int xcc_id) 1238 { 1239 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1240 1241 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1242 AMDGPU_GEM_DOMAIN_VRAM, 1243 &adev->mes.shared_cmd_buf_obj[inst], 1244 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1245 NULL); 1246 if (r) { 1247 dev_err(adev->dev, 1248 "(%d) failed to create shared cmd buf bo\n", r); 1249 return r; 1250 } 1251 1252 return 0; 1253 } 1254 1255 static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) 1256 { 1257 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1258 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1259 uint32_t tmp; 1260 1261 mqd->header = 0xC0310800; 1262 mqd->compute_pipelinestat_enable = 0x00000001; 1263 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1264 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1265 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1266 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1267 mqd->compute_misc_reserved = 0x00000007; 1268 1269 eop_base_addr = ring->eop_gpu_addr >> 8; 1270 1271 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1272 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1273 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1274 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1275 1276 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1277 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1278 mqd->cp_hqd_eop_control = tmp; 1279 1280 /* disable the queue if it's active */ 1281 ring->wptr = 0; 1282 mqd->cp_hqd_pq_rptr = 0; 1283 mqd->cp_hqd_pq_wptr_lo = 0; 1284 mqd->cp_hqd_pq_wptr_hi = 0; 1285 1286 /* set the pointer to the MQD */ 1287 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1288 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1289 1290 /* set MQD vmid to 0 */ 1291 tmp = regCP_MQD_CONTROL_DEFAULT; 1292 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1293 mqd->cp_mqd_control = tmp; 1294 1295 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1296 hqd_gpu_addr = ring->gpu_addr >> 8; 1297 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1298 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1299 1300 /* set the wb address whether it's enabled or not */ 1301 wb_gpu_addr = ring->rptr_gpu_addr; 1302 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1303 mqd->cp_hqd_pq_rptr_report_addr_hi = 1304 upper_32_bits(wb_gpu_addr) & 0xffff; 1305 1306 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1307 wb_gpu_addr = ring->wptr_gpu_addr; 1308 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1309 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1310 1311 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1312 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1313 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1314 (order_base_2(ring->ring_size / 4) - 1)); 1315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1316 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1317 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1318 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1319 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1322 mqd->cp_hqd_pq_control = tmp; 1323 1324 /* enable doorbell */ 1325 tmp = 0; 1326 if (ring->use_doorbell) { 1327 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1328 DOORBELL_OFFSET, ring->doorbell_index); 1329 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1330 DOORBELL_EN, 1); 1331 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1332 DOORBELL_SOURCE, 0); 1333 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1334 DOORBELL_HIT, 0); 1335 } else { 1336 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1337 DOORBELL_EN, 0); 1338 } 1339 mqd->cp_hqd_pq_doorbell_control = tmp; 1340 1341 mqd->cp_hqd_vmid = 0; 1342 /* activate the queue */ 1343 mqd->cp_hqd_active = 1; 1344 1345 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1346 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1347 PRELOAD_SIZE, 0x63); 1348 mqd->cp_hqd_persistent_state = tmp; 1349 1350 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT; 1351 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1352 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1353 1354 /* 1355 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1356 * doorbell handling. This is a reserved CP internal register can 1357 * not be accesss by others 1358 */ 1359 mqd->cp_hqd_gfx_control = BIT(15); 1360 1361 return 0; 1362 } 1363 1364 static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring, 1365 int xcc_id) 1366 { 1367 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1368 struct amdgpu_device *adev = ring->adev; 1369 uint32_t data = 0; 1370 1371 mutex_lock(&adev->srbm_mutex); 1372 soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id)); 1373 1374 /* set CP_HQD_VMID.VMID = 0. */ 1375 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID); 1376 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1377 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data); 1378 1379 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1380 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1381 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1382 DOORBELL_EN, 0); 1383 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1384 1385 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1386 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1387 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1388 1389 /* set CP_MQD_CONTROL.VMID=0 */ 1390 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1391 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1392 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0); 1393 1394 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1395 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1396 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1397 1398 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1399 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1400 mqd->cp_hqd_pq_rptr_report_addr_lo); 1401 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1402 mqd->cp_hqd_pq_rptr_report_addr_hi); 1403 1404 /* set CP_HQD_PQ_CONTROL */ 1405 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1406 1407 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1408 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1409 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1410 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1411 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1412 1413 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1414 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1415 mqd->cp_hqd_pq_doorbell_control); 1416 1417 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1419 1420 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1421 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1422 1423 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1424 mutex_unlock(&adev->srbm_mutex); 1425 } 1426 1427 static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id) 1428 { 1429 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 1430 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; 1431 int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1432 1433 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1434 return -EINVAL; 1435 1436 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1437 if (r) { 1438 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1439 return r; 1440 } 1441 1442 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); 1443 1444 r = amdgpu_ring_test_ring(kiq_ring); 1445 if (r) { 1446 DRM_ERROR("kfq enable failed\n"); 1447 kiq_ring->sched.ready = false; 1448 } 1449 return r; 1450 } 1451 1452 static int mes_v12_1_queue_init(struct amdgpu_device *adev, 1453 enum amdgpu_mes_pipe pipe, 1454 int xcc_id) 1455 { 1456 struct amdgpu_ring *ring; 1457 int r; 1458 1459 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1460 ring = &adev->gfx.kiq[xcc_id].ring; 1461 else 1462 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)]; 1463 1464 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1465 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1466 *(ring->wptr_cpu_addr) = 0; 1467 *(ring->rptr_cpu_addr) = 0; 1468 amdgpu_ring_clear_ring(ring); 1469 } 1470 1471 r = mes_v12_1_mqd_init(ring); 1472 if (r) 1473 return r; 1474 1475 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1476 if (adev->enable_uni_mes) 1477 r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id); 1478 else 1479 r = mes_v12_1_kiq_enable_queue(adev, xcc_id); 1480 if (r) 1481 return r; 1482 } else { 1483 mes_v12_1_queue_init_register(ring, xcc_id); 1484 } 1485 1486 return 0; 1487 } 1488 1489 static int mes_v12_1_ring_init(struct amdgpu_device *adev, 1490 int xcc_id, int pipe) 1491 { 1492 struct amdgpu_ring *ring; 1493 int inst = MES_PIPE_INST(xcc_id, pipe); 1494 1495 ring = &adev->mes.ring[inst]; 1496 1497 ring->funcs = &mes_v12_1_ring_funcs; 1498 1499 ring->me = 3; 1500 ring->pipe = pipe; 1501 ring->queue = 0; 1502 ring->xcc_id = xcc_id; 1503 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1504 1505 ring->ring_obj = NULL; 1506 ring->use_doorbell = true; 1507 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1508 ring->no_scheduler = true; 1509 snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu", 1510 (unsigned char)xcc_id, (unsigned char)ring->me, 1511 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1512 1513 if (pipe == AMDGPU_MES_SCHED_PIPE) 1514 ring->doorbell_index = 1515 (adev->doorbell_index.mes_ring0 + 1516 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1517 << 1; 1518 else 1519 ring->doorbell_index = 1520 (adev->doorbell_index.mes_ring1 + 1521 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1522 << 1; 1523 1524 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1525 AMDGPU_RING_PRIO_DEFAULT, NULL); 1526 } 1527 1528 static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id) 1529 { 1530 struct amdgpu_ring *ring; 1531 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1532 1533 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); 1534 1535 ring = &adev->gfx.kiq[xcc_id].ring; 1536 1537 ring->me = 3; 1538 ring->pipe = 1; 1539 ring->queue = 0; 1540 ring->xcc_id = xcc_id; 1541 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1542 1543 ring->adev = NULL; 1544 ring->ring_obj = NULL; 1545 ring->use_doorbell = true; 1546 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1547 ring->no_scheduler = true; 1548 ring->doorbell_index = 1549 (adev->doorbell_index.mes_ring1 + 1550 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1551 << 1; 1552 1553 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu", 1554 (unsigned char)xcc_id, (unsigned char)ring->me, 1555 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1556 1557 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1558 AMDGPU_RING_PRIO_DEFAULT, NULL); 1559 } 1560 1561 static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev, 1562 enum amdgpu_mes_pipe pipe, 1563 int xcc_id) 1564 { 1565 int r, mqd_size = sizeof(struct v12_1_mes_mqd); 1566 struct amdgpu_ring *ring; 1567 int inst = MES_PIPE_INST(xcc_id, pipe); 1568 1569 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1570 ring = &adev->gfx.kiq[xcc_id].ring; 1571 else 1572 ring = &adev->mes.ring[inst]; 1573 1574 if (ring->mqd_obj) 1575 return 0; 1576 1577 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1578 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1579 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1580 if (r) { 1581 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1582 return r; 1583 } 1584 1585 memset(ring->mqd_ptr, 0, mqd_size); 1586 1587 /* prepare MQD backup */ 1588 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL); 1589 if (!adev->mes.mqd_backup[inst]) 1590 dev_warn(adev->dev, 1591 "no memory to create MQD backup for ring %s\n", 1592 ring->name); 1593 1594 return 0; 1595 } 1596 1597 static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1598 { 1599 struct amdgpu_device *adev = ip_block->adev; 1600 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1601 1602 adev->mes.funcs = &mes_v12_1_funcs; 1603 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; 1604 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; 1605 adev->mes.enable_legacy_queue_map = true; 1606 1607 adev->mes.event_log_size = 1608 adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE; 1609 1610 r = amdgpu_mes_init(adev); 1611 if (r) 1612 return r; 1613 1614 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1615 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1616 r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id); 1617 if (r) 1618 return r; 1619 1620 r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id); 1621 if (r) 1622 return r; 1623 1624 if (!adev->enable_uni_mes && pipe == 1625 AMDGPU_MES_KIQ_PIPE) 1626 r = mes_v12_1_kiq_ring_init(adev, xcc_id); 1627 else 1628 r = mes_v12_1_ring_init(adev, xcc_id, pipe); 1629 if (r) 1630 return r; 1631 1632 if (adev->enable_uni_mes && num_xcc > 1) { 1633 r = mes_v12_1_allocate_shared_cmd_buf(adev, 1634 pipe, xcc_id); 1635 if (r) 1636 return r; 1637 } 1638 } 1639 } 1640 1641 return 0; 1642 } 1643 1644 static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1645 { 1646 struct amdgpu_device *adev = ip_block->adev; 1647 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1648 1649 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1650 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1651 inst = MES_PIPE_INST(xcc_id, pipe); 1652 1653 amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst], 1654 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1655 NULL); 1656 1657 kfree(adev->mes.mqd_backup[inst]); 1658 1659 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], 1660 &adev->mes.eop_gpu_addr[inst], 1661 NULL); 1662 1663 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1664 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, 1665 &adev->mes.ring[inst].mqd_gpu_addr, 1666 &adev->mes.ring[inst].mqd_ptr); 1667 amdgpu_ring_fini(&adev->mes.ring[inst]); 1668 } 1669 } 1670 } 1671 1672 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) 1673 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1674 1675 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1676 if (!adev->enable_uni_mes) { 1677 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, 1678 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, 1679 &adev->gfx.kiq[xcc_id].ring.mqd_ptr); 1680 amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring); 1681 } 1682 1683 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1684 mes_v12_1_free_ucode_buffers(adev, 1685 AMDGPU_MES_KIQ_PIPE, xcc_id); 1686 mes_v12_1_free_ucode_buffers(adev, 1687 AMDGPU_MES_SCHED_PIPE, xcc_id); 1688 } 1689 } 1690 1691 amdgpu_mes_fini(adev); 1692 return 0; 1693 } 1694 1695 static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev, 1696 int xcc_id) 1697 { 1698 uint32_t data; 1699 int i; 1700 1701 mutex_lock(&adev->srbm_mutex); 1702 soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0, 1703 GET_INST(GC, xcc_id)); 1704 1705 /* disable the queue if it's active */ 1706 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1707 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1708 for (i = 0; i < adev->usec_timeout; i++) { 1709 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1710 break; 1711 udelay(1); 1712 } 1713 } 1714 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1715 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1716 DOORBELL_EN, 0); 1717 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1718 DOORBELL_HIT, 1); 1719 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1720 1721 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1722 1723 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1724 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1725 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1726 1727 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1728 mutex_unlock(&adev->srbm_mutex); 1729 1730 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false; 1731 } 1732 1733 static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1734 { 1735 uint32_t tmp; 1736 struct amdgpu_device *adev = ring->adev; 1737 1738 /* tell RLC which is KIQ queue */ 1739 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1740 tmp &= 0xffffff00; 1741 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1742 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1743 tmp |= 0x80; 1744 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1745 } 1746 1747 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1748 { 1749 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1750 int r = 0; 1751 struct amdgpu_ip_block *ip_block; 1752 1753 if (adev->enable_uni_mes) 1754 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id); 1755 else 1756 mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id); 1757 1758 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1759 1760 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, 1761 false, xcc_id); 1762 if (r) { 1763 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1764 return r; 1765 } 1766 1767 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, 1768 true, xcc_id); 1769 if (r) { 1770 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1771 return r; 1772 } 1773 1774 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1775 1776 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1777 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1778 1779 mes_v12_1_enable(adev, true, xcc_id); 1780 1781 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1782 if (unlikely(!ip_block)) { 1783 dev_err(adev->dev, "Failed to get MES handle\n"); 1784 return -EINVAL; 1785 } 1786 1787 r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id); 1788 if (r) 1789 goto failure; 1790 1791 if (adev->enable_uni_mes) { 1792 r = mes_v12_1_setup_coop_mode(adev, xcc_id); 1793 if (r) 1794 goto failure; 1795 1796 r = mes_v12_1_set_hw_resources(&adev->mes, 1797 AMDGPU_MES_KIQ_PIPE, xcc_id); 1798 if (r) 1799 goto failure; 1800 1801 mes_v12_1_set_hw_resources_1(&adev->mes, 1802 AMDGPU_MES_KIQ_PIPE, xcc_id); 1803 } 1804 1805 if (adev->mes.enable_legacy_queue_map) { 1806 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1807 if (r) 1808 goto failure; 1809 } 1810 1811 return r; 1812 1813 failure: 1814 mes_v12_1_hw_fini(ip_block); 1815 return r; 1816 } 1817 1818 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1819 { 1820 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1821 1822 if (adev->mes.ring[inst].sched.ready) { 1823 if (adev->enable_uni_mes) 1824 amdgpu_mes_unmap_legacy_queue(adev, 1825 &adev->mes.ring[inst], 1826 RESET_QUEUES, 0, 0, xcc_id); 1827 else 1828 mes_v12_1_kiq_dequeue_sched(adev, xcc_id); 1829 1830 adev->mes.ring[inst].sched.ready = false; 1831 } 1832 1833 mes_v12_1_enable(adev, false, xcc_id); 1834 1835 return 0; 1836 } 1837 1838 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id) 1839 { 1840 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1841 int r = 0; 1842 1843 if (num_xcc == 1) 1844 return r; 1845 1846 if (adev->gfx.funcs && 1847 adev->gfx.funcs->get_xccs_per_xcp) 1848 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 1849 else 1850 return -EINVAL; 1851 1852 switch (adev->xcp_mgr->mode) { 1853 case AMDGPU_SPX_PARTITION_MODE: 1854 adev->mes.enable_coop_mode = 1; 1855 adev->mes.master_xcc_ids[xcc_id] = 0; 1856 break; 1857 case AMDGPU_DPX_PARTITION_MODE: 1858 adev->mes.enable_coop_mode = 1; 1859 adev->mes.master_xcc_ids[xcc_id] = 1860 (xcc_id/num_xcc_per_xcp) * (num_xcc / 2); 1861 break; 1862 case AMDGPU_QPX_PARTITION_MODE: 1863 adev->mes.enable_coop_mode = 1; 1864 adev->mes.master_xcc_ids[xcc_id] = 1865 (xcc_id/num_xcc_per_xcp) * (num_xcc / 4); 1866 break; 1867 case AMDGPU_CPX_PARTITION_MODE: 1868 adev->mes.enable_coop_mode = 0; 1869 break; 1870 default: 1871 r = -EINVAL; 1872 break; 1873 } 1874 return r; 1875 } 1876 1877 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) 1878 { 1879 int r; 1880 struct amdgpu_device *adev = ip_block->adev; 1881 1882 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready) 1883 goto out; 1884 1885 if (!adev->enable_mes_kiq) { 1886 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1887 r = mes_v12_1_load_microcode(adev, 1888 AMDGPU_MES_SCHED_PIPE, true, xcc_id); 1889 if (r) { 1890 DRM_ERROR("failed to MES fw, r=%d\n", r); 1891 return r; 1892 } 1893 1894 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1895 1896 } else if (adev->firmware.load_type == 1897 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1898 1899 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1900 } 1901 1902 mes_v12_1_enable(adev, true, xcc_id); 1903 } 1904 1905 /* Enable the MES to handle doorbell ring on unmapped queue */ 1906 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id); 1907 1908 r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id); 1909 if (r) 1910 goto failure; 1911 1912 r = mes_v12_1_set_hw_resources(&adev->mes, 1913 AMDGPU_MES_SCHED_PIPE, xcc_id); 1914 if (r) 1915 goto failure; 1916 1917 if (adev->enable_uni_mes) { 1918 mes_v12_1_set_hw_resources_1(&adev->mes, 1919 AMDGPU_MES_SCHED_PIPE, xcc_id); 1920 } 1921 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); 1922 1923 r = mes_v12_1_query_sched_status(&adev->mes, 1924 AMDGPU_MES_SCHED_PIPE, xcc_id); 1925 if (r) { 1926 DRM_ERROR("MES is busy\n"); 1927 goto failure; 1928 } 1929 1930 amdgpu_mes_validate_fw_version(adev); 1931 out: 1932 /* 1933 * Disable KIQ ring usage from the driver once MES is enabled. 1934 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1935 * with MES enabled. 1936 */ 1937 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1938 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true; 1939 1940 return 0; 1941 1942 failure: 1943 mes_v12_1_hw_fini(ip_block); 1944 return r; 1945 } 1946 1947 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 1948 { 1949 struct amdgpu_device *adev = ip_block->adev; 1950 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1951 1952 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1953 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1954 if (r) 1955 return r; 1956 } 1957 1958 return 0; 1959 } 1960 1961 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 1962 { 1963 return 0; 1964 } 1965 1966 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) 1967 { 1968 return mes_v12_1_hw_fini(ip_block); 1969 } 1970 1971 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) 1972 { 1973 return mes_v12_1_hw_init(ip_block); 1974 } 1975 1976 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) 1977 { 1978 struct amdgpu_device *adev = ip_block->adev; 1979 int pipe, r; 1980 1981 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1982 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 1983 1984 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1985 r = amdgpu_mes_init_microcode(adev, pipe); 1986 if (r) 1987 return r; 1988 } 1989 1990 return 0; 1991 } 1992 1993 static int mes_v12_1_late_init(struct amdgpu_ip_block *ip_block) 1994 { 1995 struct amdgpu_device *adev = ip_block->adev; 1996 int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1997 1998 /* TODO: remove it if issue fixed. */ 1999 if (adev->mes.enable_coop_mode) 2000 return 0; 2001 2002 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 2003 /* for COOP mode, only test master xcc. */ 2004 if (adev->mes.enable_coop_mode && 2005 adev->mes.master_xcc_ids[xcc_id] != xcc_id) 2006 continue; 2007 2008 mes_v12_1_self_test(adev, xcc_id); 2009 } 2010 2011 return 0; 2012 } 2013 2014 static const struct amd_ip_funcs mes_v12_1_ip_funcs = { 2015 .name = "mes_v12_1", 2016 .early_init = mes_v12_1_early_init, 2017 .late_init = mes_v12_1_late_init, 2018 .sw_init = mes_v12_1_sw_init, 2019 .sw_fini = mes_v12_1_sw_fini, 2020 .hw_init = mes_v12_1_hw_init, 2021 .hw_fini = mes_v12_1_hw_fini, 2022 .suspend = mes_v12_1_suspend, 2023 .resume = mes_v12_1_resume, 2024 }; 2025 2026 const struct amdgpu_ip_block_version mes_v12_1_ip_block = { 2027 .type = AMD_IP_BLOCK_TYPE_MES, 2028 .major = 12, 2029 .minor = 1, 2030 .rev = 0, 2031 .funcs = &mes_v12_1_ip_funcs, 2032 }; 2033 2034 static int mes_v12_1_alloc_test_buf(struct amdgpu_device *adev, 2035 struct amdgpu_bo **bo, uint64_t *addr, 2036 void **ptr, int size) 2037 { 2038 amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2039 bo, addr, ptr); 2040 if (!*bo) { 2041 dev_err(adev->dev, "failed to allocate test buffer bo\n"); 2042 return -ENOMEM; 2043 } 2044 memset(*ptr, 0, size); 2045 return 0; 2046 } 2047 2048 static int mes_v12_1_map_test_bo(struct amdgpu_device *adev, 2049 struct amdgpu_bo *bo, struct amdgpu_vm *vm, 2050 struct amdgpu_bo_va **bo_va, u64 va, int size) 2051 { 2052 struct amdgpu_sync sync; 2053 int r; 2054 2055 r = amdgpu_map_static_csa(adev, vm, bo, bo_va, va, size); 2056 if (r) 2057 return r; 2058 2059 amdgpu_sync_create(&sync); 2060 2061 r = amdgpu_vm_bo_update(adev, *bo_va, false); 2062 if (r) { 2063 dev_err(adev->dev, "failed to do vm_bo_update on meta data\n"); 2064 goto error; 2065 } 2066 amdgpu_sync_fence(&sync, (*bo_va)->last_pt_update, GFP_KERNEL); 2067 2068 r = amdgpu_vm_update_pdes(adev, vm, false); 2069 if (r) { 2070 dev_err(adev->dev, "failed to update pdes on meta data\n"); 2071 goto error; 2072 } 2073 amdgpu_sync_fence(&sync, vm->last_update, GFP_KERNEL); 2074 amdgpu_sync_wait(&sync, false); 2075 2076 error: 2077 amdgpu_sync_free(&sync); 2078 return r; 2079 } 2080 2081 static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id, 2082 u32 *queue_ptr, u64 fence_gpu_addr, 2083 void *fence_cpu_ptr, void *wptr_cpu_addr, 2084 u64 doorbell_idx, int queue_type) 2085 { 2086 volatile uint32_t *cpu_ptr = fence_cpu_ptr; 2087 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2088 int sdma_ring_align = 0x10, compute_ring_align = 0x100; 2089 uint32_t tmp, xcc_offset; 2090 int r = 0, i, j, wptr = 0; 2091 2092 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 2093 if (!adev->mes.enable_coop_mode) { 2094 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2095 regSCRATCH_REG0, 0xCAFEDEAD); 2096 } else { 2097 for (i = 0; i < num_xcc; i++) { 2098 if (adev->mes.master_xcc_ids[i] == xcc_id) 2099 WREG32_SOC15(GC, GET_INST(GC, i), 2100 regSCRATCH_REG0, 0xCAFEDEAD); 2101 } 2102 } 2103 2104 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 2105 queue_ptr[wptr++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2106 queue_ptr[wptr++] = xcc_offset - PACKET3_SET_UCONFIG_REG_START; 2107 queue_ptr[wptr++] = 0xDEADBEEF; 2108 2109 for (i = wptr; i < compute_ring_align; i++) 2110 queue_ptr[wptr++] = PACKET3(PACKET3_NOP, 0x3FFF); 2111 2112 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 2113 *cpu_ptr = 0xCAFEDEAD; 2114 2115 queue_ptr[wptr++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 2116 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 2117 queue_ptr[wptr++] = lower_32_bits(fence_gpu_addr); 2118 queue_ptr[wptr++] = upper_32_bits(fence_gpu_addr); 2119 queue_ptr[wptr++] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 2120 queue_ptr[wptr++] = 0xDEADBEEF; 2121 2122 for (i = wptr; i < sdma_ring_align; i++) 2123 queue_ptr[wptr++] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 2124 2125 wptr <<= 2; 2126 } 2127 2128 atomic64_set((atomic64_t *)wptr_cpu_addr, wptr); 2129 WDOORBELL64(doorbell_idx, wptr); 2130 2131 for (i = 0; i < adev->usec_timeout; i++) { 2132 if (queue_type == AMDGPU_RING_TYPE_SDMA) { 2133 tmp = le32_to_cpu(*cpu_ptr); 2134 } else { 2135 if (!adev->mes.enable_coop_mode) { 2136 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2137 regSCRATCH_REG0); 2138 } else { 2139 for (j = 0; j < num_xcc; j++) { 2140 if (xcc_id != adev->mes.master_xcc_ids[j]) 2141 continue; 2142 2143 tmp = RREG32_SOC15(GC, GET_INST(GC, j), 2144 regSCRATCH_REG0); 2145 if (tmp != 0xDEADBEEF) 2146 break; 2147 } 2148 } 2149 } 2150 2151 if (tmp == 0xDEADBEEF) 2152 break; 2153 2154 if (amdgpu_emu_mode == 1) 2155 msleep(1); 2156 else 2157 udelay(1); 2158 } 2159 2160 if (i >= adev->usec_timeout) { 2161 dev_err(adev->dev, "xcc%d: mes self test (%s) failed\n", xcc_id, 2162 queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); 2163 2164 while (halt_if_hws_hang) 2165 schedule(); 2166 2167 r = -ETIMEDOUT; 2168 } else { 2169 dev_info(adev->dev, "xcc%d: mes self test (%s) pass\n", xcc_id, 2170 queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); 2171 } 2172 2173 return r; 2174 } 2175 2176 #define USER_CTX_SIZE (PAGE_SIZE * 2) 2177 #define USER_CTX_VA AMDGPU_VA_RESERVED_BOTTOM 2178 #define RING_OFFSET(addr) ((addr)) 2179 #define EOP_OFFSET(addr) ((addr) + PAGE_SIZE) 2180 #define WPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64)) 2181 #define RPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 2) 2182 #define FENCE_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 3) 2183 2184 static int mes_v12_1_test_queue(struct amdgpu_device *adev, int xcc_id, 2185 int pasid, struct amdgpu_vm *vm, u64 meta_gpu_addr, 2186 u64 queue_gpu_addr, void *ctx_ptr, int queue_type) 2187 { 2188 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 2189 struct amdgpu_mqd *mqd_mgr = &adev->mqds[queue_type]; 2190 struct amdgpu_mqd_prop mqd_prop = {0}; 2191 struct mes_add_queue_input add_queue = {0}; 2192 struct mes_remove_queue_input remove_queue = {0}; 2193 struct amdgpu_bo *mqd_bo = NULL; 2194 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2195 int i, r, off, mqd_size, mqd_count = 1; 2196 void *mqd_ptr = NULL; 2197 u64 mqd_gpu_addr, doorbell_idx; 2198 2199 /* extra one page size padding for mes fw */ 2200 mqd_size = mqd_mgr->mqd_size + PAGE_SIZE; 2201 2202 if (queue_type == AMDGPU_RING_TYPE_SDMA) { 2203 doorbell_idx = adev->mes.db_start_dw_offset + \ 2204 adev->doorbell_index.sdma_engine[0]; 2205 } else { 2206 doorbell_idx = adev->mes.db_start_dw_offset + \ 2207 adev->doorbell_index.userqueue_start; 2208 } 2209 2210 if (adev->mes.enable_coop_mode && 2211 queue_type == AMDGPU_RING_TYPE_COMPUTE) { 2212 for (i = 0, mqd_count = 0; i < num_xcc; i++) { 2213 if (adev->mes.master_xcc_ids[i] == xcc_id) 2214 mqd_count++; 2215 } 2216 mqd_size *= mqd_count; 2217 } 2218 2219 r = mes_v12_1_alloc_test_buf(adev, &mqd_bo, &mqd_gpu_addr, 2220 &mqd_ptr, mqd_size * mqd_count); 2221 if (r < 0) 2222 return r; 2223 2224 mqd_prop.mqd_gpu_addr = mqd_gpu_addr; 2225 mqd_prop.hqd_base_gpu_addr = RING_OFFSET(USER_CTX_VA); 2226 mqd_prop.eop_gpu_addr = EOP_OFFSET(USER_CTX_VA); 2227 mqd_prop.wptr_gpu_addr = WPTR_OFFSET(USER_CTX_VA); 2228 mqd_prop.rptr_gpu_addr = RPTR_OFFSET(USER_CTX_VA); 2229 mqd_prop.doorbell_index = doorbell_idx; 2230 mqd_prop.queue_size = PAGE_SIZE; 2231 mqd_prop.mqd_stride_size = mqd_size; 2232 mqd_prop.use_doorbell = true; 2233 mqd_prop.hqd_active = false; 2234 2235 mqd_mgr->init_mqd(adev, mqd_ptr, &mqd_prop); 2236 if (mqd_count > 1) { 2237 for (i = 1; i < mqd_count; i++) { 2238 off = mqd_size * i; 2239 mqd_prop.mqd_gpu_addr = mqd_gpu_addr + off; 2240 mqd_mgr->init_mqd(adev, (char *)mqd_ptr + off, 2241 &mqd_prop); 2242 } 2243 } 2244 2245 add_queue.xcc_id = xcc_id; 2246 add_queue.process_id = pasid; 2247 add_queue.page_table_base_addr = adev->vm_manager.vram_base_offset + 2248 amdgpu_bo_gpu_offset(vm->root.bo) - adev->gmc.vram_start; 2249 add_queue.process_va_start = 0; 2250 add_queue.process_va_end = adev->vm_manager.max_pfn - 1; 2251 add_queue.process_context_addr = meta_gpu_addr; 2252 add_queue.gang_context_addr = meta_gpu_addr + AMDGPU_MES_PROC_CTX_SIZE; 2253 add_queue.doorbell_offset = doorbell_idx; 2254 add_queue.mqd_addr = mqd_gpu_addr; 2255 add_queue.wptr_addr = mqd_prop.wptr_gpu_addr; 2256 add_queue.wptr_mc_addr = WPTR_OFFSET(queue_gpu_addr); 2257 add_queue.queue_type = queue_type; 2258 add_queue.vm_cntx_cntl = hub->vm_cntx_cntl; 2259 2260 r = mes_v12_1_add_hw_queue(&adev->mes, &add_queue); 2261 if (r) 2262 goto error; 2263 2264 mes_v12_1_test_ring(adev, xcc_id, (u32 *)RING_OFFSET((char *)ctx_ptr), 2265 FENCE_OFFSET(USER_CTX_VA), 2266 FENCE_OFFSET((char *)ctx_ptr), 2267 WPTR_OFFSET((char *)ctx_ptr), 2268 doorbell_idx, queue_type); 2269 2270 remove_queue.xcc_id = xcc_id; 2271 remove_queue.doorbell_offset = doorbell_idx; 2272 remove_queue.gang_context_addr = add_queue.gang_context_addr; 2273 r = mes_v12_1_remove_hw_queue(&adev->mes, &remove_queue); 2274 2275 error: 2276 amdgpu_bo_free_kernel(&mqd_bo, &mqd_gpu_addr, &mqd_ptr); 2277 return r; 2278 } 2279 2280 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id) 2281 { 2282 int queue_types[] = { AMDGPU_RING_TYPE_COMPUTE, 2283 /* AMDGPU_RING_TYPE_SDMA */ }; 2284 struct amdgpu_bo_va *bo_va = NULL; 2285 struct amdgpu_vm *vm = NULL; 2286 struct amdgpu_bo *meta_bo = NULL, *ctx_bo = NULL; 2287 void *meta_ptr = NULL, *ctx_ptr = NULL; 2288 u64 meta_gpu_addr, ctx_gpu_addr; 2289 int size, i, r, pasid; 2290 2291 pasid = amdgpu_pasid_alloc(16); 2292 if (pasid < 0) 2293 pasid = 0; 2294 2295 size = AMDGPU_MES_PROC_CTX_SIZE + AMDGPU_MES_GANG_CTX_SIZE; 2296 r = mes_v12_1_alloc_test_buf(adev, &meta_bo, &meta_gpu_addr, 2297 &meta_ptr, size); 2298 if (r < 0) 2299 goto err2; 2300 2301 r = mes_v12_1_alloc_test_buf(adev, &ctx_bo, &ctx_gpu_addr, 2302 &ctx_ptr, USER_CTX_SIZE); 2303 if (r < 0) 2304 goto err2; 2305 2306 vm = kzalloc(sizeof(*vm), GFP_KERNEL); 2307 if (!vm) { 2308 r = -ENOMEM; 2309 goto err2; 2310 } 2311 2312 r = amdgpu_vm_init(adev, vm, -1, pasid); 2313 if (r) 2314 goto err1; 2315 2316 r = mes_v12_1_map_test_bo(adev, ctx_bo, vm, &bo_va, 2317 USER_CTX_VA, USER_CTX_SIZE); 2318 if (r) 2319 goto err0; 2320 2321 for (i = 0; i < ARRAY_SIZE(queue_types); i++) { 2322 memset(ctx_ptr, 0, USER_CTX_SIZE); 2323 2324 r = mes_v12_1_test_queue(adev, xcc_id, pasid, vm, meta_gpu_addr, 2325 ctx_gpu_addr, ctx_ptr, queue_types[i]); 2326 if (r) 2327 break; 2328 } 2329 2330 amdgpu_unmap_static_csa(adev, vm, ctx_bo, bo_va, USER_CTX_VA); 2331 err0: 2332 amdgpu_vm_fini(adev, vm); 2333 err1: 2334 kfree(vm); 2335 err2: 2336 amdgpu_bo_free_kernel(&meta_bo, &meta_gpu_addr, &meta_ptr); 2337 amdgpu_bo_free_kernel(&ctx_bo, &ctx_gpu_addr, &ctx_ptr); 2338 amdgpu_pasid_free(pasid); 2339 return r; 2340 } 2341 2342