1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc_v1_0.h" 29 #include "gc/gc_12_1_0_offset.h" 30 #include "gc/gc_12_1_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin"); 38 39 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block); 40 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id); 41 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); 42 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 43 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 44 45 #define MES_EOP_SIZE 2048 46 47 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 48 #define XCC_MID_MASK 0x41000000 49 50 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v12_1_ring_get_rptr, 85 .get_wptr = mes_v12_1_ring_get_wptr, 86 .set_wptr = mes_v12_1_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static const char *mes_v12_1_opcodes[] = { 91 "SET_HW_RSRC", 92 "SET_SCHEDULING_CONFIG", 93 "ADD_QUEUE", 94 "REMOVE_QUEUE", 95 "PERFORM_YIELD", 96 "SET_GANG_PRIORITY_LEVEL", 97 "SUSPEND", 98 "RESUME", 99 "RESET", 100 "SET_LOG_BUFFER", 101 "CHANGE_GANG_PRORITY", 102 "QUERY_SCHEDULER_STATUS", 103 "unused", 104 "SET_DEBUG_VMID", 105 "MISC", 106 "UPDATE_ROOT_PAGE_TABLE", 107 "AMD_LOG", 108 "SET_SE_MODE", 109 "SET_GANG_SUBMIT", 110 "SET_HW_RSRC_1", 111 "INVALIDATE_TLBS", 112 }; 113 114 static const char *mes_v12_1_misc_opcodes[] = { 115 "WRITE_REG", 116 "INV_GART", 117 "QUERY_STATUS", 118 "READ_REG", 119 "WAIT_REG_MEM", 120 "SET_SHADER_DEBUGGER", 121 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 122 "NOTIFY_TO_UNMAP_PROCESSES", 123 }; 124 125 static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt) 126 { 127 const char *op_str = NULL; 128 129 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes)) 130 op_str = mes_v12_1_opcodes[x_pkt->header.opcode]; 131 132 return op_str; 133 } 134 135 static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt) 136 { 137 const char *op_str = NULL; 138 139 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 140 (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes))) 141 op_str = mes_v12_1_misc_opcodes[x_pkt->opcode]; 142 143 return op_str; 144 } 145 146 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 147 int xcc_id, int pipe, void *pkt, 148 int size, int api_status_off) 149 { 150 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 151 signed long timeout = 2100000; /* 2100 ms */ 152 struct amdgpu_device *adev = mes->adev; 153 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; 154 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; 155 struct MES_API_STATUS *api_status; 156 union MESAPI__MISC *x_pkt = pkt; 157 const char *op_str, *misc_op_str; 158 unsigned long flags; 159 u64 status_gpu_addr; 160 u32 seq, status_offset; 161 u64 *status_ptr; 162 signed long r; 163 int ret; 164 165 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 166 return -EINVAL; 167 168 if (amdgpu_emu_mode) { 169 timeout *= 1000; 170 } else if (amdgpu_sriov_vf(adev)) { 171 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 172 timeout = 15 * 600 * 1000; 173 } 174 175 ret = amdgpu_device_wb_get(adev, &status_offset); 176 if (ret) 177 return ret; 178 179 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 180 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 181 *status_ptr = 0; 182 183 spin_lock_irqsave(ring_lock, flags); 184 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 185 if (r) 186 goto error_unlock_free; 187 188 seq = ++ring->fence_drv.sync_seq; 189 r = amdgpu_fence_wait_polling(ring, 190 seq - ring->fence_drv.num_fences_mask, 191 timeout); 192 if (r < 1) 193 goto error_undo; 194 195 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 196 api_status->api_completion_fence_addr = status_gpu_addr; 197 api_status->api_completion_fence_value = 1; 198 199 amdgpu_ring_write_multiple(ring, pkt, size / 4); 200 201 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 202 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 203 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 204 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 205 mes_status_pkt.api_status.api_completion_fence_addr = 206 ring->fence_drv.gpu_addr; 207 mes_status_pkt.api_status.api_completion_fence_value = seq; 208 209 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 210 sizeof(mes_status_pkt) / 4); 211 212 amdgpu_ring_commit(ring); 213 spin_unlock_irqrestore(ring_lock, flags); 214 215 op_str = mes_v12_1_get_op_string(x_pkt); 216 misc_op_str = mes_v12_1_get_misc_op_string(x_pkt); 217 218 if (misc_op_str) 219 dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n", 220 xcc_id, pipe, op_str, misc_op_str); 221 else if (op_str) 222 dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n", 223 xcc_id, pipe, op_str); 224 else 225 dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n", 226 xcc_id, pipe, x_pkt->header.opcode); 227 228 r = amdgpu_fence_wait_polling(ring, seq, timeout); 229 if (r < 1 || !*status_ptr) { 230 if (misc_op_str) 231 dev_err(adev->dev, 232 "MES(%d, %d) failed to respond to msg=%s (%s)\n", 233 xcc_id, pipe, op_str, misc_op_str); 234 else if (op_str) 235 dev_err(adev->dev, 236 "MES(%d, %d) failed to respond to msg=%s\n", 237 xcc_id, pipe, op_str); 238 else 239 dev_err(adev->dev, 240 "MES(%d, %d) failed to respond to msg=%d\n", 241 xcc_id, pipe, x_pkt->header.opcode); 242 243 while (halt_if_hws_hang) 244 schedule(); 245 246 r = -ETIMEDOUT; 247 goto error_wb_free; 248 } 249 250 amdgpu_device_wb_free(adev, status_offset); 251 return 0; 252 253 error_undo: 254 dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe); 255 amdgpu_ring_undo(ring); 256 257 error_unlock_free: 258 spin_unlock_irqrestore(ring_lock, flags); 259 260 error_wb_free: 261 amdgpu_device_wb_free(adev, status_offset); 262 return r; 263 } 264 265 static int convert_to_mes_queue_type(int queue_type) 266 { 267 if (queue_type == AMDGPU_RING_TYPE_GFX) 268 return MES_QUEUE_TYPE_GFX; 269 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 270 return MES_QUEUE_TYPE_COMPUTE; 271 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 272 return MES_QUEUE_TYPE_SDMA; 273 else if (queue_type == AMDGPU_RING_TYPE_MES) 274 return MES_QUEUE_TYPE_SCHQ; 275 else 276 BUG(); 277 return -1; 278 } 279 280 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, 281 struct mes_add_queue_input *input) 282 { 283 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 284 int xcc_id = input->xcc_id; 285 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 286 287 if (mes->enable_coop_mode) 288 xcc_id = mes->master_xcc_ids[inst]; 289 290 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 291 292 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 293 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 294 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 295 296 mes_add_queue_pkt.process_id = input->process_id; 297 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 298 mes_add_queue_pkt.process_va_start = input->process_va_start; 299 mes_add_queue_pkt.process_va_end = input->process_va_end; 300 mes_add_queue_pkt.process_quantum = input->process_quantum; 301 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 302 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 303 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 304 mes_add_queue_pkt.inprocess_gang_priority = 305 input->inprocess_gang_priority; 306 mes_add_queue_pkt.gang_global_priority_level = 307 input->gang_global_priority_level; 308 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 309 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 310 311 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 312 313 mes_add_queue_pkt.queue_type = 314 convert_to_mes_queue_type(input->queue_type); 315 mes_add_queue_pkt.paging = input->paging; 316 mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl; 317 mes_add_queue_pkt.gws_base = input->gws_base; 318 mes_add_queue_pkt.gws_size = input->gws_size; 319 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 320 mes_add_queue_pkt.tma_addr = input->tma_addr; 321 mes_add_queue_pkt.trap_en = input->trap_en; 322 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 323 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 324 325 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 326 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 327 mes_add_queue_pkt.gds_size = input->queue_size; 328 329 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 330 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 331 mes_add_queue_pkt.gds_size = input->queue_size; 332 333 mes_add_queue_pkt.full_sh_mem_config_data = input->sh_mem_config_data; 334 335 return mes_v12_1_submit_pkt_and_poll_completion(mes, 336 xcc_id, AMDGPU_MES_SCHED_PIPE, 337 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 338 offsetof(union MESAPI__ADD_QUEUE, api_status)); 339 } 340 341 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, 342 struct mes_remove_queue_input *input) 343 { 344 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 345 int xcc_id = input->xcc_id; 346 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 347 348 if (mes->enable_coop_mode) 349 xcc_id = mes->master_xcc_ids[inst]; 350 351 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 352 353 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 354 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 355 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 356 357 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 358 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 359 360 return mes_v12_1_submit_pkt_and_poll_completion(mes, 361 xcc_id, AMDGPU_MES_SCHED_PIPE, 362 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 363 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 364 } 365 366 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, 367 struct mes_reset_queue_input *input) 368 { 369 union MESAPI__RESET mes_reset_queue_pkt; 370 int pipe; 371 372 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 373 374 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 375 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 376 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 377 378 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 379 /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ 380 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 381 382 if (mes->adev->enable_uni_mes) 383 pipe = AMDGPU_MES_KIQ_PIPE; 384 else 385 pipe = AMDGPU_MES_SCHED_PIPE; 386 387 return mes_v12_1_submit_pkt_and_poll_completion(mes, 388 input->xcc_id, pipe, 389 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 390 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 391 } 392 393 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, 394 struct mes_map_legacy_queue_input *input) 395 { 396 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 397 int pipe; 398 399 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 400 401 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 402 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 403 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 404 405 mes_add_queue_pkt.pipe_id = input->pipe_id; 406 mes_add_queue_pkt.queue_id = input->queue_id; 407 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 408 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 409 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 410 mes_add_queue_pkt.queue_type = 411 convert_to_mes_queue_type(input->queue_type); 412 mes_add_queue_pkt.map_legacy_kq = 1; 413 414 if (mes->adev->enable_uni_mes) 415 pipe = AMDGPU_MES_KIQ_PIPE; 416 else 417 pipe = AMDGPU_MES_SCHED_PIPE; 418 419 return mes_v12_1_submit_pkt_and_poll_completion(mes, 420 input->xcc_id, pipe, 421 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 422 offsetof(union MESAPI__ADD_QUEUE, api_status)); 423 } 424 425 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, 426 struct mes_unmap_legacy_queue_input *input) 427 { 428 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 429 int pipe; 430 431 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 432 433 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 434 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 435 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 436 437 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 438 mes_remove_queue_pkt.gang_context_addr = 0; 439 440 mes_remove_queue_pkt.pipe_id = input->pipe_id; 441 mes_remove_queue_pkt.queue_id = input->queue_id; 442 443 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 444 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 445 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 446 mes_remove_queue_pkt.tf_data = 447 lower_32_bits(input->trail_fence_data); 448 } else { 449 mes_remove_queue_pkt.unmap_legacy_queue = 1; 450 mes_remove_queue_pkt.queue_type = 451 convert_to_mes_queue_type(input->queue_type); 452 } 453 454 if (mes->adev->enable_uni_mes) 455 pipe = AMDGPU_MES_KIQ_PIPE; 456 else 457 pipe = AMDGPU_MES_SCHED_PIPE; 458 459 return mes_v12_1_submit_pkt_and_poll_completion(mes, 460 input->xcc_id, pipe, 461 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 462 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 463 } 464 465 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, 466 struct mes_suspend_gang_input *input) 467 { 468 return 0; 469 } 470 471 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, 472 struct mes_resume_gang_input *input) 473 { 474 return 0; 475 } 476 477 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, 478 int pipe, int xcc_id) 479 { 480 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 481 482 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 483 484 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 485 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 486 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 487 488 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 489 &mes_status_pkt, sizeof(mes_status_pkt), 490 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 491 } 492 static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) 493 { 494 /* Check xcc reg offset range */ 495 uint32_t xcc = (reg_offset & XCC_MID_MASK) ? 4 : 0; 496 /* Each XCC has two register ranges. 497 * These are represented in reg_offset[17:16] 498 */ 499 return ((reg_offset >> 16) & 0x3) + xcc; 500 } 501 502 static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, 503 struct RRMT_OPTION *rrmt_opt) 504 { 505 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 506 507 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) { 508 rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg); 509 rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? 510 MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; 511 } else { 512 rrmt_opt->mode = MES_RRMT_MODE_LOCAL_REMOTE_AID; 513 } 514 } 515 516 static int mes_v12_1_misc_op(struct amdgpu_mes *mes, 517 struct mes_misc_op_input *input) 518 { 519 struct amdgpu_device *adev = mes->adev; 520 union MESAPI__MISC misc_pkt; 521 int pipe; 522 523 if (mes->adev->enable_uni_mes) 524 pipe = AMDGPU_MES_KIQ_PIPE; 525 else 526 pipe = AMDGPU_MES_SCHED_PIPE; 527 528 memset(&misc_pkt, 0, sizeof(misc_pkt)); 529 530 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 531 misc_pkt.header.opcode = MES_SCH_API_MISC; 532 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 533 534 switch (input->op) { 535 case MES_MISC_OP_READ_REG: 536 misc_pkt.opcode = MESAPI_MISC__READ_REG; 537 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 538 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 539 mes_v12_1_get_rrmt(input->read_reg.reg_offset, 540 GET_INST(GC, input->xcc_id), 541 &misc_pkt.read_reg.rrmt_opt); 542 if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) { 543 misc_pkt.read_reg.reg_offset = 544 soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset); 545 } 546 break; 547 case MES_MISC_OP_WRITE_REG: 548 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 549 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 550 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 551 mes_v12_1_get_rrmt(input->write_reg.reg_offset, 552 GET_INST(GC, input->xcc_id), 553 &misc_pkt.write_reg.rrmt_opt); 554 if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) { 555 misc_pkt.write_reg.reg_offset = 556 soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset); 557 } 558 break; 559 case MES_MISC_OP_WRM_REG_WAIT: 560 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 561 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 562 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 563 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 564 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 565 misc_pkt.wait_reg_mem.reg_offset2 = 0; 566 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 567 GET_INST(GC, input->xcc_id), 568 &misc_pkt.wait_reg_mem.rrmt_opt1); 569 if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { 570 misc_pkt.wait_reg_mem.reg_offset1 = 571 soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1); 572 } 573 break; 574 case MES_MISC_OP_WRM_REG_WR_WAIT: 575 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 576 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 577 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 578 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 579 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 580 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 581 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 582 GET_INST(GC, input->xcc_id), 583 &misc_pkt.wait_reg_mem.rrmt_opt1); 584 mes_v12_1_get_rrmt(input->wrm_reg.reg1, 585 GET_INST(GC, input->xcc_id), 586 &misc_pkt.wait_reg_mem.rrmt_opt2); 587 588 if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { 589 misc_pkt.wait_reg_mem.reg_offset1 = 590 soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1); 591 } 592 if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) { 593 misc_pkt.wait_reg_mem.reg_offset2 = 594 soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2); 595 } 596 break; 597 case MES_MISC_OP_SET_SHADER_DEBUGGER: 598 pipe = AMDGPU_MES_SCHED_PIPE; 599 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 600 misc_pkt.set_shader_debugger.process_context_addr = 601 input->set_shader_debugger.process_context_addr; 602 misc_pkt.set_shader_debugger.flags.u32all = 603 input->set_shader_debugger.flags.u32all; 604 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 605 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 606 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 607 input->set_shader_debugger.tcp_watch_cntl, 608 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 609 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 610 break; 611 case MES_MISC_OP_CHANGE_CONFIG: 612 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 613 misc_pkt.change_config.opcode = 614 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 615 misc_pkt.change_config.option.bits.limit_single_process = 616 input->change_config.option.limit_single_process; 617 break; 618 default: 619 DRM_ERROR("unsupported misc op (%d) \n", input->op); 620 return -EINVAL; 621 } 622 623 return mes_v12_1_submit_pkt_and_poll_completion(mes, 624 input->xcc_id, pipe, 625 &misc_pkt, sizeof(misc_pkt), 626 offsetof(union MESAPI__MISC, api_status)); 627 } 628 629 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, 630 int pipe, int xcc_id) 631 { 632 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 633 int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); 634 635 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 636 637 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 638 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 639 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 640 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 641 642 if (mes->enable_coop_mode && pipe == AMDGPU_MES_SCHED_PIPE) { 643 master_xcc_id = mes->master_xcc_ids[inst]; 644 mes_set_hw_res_1_pkt.mes_coop_mode = 1; 645 mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = 646 mes->shared_cmd_buf_gpu_addr[master_xcc_id]; 647 } 648 649 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 650 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 651 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 652 } 653 654 static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt) 655 { 656 /* 657 * GFX V12 has only one GFX pipe, but 8 queues in it. 658 * GFX pipe 0 queue 0 is being used by Kernel queue. 659 * Set GFX pipe 0 queue 1-7 for MES scheduling 660 * mask = 1111 1110b 661 */ 662 pkt->gfx_hqd_mask[0] = 0xFE; 663 } 664 665 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, 666 int pipe, int xcc_id) 667 { 668 int i; 669 struct amdgpu_device *adev = mes->adev; 670 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 671 672 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 673 674 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 675 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 676 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 677 678 if (pipe == AMDGPU_MES_SCHED_PIPE) { 679 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 680 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 681 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 682 mes_set_hw_res_pkt.paging_vmid = 0; 683 684 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 685 mes_set_hw_res_pkt.compute_hqd_mask[i] = 686 mes->compute_hqd_mask[i]; 687 688 mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt); 689 690 for (i = 0; i < MAX_SDMA_PIPES; i++) 691 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 692 mes->sdma_hqd_mask[i]; 693 694 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 695 mes_set_hw_res_pkt.aggregated_doorbells[i] = 696 mes->aggregated_doorbells[i]; 697 } 698 699 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 700 mes->sch_ctx_gpu_addr[pipe]; 701 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 702 mes->query_status_fence_gpu_addr[pipe]; 703 704 for (i = 0; i < 5; i++) { 705 mes_set_hw_res_pkt.gc_base[i] = 706 adev->reg_offset[GC_HWIP][0][i]; 707 mes_set_hw_res_pkt.mmhub_base[i] = 708 adev->reg_offset[MMHUB_HWIP][0][i]; 709 mes_set_hw_res_pkt.osssys_base[i] = 710 adev->reg_offset[OSSSYS_HWIP][0][i]; 711 } 712 713 mes_set_hw_res_pkt.disable_reset = 1; 714 mes_set_hw_res_pkt.disable_mes_log = 1; 715 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 716 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 717 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 718 719 /* 720 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 721 * handling support, other queue will not use the oversubscribe timer. 722 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 723 */ 724 mes_set_hw_res_pkt.oversubscription_timer = 50; 725 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 726 727 if (amdgpu_mes_log_enable) { 728 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 729 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 730 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE; 731 } 732 733 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 734 mes_set_hw_res_pkt.limit_single_process = 1; 735 736 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 737 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 738 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 739 } 740 741 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, 742 int xcc_id) 743 { 744 struct amdgpu_device *adev = mes->adev; 745 uint32_t data; 746 747 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1); 748 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 749 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 750 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 751 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 752 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 753 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 754 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data); 755 756 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2); 757 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 758 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 759 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 760 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 761 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 762 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 763 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data); 764 765 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3); 766 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 767 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 768 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 769 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 770 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 771 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 772 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data); 773 774 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4); 775 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 776 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 777 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 778 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 779 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 780 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 781 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data); 782 783 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5); 784 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 785 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 786 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 787 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 788 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 789 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 790 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data); 791 792 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 793 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data); 794 } 795 796 797 static void mes_v12_1_enable_unmapped_doorbell_handling( 798 struct amdgpu_mes *mes, bool enable, int xcc_id) 799 { 800 struct amdgpu_device *adev = mes->adev; 801 uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL); 802 803 /* 804 * The default PROC_LSB settng is 0xc which means doorbell 805 * addr[16:12] gives the doorbell page number. For kfd, each 806 * process will use 2 pages of doorbell, we need to change the 807 * setting to 0xd 808 */ 809 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 810 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 811 812 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 813 814 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data); 815 } 816 817 #if 0 818 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, 819 struct mes_reset_legacy_queue_input *input) 820 { 821 union MESAPI__RESET mes_reset_queue_pkt; 822 int pipe; 823 824 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 825 826 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 827 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 828 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 829 830 mes_reset_queue_pkt.queue_type = 831 convert_to_mes_queue_type(input->queue_type); 832 833 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 834 mes_reset_queue_pkt.reset_legacy_gfx = 1; 835 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 836 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 837 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 838 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 839 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 840 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 841 } else { 842 mes_reset_queue_pkt.reset_queue_only = 1; 843 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 844 } 845 846 if (mes->adev->enable_uni_mes) 847 pipe = AMDGPU_MES_KIQ_PIPE; 848 else 849 pipe = AMDGPU_MES_SCHED_PIPE; 850 851 return mes_v12_1_submit_pkt_and_poll_completion(mes, 852 input->xcc_id, pipe, 853 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 854 offsetof(union MESAPI__RESET, api_status)); 855 } 856 #endif 857 858 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 859 { 860 /* 861 * MES doesn't support invalidate gc_hub on slave xcc individually 862 * master xcc will invalidate all gc_hub for the partition 863 */ 864 if (AMDGPU_IS_GFXHUB(id)) 865 return 0; 866 else if (AMDGPU_IS_MMHUB0(id)) 867 return 1; 868 else if (AMDGPU_IS_MMHUB1(id)) 869 return 2; 870 return -EINVAL; 871 872 } 873 874 static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes, 875 struct mes_inv_tlbs_pasid_input *input) 876 { 877 union MESAPI__INV_TLBS mes_inv_tlbs; 878 int xcc_id = input->xcc_id; 879 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 880 int ret; 881 882 if (mes->enable_coop_mode) 883 xcc_id = mes->master_xcc_ids[inst]; 884 885 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 886 887 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 888 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 889 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 890 891 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 892 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 893 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 894 895 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 896 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 897 if (ret < 0) 898 return -EINVAL; 899 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 900 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE, 901 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 902 offsetof(union MESAPI__INV_TLBS, api_status)); 903 904 } 905 906 static const struct amdgpu_mes_funcs mes_v12_1_funcs = { 907 .add_hw_queue = mes_v12_1_add_hw_queue, 908 .remove_hw_queue = mes_v12_1_remove_hw_queue, 909 .map_legacy_queue = mes_v12_1_map_legacy_queue, 910 .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue, 911 .suspend_gang = mes_v12_1_suspend_gang, 912 .resume_gang = mes_v12_1_resume_gang, 913 .misc_op = mes_v12_1_misc_op, 914 .reset_hw_queue = mes_v12_1_reset_hw_queue, 915 .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, 916 }; 917 918 static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev, 919 enum amdgpu_mes_pipe pipe, 920 int xcc_id) 921 { 922 int r, inst = MES_PIPE_INST(xcc_id, pipe); 923 const struct mes_firmware_header_v1_0 *mes_hdr; 924 const __le32 *fw_data; 925 unsigned fw_size; 926 927 mes_hdr = (const struct mes_firmware_header_v1_0 *) 928 adev->mes.fw[pipe]->data; 929 930 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 931 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 932 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 933 934 r = amdgpu_bo_create_reserved(adev, fw_size, 935 PAGE_SIZE, 936 AMDGPU_GEM_DOMAIN_VRAM, 937 &adev->mes.ucode_fw_obj[inst], 938 &adev->mes.ucode_fw_gpu_addr[inst], 939 (void **)&adev->mes.ucode_fw_ptr[inst]); 940 if (r) { 941 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 942 return r; 943 } 944 945 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size); 946 947 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]); 948 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]); 949 950 return 0; 951 } 952 953 static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 954 enum amdgpu_mes_pipe pipe, 955 int xcc_id) 956 { 957 int r, inst = MES_PIPE_INST(xcc_id, pipe); 958 const struct mes_firmware_header_v1_0 *mes_hdr; 959 const __le32 *fw_data; 960 unsigned fw_size; 961 962 mes_hdr = (const struct mes_firmware_header_v1_0 *) 963 adev->mes.fw[pipe]->data; 964 965 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 966 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 967 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 968 969 r = amdgpu_bo_create_reserved(adev, fw_size, 970 64 * 1024, 971 AMDGPU_GEM_DOMAIN_VRAM, 972 &adev->mes.data_fw_obj[inst], 973 &adev->mes.data_fw_gpu_addr[inst], 974 (void **)&adev->mes.data_fw_ptr[inst]); 975 if (r) { 976 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 977 return r; 978 } 979 980 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size); 981 982 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]); 983 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]); 984 985 return 0; 986 } 987 988 static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev, 989 enum amdgpu_mes_pipe pipe, 990 int xcc_id) 991 { 992 int inst = MES_PIPE_INST(xcc_id, pipe); 993 994 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst], 995 &adev->mes.data_fw_gpu_addr[inst], 996 (void **)&adev->mes.data_fw_ptr[inst]); 997 998 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst], 999 &adev->mes.ucode_fw_gpu_addr[inst], 1000 (void **)&adev->mes.ucode_fw_ptr[inst]); 1001 } 1002 1003 static void mes_v12_1_enable(struct amdgpu_device *adev, 1004 bool enable, int xcc_id) 1005 { 1006 uint64_t ucode_addr; 1007 uint32_t pipe, data = 0; 1008 1009 if (enable) { 1010 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1011 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1012 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1013 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1014 1015 mutex_lock(&adev->srbm_mutex); 1016 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1017 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, 1018 GET_INST(GC, xcc_id)); 1019 1020 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1021 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1022 regCP_MES_PRGRM_CNTR_START, 1023 lower_32_bits(ucode_addr)); 1024 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1025 regCP_MES_PRGRM_CNTR_START_HI, 1026 upper_32_bits(ucode_addr)); 1027 } 1028 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1029 mutex_unlock(&adev->srbm_mutex); 1030 1031 /* unhalt MES and activate pipe0 */ 1032 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1033 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1034 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1035 1036 if (amdgpu_emu_mode) 1037 msleep(500); 1038 else if (adev->enable_uni_mes) 1039 udelay(500); 1040 else 1041 udelay(50); 1042 } else { 1043 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1044 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1045 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1046 data = REG_SET_FIELD(data, CP_MES_CNTL, 1047 MES_INVALIDATE_ICACHE, 1); 1048 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1049 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1050 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1051 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1052 } 1053 } 1054 1055 static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev, 1056 int xcc_id) 1057 { 1058 uint64_t ucode_addr; 1059 int pipe; 1060 1061 mes_v12_1_enable(adev, false, xcc_id); 1062 1063 mutex_lock(&adev->srbm_mutex); 1064 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1065 /* me=3, queue=0 */ 1066 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1067 1068 /* set ucode start address */ 1069 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1070 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START, 1071 lower_32_bits(ucode_addr)); 1072 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI, 1073 upper_32_bits(ucode_addr)); 1074 1075 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1076 } 1077 mutex_unlock(&adev->srbm_mutex); 1078 } 1079 1080 /* This function is for backdoor MES firmware */ 1081 static int mes_v12_1_load_microcode(struct amdgpu_device *adev, 1082 enum amdgpu_mes_pipe pipe, 1083 bool prime_icache, int xcc_id) 1084 { 1085 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1086 uint32_t data; 1087 1088 mes_v12_1_enable(adev, false, xcc_id); 1089 1090 if (!adev->mes.fw[pipe]) 1091 return -EINVAL; 1092 1093 r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id); 1094 if (r) 1095 return r; 1096 1097 r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id); 1098 if (r) { 1099 mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id); 1100 return r; 1101 } 1102 1103 mutex_lock(&adev->srbm_mutex); 1104 /* me=3, pipe=0, queue=0 */ 1105 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1106 1107 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0); 1108 1109 /* set ucode fimrware address */ 1110 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO, 1111 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1112 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI, 1113 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1114 1115 /* set ucode instruction cache boundary to 2M-1 */ 1116 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF); 1117 1118 /* set ucode data firmware address */ 1119 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO, 1120 lower_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1121 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI, 1122 upper_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1123 1124 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1125 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF); 1126 1127 if (prime_icache) { 1128 /* invalidate ICACHE */ 1129 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1130 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1131 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1132 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1133 1134 /* prime the ICACHE. */ 1135 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1136 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1137 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1138 } 1139 1140 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1141 mutex_unlock(&adev->srbm_mutex); 1142 1143 return 0; 1144 } 1145 1146 static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev, 1147 enum amdgpu_mes_pipe pipe, 1148 int xcc_id) 1149 { 1150 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1151 u32 *eop; 1152 1153 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1154 AMDGPU_GEM_DOMAIN_GTT, 1155 &adev->mes.eop_gpu_obj[inst], 1156 &adev->mes.eop_gpu_addr[inst], 1157 (void **)&eop); 1158 if (r) { 1159 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1160 return r; 1161 } 1162 1163 memset(eop, 0, 1164 adev->mes.eop_gpu_obj[inst]->tbo.base.size); 1165 1166 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]); 1167 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]); 1168 1169 return 0; 1170 } 1171 1172 static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, 1173 enum amdgpu_mes_pipe pipe, 1174 int xcc_id) 1175 { 1176 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1177 1178 if (pipe == AMDGPU_MES_KIQ_PIPE) 1179 return 0; 1180 1181 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1182 AMDGPU_GEM_DOMAIN_VRAM, 1183 &adev->mes.shared_cmd_buf_obj[inst], 1184 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1185 NULL); 1186 if (r) { 1187 dev_err(adev->dev, 1188 "(%d) failed to create shared cmd buf bo\n", r); 1189 return r; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) 1196 { 1197 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1198 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1199 uint32_t tmp; 1200 1201 mqd->header = 0xC0310800; 1202 mqd->compute_pipelinestat_enable = 0x00000001; 1203 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1204 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1205 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1206 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1207 mqd->compute_misc_reserved = 0x00000007; 1208 1209 eop_base_addr = ring->eop_gpu_addr >> 8; 1210 1211 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1212 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1213 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1214 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1215 1216 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1217 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1218 mqd->cp_hqd_eop_control = tmp; 1219 1220 /* disable the queue if it's active */ 1221 ring->wptr = 0; 1222 mqd->cp_hqd_pq_rptr = 0; 1223 mqd->cp_hqd_pq_wptr_lo = 0; 1224 mqd->cp_hqd_pq_wptr_hi = 0; 1225 1226 /* set the pointer to the MQD */ 1227 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1228 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1229 1230 /* set MQD vmid to 0 */ 1231 tmp = regCP_MQD_CONTROL_DEFAULT; 1232 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1233 mqd->cp_mqd_control = tmp; 1234 1235 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1236 hqd_gpu_addr = ring->gpu_addr >> 8; 1237 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1238 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1239 1240 /* set the wb address whether it's enabled or not */ 1241 wb_gpu_addr = ring->rptr_gpu_addr; 1242 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1243 mqd->cp_hqd_pq_rptr_report_addr_hi = 1244 upper_32_bits(wb_gpu_addr) & 0xffff; 1245 1246 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1247 wb_gpu_addr = ring->wptr_gpu_addr; 1248 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1249 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1250 1251 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1252 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1254 (order_base_2(ring->ring_size / 4) - 1)); 1255 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1256 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1257 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1258 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1259 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1260 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1261 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1262 mqd->cp_hqd_pq_control = tmp; 1263 1264 /* enable doorbell */ 1265 tmp = 0; 1266 if (ring->use_doorbell) { 1267 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1268 DOORBELL_OFFSET, ring->doorbell_index); 1269 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1270 DOORBELL_EN, 1); 1271 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1272 DOORBELL_SOURCE, 0); 1273 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1274 DOORBELL_HIT, 0); 1275 } else { 1276 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1277 DOORBELL_EN, 0); 1278 } 1279 mqd->cp_hqd_pq_doorbell_control = tmp; 1280 1281 mqd->cp_hqd_vmid = 0; 1282 /* activate the queue */ 1283 mqd->cp_hqd_active = 1; 1284 1285 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1286 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1287 PRELOAD_SIZE, 0x63); 1288 mqd->cp_hqd_persistent_state = tmp; 1289 1290 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT; 1291 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1292 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1293 1294 /* 1295 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1296 * doorbell handling. This is a reserved CP internal register can 1297 * not be accesss by others 1298 */ 1299 mqd->cp_hqd_gfx_control = BIT(15); 1300 1301 return 0; 1302 } 1303 1304 static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring, 1305 int xcc_id) 1306 { 1307 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1308 struct amdgpu_device *adev = ring->adev; 1309 uint32_t data = 0; 1310 1311 mutex_lock(&adev->srbm_mutex); 1312 soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id)); 1313 1314 /* set CP_HQD_VMID.VMID = 0. */ 1315 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID); 1316 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1317 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data); 1318 1319 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1320 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1321 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1322 DOORBELL_EN, 0); 1323 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1324 1325 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1326 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1327 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1328 1329 /* set CP_MQD_CONTROL.VMID=0 */ 1330 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1331 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1332 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0); 1333 1334 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1336 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1337 1338 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1339 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1340 mqd->cp_hqd_pq_rptr_report_addr_lo); 1341 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1342 mqd->cp_hqd_pq_rptr_report_addr_hi); 1343 1344 /* set CP_HQD_PQ_CONTROL */ 1345 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1346 1347 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1349 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1350 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1351 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1352 1353 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1354 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1355 mqd->cp_hqd_pq_doorbell_control); 1356 1357 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1358 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1359 1360 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1361 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1362 1363 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1364 mutex_unlock(&adev->srbm_mutex); 1365 } 1366 1367 static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id) 1368 { 1369 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 1370 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; 1371 int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1372 1373 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1374 return -EINVAL; 1375 1376 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1377 if (r) { 1378 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1379 return r; 1380 } 1381 1382 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); 1383 1384 r = amdgpu_ring_test_ring(kiq_ring); 1385 if (r) { 1386 DRM_ERROR("kfq enable failed\n"); 1387 kiq_ring->sched.ready = false; 1388 } 1389 return r; 1390 } 1391 1392 static int mes_v12_1_queue_init(struct amdgpu_device *adev, 1393 enum amdgpu_mes_pipe pipe, 1394 int xcc_id) 1395 { 1396 struct amdgpu_ring *ring; 1397 int r; 1398 1399 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1400 ring = &adev->gfx.kiq[xcc_id].ring; 1401 else 1402 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)]; 1403 1404 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1405 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1406 *(ring->wptr_cpu_addr) = 0; 1407 *(ring->rptr_cpu_addr) = 0; 1408 amdgpu_ring_clear_ring(ring); 1409 } 1410 1411 r = mes_v12_1_mqd_init(ring); 1412 if (r) 1413 return r; 1414 1415 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1416 if (adev->enable_uni_mes) 1417 r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id); 1418 else 1419 r = mes_v12_1_kiq_enable_queue(adev, xcc_id); 1420 if (r) 1421 return r; 1422 } else { 1423 mes_v12_1_queue_init_register(ring, xcc_id); 1424 } 1425 1426 /* get MES scheduler/KIQ versions */ 1427 mutex_lock(&adev->srbm_mutex); 1428 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1429 1430 if (pipe == AMDGPU_MES_SCHED_PIPE) 1431 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 1432 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1433 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 1434 1435 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1436 mutex_unlock(&adev->srbm_mutex); 1437 1438 return 0; 1439 } 1440 1441 static int mes_v12_1_ring_init(struct amdgpu_device *adev, 1442 int xcc_id, int pipe) 1443 { 1444 struct amdgpu_ring *ring; 1445 int inst = MES_PIPE_INST(xcc_id, pipe); 1446 1447 ring = &adev->mes.ring[inst]; 1448 1449 ring->funcs = &mes_v12_1_ring_funcs; 1450 1451 ring->me = 3; 1452 ring->pipe = pipe; 1453 ring->queue = 0; 1454 ring->xcc_id = xcc_id; 1455 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1456 1457 ring->ring_obj = NULL; 1458 ring->use_doorbell = true; 1459 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1460 ring->no_scheduler = true; 1461 snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu", 1462 (unsigned char)xcc_id, (unsigned char)ring->me, 1463 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1464 1465 if (pipe == AMDGPU_MES_SCHED_PIPE) 1466 ring->doorbell_index = 1467 (adev->doorbell_index.mes_ring0 + 1468 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1469 << 1; 1470 else 1471 ring->doorbell_index = 1472 (adev->doorbell_index.mes_ring1 + 1473 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1474 << 1; 1475 1476 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1477 AMDGPU_RING_PRIO_DEFAULT, NULL); 1478 } 1479 1480 static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id) 1481 { 1482 struct amdgpu_ring *ring; 1483 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1484 1485 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); 1486 1487 ring = &adev->gfx.kiq[xcc_id].ring; 1488 1489 ring->me = 3; 1490 ring->pipe = 1; 1491 ring->queue = 0; 1492 ring->xcc_id = xcc_id; 1493 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1494 1495 ring->adev = NULL; 1496 ring->ring_obj = NULL; 1497 ring->use_doorbell = true; 1498 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1499 ring->no_scheduler = true; 1500 ring->doorbell_index = 1501 (adev->doorbell_index.mes_ring1 + 1502 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1503 << 1; 1504 1505 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu", 1506 (unsigned char)xcc_id, (unsigned char)ring->me, 1507 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1508 1509 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1510 AMDGPU_RING_PRIO_DEFAULT, NULL); 1511 } 1512 1513 static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev, 1514 enum amdgpu_mes_pipe pipe, 1515 int xcc_id) 1516 { 1517 int r, mqd_size = sizeof(struct v12_1_mes_mqd); 1518 struct amdgpu_ring *ring; 1519 int inst = MES_PIPE_INST(xcc_id, pipe); 1520 1521 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1522 ring = &adev->gfx.kiq[xcc_id].ring; 1523 else 1524 ring = &adev->mes.ring[inst]; 1525 1526 if (ring->mqd_obj) 1527 return 0; 1528 1529 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1530 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1531 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1532 if (r) { 1533 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1534 return r; 1535 } 1536 1537 memset(ring->mqd_ptr, 0, mqd_size); 1538 1539 /* prepare MQD backup */ 1540 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL); 1541 if (!adev->mes.mqd_backup[inst]) 1542 dev_warn(adev->dev, 1543 "no memory to create MQD backup for ring %s\n", 1544 ring->name); 1545 1546 return 0; 1547 } 1548 1549 static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1550 { 1551 struct amdgpu_device *adev = ip_block->adev; 1552 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1553 1554 adev->mes.funcs = &mes_v12_1_funcs; 1555 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; 1556 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; 1557 adev->mes.enable_legacy_queue_map = true; 1558 1559 adev->mes.event_log_size = 1560 adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE; 1561 1562 r = amdgpu_mes_init(adev); 1563 if (r) 1564 return r; 1565 1566 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1567 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1568 r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id); 1569 if (r) 1570 return r; 1571 1572 r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id); 1573 if (r) 1574 return r; 1575 1576 if (!adev->enable_uni_mes && pipe == 1577 AMDGPU_MES_KIQ_PIPE) 1578 r = mes_v12_1_kiq_ring_init(adev, xcc_id); 1579 else 1580 r = mes_v12_1_ring_init(adev, xcc_id, pipe); 1581 if (r) 1582 return r; 1583 1584 if (adev->enable_uni_mes && num_xcc > 1) { 1585 r = mes_v12_1_allocate_shared_cmd_buf(adev, 1586 pipe, xcc_id); 1587 if (r) 1588 return r; 1589 } 1590 } 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1597 { 1598 struct amdgpu_device *adev = ip_block->adev; 1599 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1600 1601 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1602 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1603 inst = MES_PIPE_INST(xcc_id, pipe); 1604 1605 amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst], 1606 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1607 NULL); 1608 1609 kfree(adev->mes.mqd_backup[inst]); 1610 1611 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], 1612 &adev->mes.eop_gpu_addr[inst], 1613 NULL); 1614 amdgpu_ucode_release(&adev->mes.fw[inst]); 1615 1616 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1617 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, 1618 &adev->mes.ring[inst].mqd_gpu_addr, 1619 &adev->mes.ring[inst].mqd_ptr); 1620 amdgpu_ring_fini(&adev->mes.ring[inst]); 1621 } 1622 } 1623 } 1624 1625 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1626 if (!adev->enable_uni_mes) { 1627 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, 1628 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, 1629 &adev->gfx.kiq[xcc_id].ring.mqd_ptr); 1630 amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring); 1631 } 1632 1633 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1634 mes_v12_1_free_ucode_buffers(adev, 1635 AMDGPU_MES_KIQ_PIPE, xcc_id); 1636 mes_v12_1_free_ucode_buffers(adev, 1637 AMDGPU_MES_SCHED_PIPE, xcc_id); 1638 } 1639 } 1640 1641 amdgpu_mes_fini(adev); 1642 return 0; 1643 } 1644 1645 static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev, 1646 int xcc_id) 1647 { 1648 uint32_t data; 1649 int i; 1650 1651 mutex_lock(&adev->srbm_mutex); 1652 soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0, 1653 GET_INST(GC, xcc_id)); 1654 1655 /* disable the queue if it's active */ 1656 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1657 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1658 for (i = 0; i < adev->usec_timeout; i++) { 1659 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1660 break; 1661 udelay(1); 1662 } 1663 } 1664 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1665 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1666 DOORBELL_EN, 0); 1667 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1668 DOORBELL_HIT, 1); 1669 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1670 1671 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1672 1673 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1674 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1675 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1676 1677 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1678 mutex_unlock(&adev->srbm_mutex); 1679 1680 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false; 1681 } 1682 1683 static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1684 { 1685 uint32_t tmp; 1686 struct amdgpu_device *adev = ring->adev; 1687 1688 /* tell RLC which is KIQ queue */ 1689 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1690 tmp &= 0xffffff00; 1691 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1692 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1693 tmp |= 0x80; 1694 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1695 } 1696 1697 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1698 { 1699 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1700 int r = 0; 1701 struct amdgpu_ip_block *ip_block; 1702 1703 if (adev->enable_uni_mes) 1704 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id); 1705 else 1706 mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id); 1707 1708 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1709 1710 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, 1711 false, xcc_id); 1712 if (r) { 1713 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1714 return r; 1715 } 1716 1717 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, 1718 true, xcc_id); 1719 if (r) { 1720 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1721 return r; 1722 } 1723 1724 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1725 1726 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1727 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1728 1729 mes_v12_1_enable(adev, true, xcc_id); 1730 1731 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1732 if (unlikely(!ip_block)) { 1733 dev_err(adev->dev, "Failed to get MES handle\n"); 1734 return -EINVAL; 1735 } 1736 1737 r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id); 1738 if (r) 1739 goto failure; 1740 1741 if (adev->enable_uni_mes) { 1742 r = mes_v12_1_set_hw_resources(&adev->mes, 1743 AMDGPU_MES_KIQ_PIPE, xcc_id); 1744 if (r) 1745 goto failure; 1746 1747 mes_v12_1_set_hw_resources_1(&adev->mes, 1748 AMDGPU_MES_KIQ_PIPE, xcc_id); 1749 } 1750 1751 if (adev->mes.enable_legacy_queue_map) { 1752 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1753 if (r) 1754 goto failure; 1755 } 1756 1757 return r; 1758 1759 failure: 1760 mes_v12_1_hw_fini(ip_block); 1761 return r; 1762 } 1763 1764 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1765 { 1766 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1767 1768 if (adev->mes.ring[inst].sched.ready) { 1769 if (adev->enable_uni_mes) 1770 amdgpu_mes_unmap_legacy_queue(adev, 1771 &adev->mes.ring[inst], 1772 RESET_QUEUES, 0, 0, xcc_id); 1773 else 1774 mes_v12_1_kiq_dequeue_sched(adev, xcc_id); 1775 1776 adev->mes.ring[inst].sched.ready = false; 1777 } 1778 1779 mes_v12_1_enable(adev, false, xcc_id); 1780 1781 return 0; 1782 } 1783 1784 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id) 1785 { 1786 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1787 int r = 0; 1788 1789 if (num_xcc == 1) 1790 return r; 1791 1792 if (adev->gfx.funcs && 1793 adev->gfx.funcs->get_xccs_per_xcp) 1794 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 1795 else 1796 return -EINVAL; 1797 1798 switch (adev->xcp_mgr->mode) { 1799 case AMDGPU_SPX_PARTITION_MODE: 1800 adev->mes.enable_coop_mode = 1; 1801 adev->mes.master_xcc_ids[xcc_id] = 0; 1802 break; 1803 case AMDGPU_DPX_PARTITION_MODE: 1804 adev->mes.enable_coop_mode = 1; 1805 adev->mes.master_xcc_ids[xcc_id] = 1806 (xcc_id/num_xcc_per_xcp) * (num_xcc / 2); 1807 break; 1808 case AMDGPU_QPX_PARTITION_MODE: 1809 adev->mes.enable_coop_mode = 1; 1810 adev->mes.master_xcc_ids[xcc_id] = 1811 (xcc_id/num_xcc_per_xcp) * (num_xcc / 4); 1812 break; 1813 case AMDGPU_CPX_PARTITION_MODE: 1814 adev->mes.enable_coop_mode = 0; 1815 break; 1816 default: 1817 r = -EINVAL; 1818 break; 1819 } 1820 return r; 1821 } 1822 1823 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) 1824 { 1825 int r; 1826 struct amdgpu_device *adev = ip_block->adev; 1827 1828 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready) 1829 goto out; 1830 1831 if (!adev->enable_mes_kiq) { 1832 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1833 r = mes_v12_1_load_microcode(adev, 1834 AMDGPU_MES_SCHED_PIPE, true, xcc_id); 1835 if (r) { 1836 DRM_ERROR("failed to MES fw, r=%d\n", r); 1837 return r; 1838 } 1839 1840 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1841 1842 } else if (adev->firmware.load_type == 1843 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1844 1845 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1846 } 1847 1848 mes_v12_1_enable(adev, true, xcc_id); 1849 } 1850 1851 /* Enable the MES to handle doorbell ring on unmapped queue */ 1852 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id); 1853 1854 r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id); 1855 if (r) 1856 goto failure; 1857 1858 r = mes_v12_1_set_hw_resources(&adev->mes, 1859 AMDGPU_MES_SCHED_PIPE, xcc_id); 1860 if (r) 1861 goto failure; 1862 1863 if (adev->enable_uni_mes) { 1864 r = mes_v12_1_setup_coop_mode(adev, xcc_id); 1865 if (r) 1866 goto failure; 1867 mes_v12_1_set_hw_resources_1(&adev->mes, 1868 AMDGPU_MES_SCHED_PIPE, xcc_id); 1869 } 1870 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); 1871 1872 r = mes_v12_1_query_sched_status(&adev->mes, 1873 AMDGPU_MES_SCHED_PIPE, xcc_id); 1874 if (r) { 1875 DRM_ERROR("MES is busy\n"); 1876 goto failure; 1877 } 1878 1879 out: 1880 /* 1881 * Disable KIQ ring usage from the driver once MES is enabled. 1882 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1883 * with MES enabled. 1884 */ 1885 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1886 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true; 1887 1888 return 0; 1889 1890 failure: 1891 mes_v12_1_hw_fini(ip_block); 1892 return r; 1893 } 1894 1895 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 1896 { 1897 struct amdgpu_device *adev = ip_block->adev; 1898 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1899 1900 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1901 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1902 if (r) 1903 return r; 1904 } 1905 1906 return 0; 1907 } 1908 1909 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 1910 { 1911 return 0; 1912 } 1913 1914 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) 1915 { 1916 int r; 1917 1918 r = amdgpu_mes_suspend(ip_block->adev); 1919 if (r) 1920 return r; 1921 1922 return mes_v12_1_hw_fini(ip_block); 1923 } 1924 1925 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) 1926 { 1927 int r; 1928 1929 r = mes_v12_1_hw_init(ip_block); 1930 if (r) 1931 return r; 1932 1933 return amdgpu_mes_resume(ip_block->adev); 1934 } 1935 1936 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) 1937 { 1938 struct amdgpu_device *adev = ip_block->adev; 1939 int pipe, r; 1940 1941 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1942 r = amdgpu_mes_init_microcode(adev, pipe); 1943 if (r) 1944 return r; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static const struct amd_ip_funcs mes_v12_1_ip_funcs = { 1951 .name = "mes_v12_1", 1952 .early_init = mes_v12_1_early_init, 1953 .late_init = NULL, 1954 .sw_init = mes_v12_1_sw_init, 1955 .sw_fini = mes_v12_1_sw_fini, 1956 .hw_init = mes_v12_1_hw_init, 1957 .hw_fini = mes_v12_1_hw_fini, 1958 .suspend = mes_v12_1_suspend, 1959 .resume = mes_v12_1_resume, 1960 }; 1961 1962 const struct amdgpu_ip_block_version mes_v12_1_ip_block = { 1963 .type = AMD_IP_BLOCK_TYPE_MES, 1964 .major = 12, 1965 .minor = 1, 1966 .rev = 0, 1967 .funcs = &mes_v12_1_ip_funcs, 1968 }; 1969