1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc_v1_0.h" 29 #include "gc/gc_12_1_0_offset.h" 30 #include "gc/gc_12_1_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 #include "gfx_v12_1_pkt.h" 35 #include "sdma_v7_1_0_pkt_open.h" 36 37 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin"); 40 41 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block); 42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id); 43 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 46 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id); 47 48 #define MES_EOP_SIZE 2048 49 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 50 #define MES12_HUNG_HQD_INFO_OFFSET 4 51 52 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 53 #define XCC_MID_MASK 0x41000000 54 55 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) 56 { 57 struct amdgpu_device *adev = ring->adev; 58 59 if (ring->use_doorbell) { 60 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 61 ring->wptr); 62 WDOORBELL64(ring->doorbell_index, ring->wptr); 63 } else { 64 BUG(); 65 } 66 } 67 68 static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring) 69 { 70 return *ring->rptr_cpu_addr; 71 } 72 73 static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring) 74 { 75 u64 wptr; 76 77 if (ring->use_doorbell) 78 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 79 else 80 BUG(); 81 return wptr; 82 } 83 84 static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = { 85 .type = AMDGPU_RING_TYPE_MES, 86 .align_mask = 1, 87 .nop = 0, 88 .support_64bit_ptrs = true, 89 .get_rptr = mes_v12_1_ring_get_rptr, 90 .get_wptr = mes_v12_1_ring_get_wptr, 91 .set_wptr = mes_v12_1_ring_set_wptr, 92 .insert_nop = amdgpu_ring_insert_nop, 93 }; 94 95 static const char *mes_v12_1_opcodes[] = { 96 "SET_HW_RSRC", 97 "SET_SCHEDULING_CONFIG", 98 "ADD_QUEUE", 99 "REMOVE_QUEUE", 100 "PERFORM_YIELD", 101 "SET_GANG_PRIORITY_LEVEL", 102 "SUSPEND", 103 "RESUME", 104 "RESET", 105 "SET_LOG_BUFFER", 106 "CHANGE_GANG_PRORITY", 107 "QUERY_SCHEDULER_STATUS", 108 "unused", 109 "SET_DEBUG_VMID", 110 "MISC", 111 "UPDATE_ROOT_PAGE_TABLE", 112 "AMD_LOG", 113 "SET_SE_MODE", 114 "SET_GANG_SUBMIT", 115 "SET_HW_RSRC_1", 116 "INVALIDATE_TLBS", 117 }; 118 119 static const char *mes_v12_1_misc_opcodes[] = { 120 "WRITE_REG", 121 "INV_GART", 122 "QUERY_STATUS", 123 "READ_REG", 124 "WAIT_REG_MEM", 125 "SET_SHADER_DEBUGGER", 126 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 127 "NOTIFY_TO_UNMAP_PROCESSES", 128 }; 129 130 static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt) 131 { 132 const char *op_str = NULL; 133 134 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes)) 135 op_str = mes_v12_1_opcodes[x_pkt->header.opcode]; 136 137 return op_str; 138 } 139 140 static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt) 141 { 142 const char *op_str = NULL; 143 144 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 145 (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes))) 146 op_str = mes_v12_1_misc_opcodes[x_pkt->opcode]; 147 148 return op_str; 149 } 150 151 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 152 int xcc_id, int pipe, void *pkt, 153 int size, int api_status_off) 154 { 155 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 156 signed long timeout = 2100000; /* 2100 ms */ 157 struct amdgpu_device *adev = mes->adev; 158 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; 159 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; 160 struct MES_API_STATUS *api_status; 161 union MESAPI__MISC *x_pkt = pkt; 162 const char *op_str, *misc_op_str; 163 unsigned long flags; 164 u64 status_gpu_addr; 165 u32 seq, status_offset; 166 u64 *status_ptr; 167 signed long r; 168 int ret; 169 170 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 171 return -EINVAL; 172 173 if (amdgpu_emu_mode) { 174 timeout *= 1000; 175 } else if (amdgpu_sriov_vf(adev)) { 176 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 177 timeout = 15 * 600 * 1000; 178 } 179 180 ret = amdgpu_wb_get(adev, &status_offset); 181 if (ret) 182 return ret; 183 184 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 185 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 186 *status_ptr = 0; 187 188 spin_lock_irqsave(ring_lock, flags); 189 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 190 if (r) 191 goto error_unlock_free; 192 193 seq = ++ring->fence_drv.sync_seq; 194 r = amdgpu_fence_wait_polling(ring, 195 seq - ring->fence_drv.num_fences_mask, 196 timeout); 197 if (r < 1) 198 goto error_undo; 199 200 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 201 api_status->api_completion_fence_addr = status_gpu_addr; 202 api_status->api_completion_fence_value = 1; 203 204 amdgpu_ring_write_multiple(ring, pkt, size / 4); 205 206 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 207 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 208 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 209 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 210 mes_status_pkt.api_status.api_completion_fence_addr = 211 ring->fence_drv.gpu_addr; 212 mes_status_pkt.api_status.api_completion_fence_value = seq; 213 214 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 215 sizeof(mes_status_pkt) / 4); 216 217 amdgpu_ring_commit(ring); 218 spin_unlock_irqrestore(ring_lock, flags); 219 220 op_str = mes_v12_1_get_op_string(x_pkt); 221 misc_op_str = mes_v12_1_get_misc_op_string(x_pkt); 222 223 if (misc_op_str) 224 dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n", 225 xcc_id, pipe, op_str, misc_op_str); 226 else if (op_str) 227 dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n", 228 xcc_id, pipe, op_str); 229 else 230 dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n", 231 xcc_id, pipe, x_pkt->header.opcode); 232 233 r = amdgpu_fence_wait_polling(ring, seq, timeout); 234 if (r < 1 || !lower_32_bits(*status_ptr)) { 235 if (misc_op_str) 236 dev_err(adev->dev, 237 "MES(%d, %d) failed to respond to msg=%s (%s)\n", 238 xcc_id, pipe, op_str, misc_op_str); 239 else if (op_str) 240 dev_err(adev->dev, 241 "MES(%d, %d) failed to respond to msg=%s\n", 242 xcc_id, pipe, op_str); 243 else 244 dev_err(adev->dev, 245 "MES(%d, %d) failed to respond to msg=%d\n", 246 xcc_id, pipe, x_pkt->header.opcode); 247 248 while (halt_if_hws_hang) 249 schedule(); 250 251 r = -ETIMEDOUT; 252 goto error_wb_free; 253 } 254 255 amdgpu_wb_free(adev, status_offset); 256 return 0; 257 258 error_undo: 259 dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe); 260 amdgpu_ring_undo(ring); 261 262 error_unlock_free: 263 spin_unlock_irqrestore(ring_lock, flags); 264 265 error_wb_free: 266 amdgpu_wb_free(adev, status_offset); 267 return r; 268 } 269 270 static int convert_to_mes_queue_type(int queue_type) 271 { 272 if (queue_type == AMDGPU_RING_TYPE_GFX) 273 return MES_QUEUE_TYPE_GFX; 274 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 275 return MES_QUEUE_TYPE_COMPUTE; 276 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 277 return MES_QUEUE_TYPE_SDMA; 278 else if (queue_type == AMDGPU_RING_TYPE_MES) 279 return MES_QUEUE_TYPE_SCHQ; 280 else 281 BUG(); 282 return -1; 283 } 284 285 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, 286 struct mes_add_queue_input *input) 287 { 288 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 289 int xcc_id = input->xcc_id; 290 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 291 292 if (mes->enable_coop_mode) 293 xcc_id = mes->master_xcc_ids[inst]; 294 295 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 296 297 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 298 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 299 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 300 301 mes_add_queue_pkt.process_id = input->process_id; 302 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 303 mes_add_queue_pkt.process_va_start = input->process_va_start; 304 mes_add_queue_pkt.process_va_end = input->process_va_end; 305 mes_add_queue_pkt.process_quantum = input->process_quantum; 306 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 307 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 308 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 309 mes_add_queue_pkt.inprocess_gang_priority = 310 input->inprocess_gang_priority; 311 mes_add_queue_pkt.gang_global_priority_level = 312 input->gang_global_priority_level; 313 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 314 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 315 316 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 317 318 mes_add_queue_pkt.queue_type = 319 convert_to_mes_queue_type(input->queue_type); 320 mes_add_queue_pkt.paging = input->paging; 321 mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl; 322 mes_add_queue_pkt.gws_base = input->gws_base; 323 mes_add_queue_pkt.gws_size = input->gws_size; 324 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 325 mes_add_queue_pkt.tma_addr = input->tma_addr; 326 mes_add_queue_pkt.trap_en = input->trap_en; 327 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 328 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 329 330 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 331 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 332 mes_add_queue_pkt.gds_size = input->queue_size; 333 334 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 335 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 336 mes_add_queue_pkt.gds_size = input->queue_size; 337 338 mes_add_queue_pkt.full_sh_mem_config_data = input->sh_mem_config_data; 339 340 return mes_v12_1_submit_pkt_and_poll_completion(mes, 341 xcc_id, AMDGPU_MES_SCHED_PIPE, 342 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 343 offsetof(union MESAPI__ADD_QUEUE, api_status)); 344 } 345 346 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, 347 struct mes_remove_queue_input *input) 348 { 349 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 350 int xcc_id = input->xcc_id; 351 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 352 353 if (mes->enable_coop_mode) 354 xcc_id = mes->master_xcc_ids[inst]; 355 356 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 357 358 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 359 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 360 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 361 362 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 363 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 364 mes_remove_queue_pkt.queue_type = 365 convert_to_mes_queue_type(input->queue_type); 366 367 return mes_v12_1_submit_pkt_and_poll_completion(mes, 368 xcc_id, AMDGPU_MES_SCHED_PIPE, 369 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 370 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 371 } 372 373 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, 374 struct mes_reset_queue_input *input) 375 { 376 union MESAPI__RESET mes_reset_queue_pkt; 377 int pipe; 378 379 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 380 381 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 382 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 383 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 384 385 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 386 /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ 387 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 388 389 if (mes->adev->enable_uni_mes) 390 pipe = AMDGPU_MES_KIQ_PIPE; 391 else 392 pipe = AMDGPU_MES_SCHED_PIPE; 393 394 return mes_v12_1_submit_pkt_and_poll_completion(mes, 395 input->xcc_id, pipe, 396 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 397 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 398 } 399 400 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, 401 struct mes_map_legacy_queue_input *input) 402 { 403 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 404 int pipe; 405 406 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 407 408 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 409 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 410 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 411 412 mes_add_queue_pkt.pipe_id = input->pipe_id; 413 mes_add_queue_pkt.queue_id = input->queue_id; 414 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 415 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 416 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 417 mes_add_queue_pkt.queue_type = 418 convert_to_mes_queue_type(input->queue_type); 419 mes_add_queue_pkt.map_legacy_kq = 1; 420 421 if (mes->adev->enable_uni_mes) { 422 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 423 if (input->queue_type == AMDGPU_RING_TYPE_MES) 424 pipe = AMDGPU_MES_KIQ_PIPE; 425 else 426 pipe = AMDGPU_MES_SCHED_PIPE; 427 } else { 428 pipe = AMDGPU_MES_SCHED_PIPE; 429 } 430 431 return mes_v12_1_submit_pkt_and_poll_completion(mes, 432 input->xcc_id, pipe, 433 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 434 offsetof(union MESAPI__ADD_QUEUE, api_status)); 435 } 436 437 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, 438 struct mes_unmap_legacy_queue_input *input) 439 { 440 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 441 int pipe; 442 443 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 444 445 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 446 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 447 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 448 449 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 450 mes_remove_queue_pkt.gang_context_addr = 0; 451 452 mes_remove_queue_pkt.pipe_id = input->pipe_id; 453 mes_remove_queue_pkt.queue_id = input->queue_id; 454 455 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 456 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 457 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 458 mes_remove_queue_pkt.tf_data = 459 lower_32_bits(input->trail_fence_data); 460 } else { 461 mes_remove_queue_pkt.unmap_legacy_queue = 1; 462 mes_remove_queue_pkt.queue_type = 463 convert_to_mes_queue_type(input->queue_type); 464 } 465 466 if (mes->adev->enable_uni_mes) { 467 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 468 if (input->queue_type == AMDGPU_RING_TYPE_MES) 469 pipe = AMDGPU_MES_KIQ_PIPE; 470 else 471 pipe = AMDGPU_MES_SCHED_PIPE; 472 } else { 473 pipe = AMDGPU_MES_SCHED_PIPE; 474 } 475 476 return mes_v12_1_submit_pkt_and_poll_completion(mes, 477 input->xcc_id, pipe, 478 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 479 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 480 } 481 482 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, 483 struct mes_suspend_gang_input *input) 484 { 485 union MESAPI__SUSPEND mes_suspend_gang_pkt; 486 487 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 488 489 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 490 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 491 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 492 493 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 494 mes_suspend_gang_pkt.suspend_all_sdma_gangs = input->suspend_all_sdma_gangs; 495 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 496 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 497 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 498 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 499 500 /* Suspend gang is handled by master MES */ 501 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, 502 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 503 offsetof(union MESAPI__SUSPEND, api_status)); 504 } 505 506 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, 507 struct mes_resume_gang_input *input) 508 { 509 union MESAPI__RESUME mes_resume_gang_pkt; 510 511 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 512 513 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 514 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 515 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 516 517 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 518 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 519 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 520 521 /* Resume gang is handled by master MES */ 522 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE, 523 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 524 offsetof(union MESAPI__RESUME, api_status)); 525 } 526 527 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, 528 int pipe, int xcc_id) 529 { 530 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 531 532 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 533 534 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 535 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 536 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 537 538 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 539 &mes_status_pkt, sizeof(mes_status_pkt), 540 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 541 } 542 static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) 543 { 544 return ((reg_offset >> 16) & 0x7); 545 } 546 547 static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, 548 struct RRMT_OPTION *rrmt_opt, 549 uint32_t *out_reg) 550 { 551 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 552 553 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) { 554 rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg); 555 rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? 556 MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; 557 } else { 558 rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID; 559 if (soc_v1_0_mid1_reg_range(reg)) 560 rrmt_opt->mid_die_id = 1; 561 } 562 563 *out_reg = soc_v1_0_normalize_reg_offset(reg); 564 } 565 566 static int mes_v12_1_misc_op(struct amdgpu_mes *mes, 567 struct mes_misc_op_input *input) 568 { 569 struct amdgpu_device *adev = mes->adev; 570 union MESAPI__MISC misc_pkt; 571 int pipe; 572 573 if (mes->adev->enable_uni_mes) 574 pipe = AMDGPU_MES_KIQ_PIPE; 575 else 576 pipe = AMDGPU_MES_SCHED_PIPE; 577 578 memset(&misc_pkt, 0, sizeof(misc_pkt)); 579 580 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 581 misc_pkt.header.opcode = MES_SCH_API_MISC; 582 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 583 584 switch (input->op) { 585 case MES_MISC_OP_READ_REG: 586 misc_pkt.opcode = MESAPI_MISC__READ_REG; 587 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 588 mes_v12_1_get_rrmt(input->read_reg.reg_offset, 589 GET_INST(GC, input->xcc_id), 590 &misc_pkt.read_reg.rrmt_opt, 591 &misc_pkt.read_reg.reg_offset); 592 break; 593 case MES_MISC_OP_WRITE_REG: 594 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 595 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 596 mes_v12_1_get_rrmt(input->write_reg.reg_offset, 597 GET_INST(GC, input->xcc_id), 598 &misc_pkt.write_reg.rrmt_opt, 599 &misc_pkt.write_reg.reg_offset); 600 break; 601 case MES_MISC_OP_WRM_REG_WAIT: 602 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 603 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 604 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 605 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 606 misc_pkt.wait_reg_mem.reg_offset2 = 0; 607 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 608 GET_INST(GC, input->xcc_id), 609 &misc_pkt.wait_reg_mem.rrmt_opt1, 610 &misc_pkt.wait_reg_mem.reg_offset1); 611 break; 612 case MES_MISC_OP_WRM_REG_WR_WAIT: 613 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 614 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 615 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 616 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 617 mes_v12_1_get_rrmt(input->wrm_reg.reg0, 618 GET_INST(GC, input->xcc_id), 619 &misc_pkt.wait_reg_mem.rrmt_opt1, 620 &misc_pkt.wait_reg_mem.reg_offset1); 621 mes_v12_1_get_rrmt(input->wrm_reg.reg1, 622 GET_INST(GC, input->xcc_id), 623 &misc_pkt.wait_reg_mem.rrmt_opt2, 624 &misc_pkt.wait_reg_mem.reg_offset2); 625 break; 626 case MES_MISC_OP_SET_SHADER_DEBUGGER: 627 pipe = AMDGPU_MES_SCHED_PIPE; 628 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 629 misc_pkt.set_shader_debugger.process_context_addr = 630 input->set_shader_debugger.process_context_addr; 631 misc_pkt.set_shader_debugger.flags.u32all = 632 input->set_shader_debugger.flags.u32all; 633 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 634 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 635 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 636 input->set_shader_debugger.tcp_watch_cntl, 637 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 638 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 639 break; 640 case MES_MISC_OP_CHANGE_CONFIG: 641 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 642 misc_pkt.change_config.opcode = 643 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 644 misc_pkt.change_config.option.bits.limit_single_process = 645 input->change_config.option.limit_single_process; 646 break; 647 default: 648 DRM_ERROR("unsupported misc op (%d) \n", input->op); 649 return -EINVAL; 650 } 651 652 return mes_v12_1_submit_pkt_and_poll_completion(mes, 653 input->xcc_id, pipe, 654 &misc_pkt, sizeof(misc_pkt), 655 offsetof(union MESAPI__MISC, api_status)); 656 } 657 658 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, 659 int pipe, int xcc_id) 660 { 661 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 662 int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); 663 664 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 665 666 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 667 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 668 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 669 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 670 671 /* From version 0x74 above, pipe1 support use shared command buffer 672 to distribute some tasks on individual XCCs*/ 673 if (mes->enable_coop_mode && 674 ((pipe == AMDGPU_MES_SCHED_PIPE) || 675 ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) { 676 master_xcc_id = mes->master_xcc_ids[inst]; 677 mes_set_hw_res_1_pkt.mes_coop_mode = 1; 678 mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = 679 mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe]; 680 } 681 682 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 683 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 684 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 685 } 686 687 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, 688 int pipe, int xcc_id) 689 { 690 int i, status; 691 struct amdgpu_device *adev = mes->adev; 692 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 693 694 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 695 696 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 697 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 698 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 699 700 if (pipe == AMDGPU_MES_SCHED_PIPE) { 701 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 702 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 703 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 704 mes_set_hw_res_pkt.paging_vmid = 0; 705 706 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 707 mes_set_hw_res_pkt.compute_hqd_mask[i] = 708 mes->compute_hqd_mask[i]; 709 710 for (i = 0; i < MAX_GFX_PIPES; i++) 711 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 712 mes->gfx_hqd_mask[i]; 713 714 for (i = 0; i < MAX_SDMA_PIPES; i++) 715 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 716 mes->sdma_hqd_mask[i]; 717 718 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 719 mes_set_hw_res_pkt.aggregated_doorbells[i] = 720 mes->aggregated_doorbells[i]; 721 } 722 723 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 724 mes->sch_ctx_gpu_addr[pipe]; 725 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 726 mes->query_status_fence_gpu_addr[pipe]; 727 728 for (i = 0; i < 5; i++) { 729 mes_set_hw_res_pkt.gc_base[i] = 730 adev->reg_offset[GC_HWIP][0][i]; 731 mes_set_hw_res_pkt.mmhub_base[i] = 732 adev->reg_offset[MMHUB_HWIP][0][i]; 733 mes_set_hw_res_pkt.osssys_base[i] = 734 adev->reg_offset[OSSSYS_HWIP][0][i]; 735 } 736 737 mes_set_hw_res_pkt.disable_reset = 1; 738 mes_set_hw_res_pkt.disable_mes_log = 1; 739 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 740 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 741 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 742 743 /* 744 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 745 * handling support, other queue will not use the oversubscribe timer. 746 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 747 */ 748 mes_set_hw_res_pkt.oversubscription_timer = 50; 749 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 750 751 if (amdgpu_mes_log_enable) { 752 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 753 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 754 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE; 755 } 756 757 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 758 mes_set_hw_res_pkt.limit_single_process = 1; 759 760 status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, 761 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 762 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 763 764 /* get MES scheduler versions */ 765 mutex_lock(&adev->srbm_mutex); 766 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 767 768 if (pipe == AMDGPU_MES_SCHED_PIPE) 769 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 770 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 771 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); 772 773 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 774 mutex_unlock(&adev->srbm_mutex); 775 776 return status; 777 } 778 779 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, 780 int xcc_id) 781 { 782 struct amdgpu_device *adev = mes->adev; 783 uint32_t data; 784 785 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1); 786 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 787 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 788 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 789 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 790 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 791 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 792 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data); 793 794 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2); 795 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 796 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 797 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 798 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 799 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 800 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 801 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data); 802 803 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3); 804 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 805 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 806 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 807 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 808 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 809 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 810 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data); 811 812 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4); 813 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 814 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 815 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 816 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 817 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 818 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 819 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data); 820 821 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5); 822 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 823 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 824 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 825 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 826 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 827 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 828 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data); 829 830 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 831 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data); 832 } 833 834 835 static void mes_v12_1_enable_unmapped_doorbell_handling( 836 struct amdgpu_mes *mes, bool enable, int xcc_id) 837 { 838 struct amdgpu_device *adev = mes->adev; 839 uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL); 840 841 /* 842 * The default PROC_LSB settng is 0xc which means doorbell 843 * addr[16:12] gives the doorbell page number. For kfd, each 844 * process will use 2 pages of doorbell, we need to change the 845 * setting to 0xd 846 */ 847 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 848 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 849 850 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 851 852 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data); 853 } 854 855 #if 0 856 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, 857 struct mes_reset_legacy_queue_input *input) 858 { 859 union MESAPI__RESET mes_reset_queue_pkt; 860 int pipe; 861 862 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 863 864 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 865 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 866 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 867 868 mes_reset_queue_pkt.queue_type = 869 convert_to_mes_queue_type(input->queue_type); 870 871 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 872 mes_reset_queue_pkt.reset_legacy_gfx = 1; 873 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 874 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 875 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 876 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 877 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 878 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 879 } else { 880 mes_reset_queue_pkt.reset_queue_only = 1; 881 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 882 } 883 884 if (mes->adev->enable_uni_mes) 885 pipe = AMDGPU_MES_KIQ_PIPE; 886 else 887 pipe = AMDGPU_MES_SCHED_PIPE; 888 889 return mes_v12_1_submit_pkt_and_poll_completion(mes, 890 input->xcc_id, pipe, 891 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 892 offsetof(union MESAPI__RESET, api_status)); 893 } 894 #endif 895 896 static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 897 struct mes_detect_and_reset_queue_input *input) 898 { 899 union MESAPI__RESET mes_reset_queue_pkt; 900 901 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 902 903 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 904 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 905 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 906 907 mes_reset_queue_pkt.queue_type = 908 convert_to_mes_queue_type(input->queue_type); 909 mes_reset_queue_pkt.doorbell_offset_addr = 910 mes->hung_queue_db_array_gpu_addr[0]; 911 912 if (input->detect_only) 913 mes_reset_queue_pkt.hang_detect_only = 1; 914 else 915 mes_reset_queue_pkt.hang_detect_then_reset = 1; 916 917 return mes_v12_1_submit_pkt_and_poll_completion(mes, 918 input->xcc_id, AMDGPU_MES_SCHED_PIPE, 919 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 920 offsetof(union MESAPI__RESET, api_status)); 921 } 922 923 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 924 { 925 /* 926 * MES doesn't support invalidate gc_hub on slave xcc individually 927 * master xcc will invalidate all gc_hub for the partition 928 */ 929 if (AMDGPU_IS_GFXHUB(id)) 930 return 0; 931 else if (AMDGPU_IS_MMHUB0(id)) 932 return 1; 933 else if (AMDGPU_IS_MMHUB1(id)) 934 return 2; 935 return -EINVAL; 936 937 } 938 939 static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes, 940 struct mes_inv_tlbs_pasid_input *input) 941 { 942 union MESAPI__INV_TLBS mes_inv_tlbs; 943 int xcc_id = input->xcc_id; 944 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 945 int ret; 946 947 if (mes->enable_coop_mode) 948 xcc_id = mes->master_xcc_ids[inst]; 949 950 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 951 952 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 953 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 954 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 955 956 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 957 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 958 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 959 960 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 961 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 962 if (ret < 0) 963 return -EINVAL; 964 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 965 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE, 966 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 967 offsetof(union MESAPI__INV_TLBS, api_status)); 968 969 } 970 971 static const struct amdgpu_mes_funcs mes_v12_1_funcs = { 972 .add_hw_queue = mes_v12_1_add_hw_queue, 973 .remove_hw_queue = mes_v12_1_remove_hw_queue, 974 .map_legacy_queue = mes_v12_1_map_legacy_queue, 975 .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue, 976 .suspend_gang = mes_v12_1_suspend_gang, 977 .resume_gang = mes_v12_1_resume_gang, 978 .misc_op = mes_v12_1_misc_op, 979 .reset_hw_queue = mes_v12_1_reset_hw_queue, 980 .detect_and_reset_hung_queues = mes_v12_1_detect_and_reset_hung_queues, 981 .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, 982 }; 983 984 static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev, 985 enum amdgpu_mes_pipe pipe, 986 int xcc_id) 987 { 988 int r, inst = MES_PIPE_INST(xcc_id, pipe); 989 const struct mes_firmware_header_v1_0 *mes_hdr; 990 const __le32 *fw_data; 991 unsigned fw_size; 992 993 mes_hdr = (const struct mes_firmware_header_v1_0 *) 994 adev->mes.fw[pipe]->data; 995 996 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 997 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 998 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 999 1000 r = amdgpu_bo_create_reserved(adev, fw_size, 1001 PAGE_SIZE, 1002 AMDGPU_GEM_DOMAIN_VRAM, 1003 &adev->mes.ucode_fw_obj[inst], 1004 &adev->mes.ucode_fw_gpu_addr[inst], 1005 (void **)&adev->mes.ucode_fw_ptr[inst]); 1006 if (r) { 1007 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1008 return r; 1009 } 1010 1011 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size); 1012 1013 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]); 1014 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]); 1015 1016 return 0; 1017 } 1018 1019 static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1020 enum amdgpu_mes_pipe pipe, 1021 int xcc_id) 1022 { 1023 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1024 const struct mes_firmware_header_v1_0 *mes_hdr; 1025 const __le32 *fw_data; 1026 unsigned fw_size; 1027 1028 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1029 adev->mes.fw[pipe]->data; 1030 1031 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1032 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1033 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1034 1035 r = amdgpu_bo_create_reserved(adev, fw_size, 1036 64 * 1024, 1037 AMDGPU_GEM_DOMAIN_VRAM, 1038 &adev->mes.data_fw_obj[inst], 1039 &adev->mes.data_fw_gpu_addr[inst], 1040 (void **)&adev->mes.data_fw_ptr[inst]); 1041 if (r) { 1042 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1043 return r; 1044 } 1045 1046 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size); 1047 1048 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]); 1049 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]); 1050 1051 return 0; 1052 } 1053 1054 static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev, 1055 enum amdgpu_mes_pipe pipe, 1056 int xcc_id) 1057 { 1058 int inst = MES_PIPE_INST(xcc_id, pipe); 1059 1060 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst], 1061 &adev->mes.data_fw_gpu_addr[inst], 1062 (void **)&adev->mes.data_fw_ptr[inst]); 1063 1064 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst], 1065 &adev->mes.ucode_fw_gpu_addr[inst], 1066 (void **)&adev->mes.ucode_fw_ptr[inst]); 1067 } 1068 1069 static void mes_v12_1_enable(struct amdgpu_device *adev, 1070 bool enable, int xcc_id) 1071 { 1072 uint64_t ucode_addr; 1073 uint32_t pipe, data = 0; 1074 1075 if (enable) { 1076 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1077 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1078 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1079 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1080 1081 mutex_lock(&adev->srbm_mutex); 1082 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1083 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, 1084 GET_INST(GC, xcc_id)); 1085 1086 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1087 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1088 regCP_MES_PRGRM_CNTR_START, 1089 lower_32_bits(ucode_addr)); 1090 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1091 regCP_MES_PRGRM_CNTR_START_HI, 1092 upper_32_bits(ucode_addr)); 1093 } 1094 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1095 mutex_unlock(&adev->srbm_mutex); 1096 1097 /* unhalt MES and activate pipe0 */ 1098 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1099 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1100 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1101 1102 if (amdgpu_emu_mode) 1103 msleep(500); 1104 else if (adev->enable_uni_mes) 1105 udelay(500); 1106 else 1107 udelay(50); 1108 } else { 1109 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); 1110 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1111 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1112 data = REG_SET_FIELD(data, CP_MES_CNTL, 1113 MES_INVALIDATE_ICACHE, 1); 1114 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1115 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1116 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1117 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); 1118 } 1119 } 1120 1121 static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev, 1122 int xcc_id) 1123 { 1124 uint64_t ucode_addr; 1125 int pipe; 1126 1127 mes_v12_1_enable(adev, false, xcc_id); 1128 1129 mutex_lock(&adev->srbm_mutex); 1130 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1131 /* me=3, queue=0 */ 1132 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1133 1134 /* set ucode start address */ 1135 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1136 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START, 1137 lower_32_bits(ucode_addr)); 1138 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI, 1139 upper_32_bits(ucode_addr)); 1140 1141 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1142 } 1143 mutex_unlock(&adev->srbm_mutex); 1144 } 1145 1146 /* This function is for backdoor MES firmware */ 1147 static int mes_v12_1_load_microcode(struct amdgpu_device *adev, 1148 enum amdgpu_mes_pipe pipe, 1149 bool prime_icache, int xcc_id) 1150 { 1151 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1152 uint32_t data; 1153 1154 mes_v12_1_enable(adev, false, xcc_id); 1155 1156 if (!adev->mes.fw[pipe]) 1157 return -EINVAL; 1158 1159 r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id); 1160 if (r) 1161 return r; 1162 1163 r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id); 1164 if (r) { 1165 mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id); 1166 return r; 1167 } 1168 1169 mutex_lock(&adev->srbm_mutex); 1170 /* me=3, pipe=0, queue=0 */ 1171 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); 1172 1173 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0); 1174 1175 /* set ucode fimrware address */ 1176 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO, 1177 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1178 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI, 1179 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); 1180 1181 /* set ucode instruction cache boundary to 2M-1 */ 1182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF); 1183 1184 /* set ucode data firmware address */ 1185 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO, 1186 lower_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1187 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI, 1188 upper_32_bits(adev->mes.data_fw_gpu_addr[inst])); 1189 1190 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1191 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF); 1192 1193 if (prime_icache) { 1194 /* invalidate ICACHE */ 1195 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1196 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1197 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1198 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1199 1200 /* prime the ICACHE. */ 1201 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); 1202 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1203 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); 1204 } 1205 1206 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1207 mutex_unlock(&adev->srbm_mutex); 1208 1209 return 0; 1210 } 1211 1212 static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev, 1213 enum amdgpu_mes_pipe pipe, 1214 int xcc_id) 1215 { 1216 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1217 u32 *eop; 1218 1219 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1220 AMDGPU_GEM_DOMAIN_GTT, 1221 &adev->mes.eop_gpu_obj[inst], 1222 &adev->mes.eop_gpu_addr[inst], 1223 (void **)&eop); 1224 if (r) { 1225 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1226 return r; 1227 } 1228 1229 memset(eop, 0, 1230 adev->mes.eop_gpu_obj[inst]->tbo.base.size); 1231 1232 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]); 1233 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]); 1234 1235 return 0; 1236 } 1237 1238 static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, 1239 enum amdgpu_mes_pipe pipe, 1240 int xcc_id) 1241 { 1242 int r, inst = MES_PIPE_INST(xcc_id, pipe); 1243 1244 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1245 AMDGPU_GEM_DOMAIN_VRAM, 1246 &adev->mes.shared_cmd_buf_obj[inst], 1247 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1248 NULL); 1249 if (r) { 1250 dev_err(adev->dev, 1251 "(%d) failed to create shared cmd buf bo\n", r); 1252 return r; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) 1259 { 1260 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1261 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1262 uint32_t tmp; 1263 1264 mqd->header = 0xC0310800; 1265 mqd->compute_pipelinestat_enable = 0x00000001; 1266 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1267 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1268 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1269 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1270 mqd->compute_misc_reserved = 0x00000007; 1271 1272 eop_base_addr = ring->eop_gpu_addr >> 8; 1273 1274 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1275 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1276 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1277 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1278 1279 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1280 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1281 mqd->cp_hqd_eop_control = tmp; 1282 1283 /* disable the queue if it's active */ 1284 ring->wptr = 0; 1285 mqd->cp_hqd_pq_rptr = 0; 1286 mqd->cp_hqd_pq_wptr_lo = 0; 1287 mqd->cp_hqd_pq_wptr_hi = 0; 1288 1289 /* set the pointer to the MQD */ 1290 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1291 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1292 1293 /* set MQD vmid to 0 */ 1294 tmp = regCP_MQD_CONTROL_DEFAULT; 1295 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1296 mqd->cp_mqd_control = tmp; 1297 1298 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1299 hqd_gpu_addr = ring->gpu_addr >> 8; 1300 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1301 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1302 1303 /* set the wb address whether it's enabled or not */ 1304 wb_gpu_addr = ring->rptr_gpu_addr; 1305 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1306 mqd->cp_hqd_pq_rptr_report_addr_hi = 1307 upper_32_bits(wb_gpu_addr) & 0xffff; 1308 1309 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1310 wb_gpu_addr = ring->wptr_gpu_addr; 1311 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1312 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1313 1314 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1315 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1316 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1317 (order_base_2(ring->ring_size / 4) - 1)); 1318 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1319 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1323 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1324 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1325 mqd->cp_hqd_pq_control = tmp; 1326 1327 /* enable doorbell */ 1328 tmp = 0; 1329 if (ring->use_doorbell) { 1330 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1331 DOORBELL_OFFSET, ring->doorbell_index); 1332 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1333 DOORBELL_EN, 1); 1334 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1335 DOORBELL_SOURCE, 0); 1336 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1337 DOORBELL_HIT, 0); 1338 } else { 1339 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1340 DOORBELL_EN, 0); 1341 } 1342 mqd->cp_hqd_pq_doorbell_control = tmp; 1343 1344 mqd->cp_hqd_vmid = 0; 1345 /* activate the queue */ 1346 mqd->cp_hqd_active = 1; 1347 1348 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1349 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1350 PRELOAD_SIZE, 0x63); 1351 mqd->cp_hqd_persistent_state = tmp; 1352 1353 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT; 1354 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1355 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1356 1357 /* 1358 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1359 * doorbell handling. This is a reserved CP internal register can 1360 * not be accesss by others 1361 */ 1362 mqd->cp_hqd_gfx_control = BIT(15); 1363 1364 return 0; 1365 } 1366 1367 static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring, 1368 int xcc_id) 1369 { 1370 struct v12_1_mes_mqd *mqd = ring->mqd_ptr; 1371 struct amdgpu_device *adev = ring->adev; 1372 uint32_t data = 0; 1373 1374 mutex_lock(&adev->srbm_mutex); 1375 soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id)); 1376 1377 /* set CP_HQD_VMID.VMID = 0. */ 1378 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID); 1379 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1380 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data); 1381 1382 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1383 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1384 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1385 DOORBELL_EN, 0); 1386 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1387 1388 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1389 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1390 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1391 1392 /* set CP_MQD_CONTROL.VMID=0 */ 1393 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1394 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1395 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0); 1396 1397 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1398 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1399 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1400 1401 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1402 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1403 mqd->cp_hqd_pq_rptr_report_addr_lo); 1404 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1405 mqd->cp_hqd_pq_rptr_report_addr_hi); 1406 1407 /* set CP_HQD_PQ_CONTROL */ 1408 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1409 1410 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1411 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1412 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1413 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1414 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1415 1416 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1418 mqd->cp_hqd_pq_doorbell_control); 1419 1420 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1421 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1422 1423 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1424 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1425 1426 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1427 mutex_unlock(&adev->srbm_mutex); 1428 } 1429 1430 static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id) 1431 { 1432 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 1433 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; 1434 int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1435 1436 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1437 return -EINVAL; 1438 1439 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1440 if (r) { 1441 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1442 return r; 1443 } 1444 1445 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); 1446 1447 r = amdgpu_ring_test_ring(kiq_ring); 1448 if (r) { 1449 DRM_ERROR("kfq enable failed\n"); 1450 kiq_ring->sched.ready = false; 1451 } 1452 return r; 1453 } 1454 1455 static int mes_v12_1_queue_init(struct amdgpu_device *adev, 1456 enum amdgpu_mes_pipe pipe, 1457 int xcc_id) 1458 { 1459 struct amdgpu_ring *ring; 1460 int r; 1461 1462 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1463 ring = &adev->gfx.kiq[xcc_id].ring; 1464 else 1465 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)]; 1466 1467 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1468 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1469 *(ring->wptr_cpu_addr) = 0; 1470 *(ring->rptr_cpu_addr) = 0; 1471 amdgpu_ring_clear_ring(ring); 1472 } 1473 1474 r = mes_v12_1_mqd_init(ring); 1475 if (r) 1476 return r; 1477 1478 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1479 if (adev->enable_uni_mes) 1480 r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id); 1481 else 1482 r = mes_v12_1_kiq_enable_queue(adev, xcc_id); 1483 if (r) 1484 return r; 1485 } else { 1486 mes_v12_1_queue_init_register(ring, xcc_id); 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int mes_v12_1_ring_init(struct amdgpu_device *adev, 1493 int xcc_id, int pipe) 1494 { 1495 struct amdgpu_ring *ring; 1496 int inst = MES_PIPE_INST(xcc_id, pipe); 1497 1498 ring = &adev->mes.ring[inst]; 1499 1500 ring->funcs = &mes_v12_1_ring_funcs; 1501 1502 ring->me = 3; 1503 ring->pipe = pipe; 1504 ring->queue = 0; 1505 ring->xcc_id = xcc_id; 1506 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1507 1508 ring->ring_obj = NULL; 1509 ring->use_doorbell = true; 1510 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1511 ring->no_scheduler = true; 1512 snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu", 1513 (unsigned char)xcc_id, (unsigned char)ring->me, 1514 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1515 1516 if (pipe == AMDGPU_MES_SCHED_PIPE) 1517 ring->doorbell_index = 1518 (adev->doorbell_index.mes_ring0 + 1519 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1520 << 1; 1521 else 1522 ring->doorbell_index = 1523 (adev->doorbell_index.mes_ring1 + 1524 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1525 << 1; 1526 1527 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1528 AMDGPU_RING_PRIO_DEFAULT, NULL); 1529 } 1530 1531 static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id) 1532 { 1533 struct amdgpu_ring *ring; 1534 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1535 1536 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); 1537 1538 ring = &adev->gfx.kiq[xcc_id].ring; 1539 1540 ring->me = 3; 1541 ring->pipe = 1; 1542 ring->queue = 0; 1543 ring->xcc_id = xcc_id; 1544 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1545 1546 ring->adev = NULL; 1547 ring->ring_obj = NULL; 1548 ring->use_doorbell = true; 1549 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; 1550 ring->no_scheduler = true; 1551 ring->doorbell_index = 1552 (adev->doorbell_index.mes_ring1 + 1553 xcc_id * adev->doorbell_index.xcc_doorbell_range) 1554 << 1; 1555 1556 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu", 1557 (unsigned char)xcc_id, (unsigned char)ring->me, 1558 (unsigned char)ring->pipe, (unsigned char)ring->queue); 1559 1560 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1561 AMDGPU_RING_PRIO_DEFAULT, NULL); 1562 } 1563 1564 static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev, 1565 enum amdgpu_mes_pipe pipe, 1566 int xcc_id) 1567 { 1568 int r, mqd_size = sizeof(struct v12_1_mes_mqd); 1569 struct amdgpu_ring *ring; 1570 int inst = MES_PIPE_INST(xcc_id, pipe); 1571 1572 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1573 ring = &adev->gfx.kiq[xcc_id].ring; 1574 else 1575 ring = &adev->mes.ring[inst]; 1576 1577 if (ring->mqd_obj) 1578 return 0; 1579 1580 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1581 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1582 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1583 if (r) { 1584 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1585 return r; 1586 } 1587 1588 memset(ring->mqd_ptr, 0, mqd_size); 1589 1590 /* prepare MQD backup */ 1591 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL); 1592 if (!adev->mes.mqd_backup[inst]) 1593 dev_warn(adev->dev, 1594 "no memory to create MQD backup for ring %s\n", 1595 ring->name); 1596 1597 return 0; 1598 } 1599 1600 static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1601 { 1602 struct amdgpu_device *adev = ip_block->adev; 1603 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1604 1605 adev->mes.funcs = &mes_v12_1_funcs; 1606 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; 1607 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; 1608 adev->mes.enable_legacy_queue_map = true; 1609 1610 adev->mes.event_log_size = 1611 adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE; 1612 1613 r = amdgpu_mes_init(adev); 1614 if (r) 1615 return r; 1616 1617 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1618 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1619 r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id); 1620 if (r) 1621 return r; 1622 1623 r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id); 1624 if (r) 1625 return r; 1626 1627 if (!adev->enable_uni_mes && pipe == 1628 AMDGPU_MES_KIQ_PIPE) 1629 r = mes_v12_1_kiq_ring_init(adev, xcc_id); 1630 else 1631 r = mes_v12_1_ring_init(adev, xcc_id, pipe); 1632 if (r) 1633 return r; 1634 1635 if (adev->enable_uni_mes && num_xcc > 1) { 1636 r = mes_v12_1_allocate_shared_cmd_buf(adev, 1637 pipe, xcc_id); 1638 if (r) 1639 return r; 1640 } 1641 } 1642 } 1643 1644 return 0; 1645 } 1646 1647 static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1648 { 1649 struct amdgpu_device *adev = ip_block->adev; 1650 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1651 1652 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1653 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1654 inst = MES_PIPE_INST(xcc_id, pipe); 1655 1656 amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst], 1657 &adev->mes.shared_cmd_buf_gpu_addr[inst], 1658 NULL); 1659 1660 kfree(adev->mes.mqd_backup[inst]); 1661 1662 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], 1663 &adev->mes.eop_gpu_addr[inst], 1664 NULL); 1665 1666 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1667 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, 1668 &adev->mes.ring[inst].mqd_gpu_addr, 1669 &adev->mes.ring[inst].mqd_ptr); 1670 amdgpu_ring_fini(&adev->mes.ring[inst]); 1671 } 1672 } 1673 } 1674 1675 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) 1676 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1677 1678 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1679 if (!adev->enable_uni_mes) { 1680 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, 1681 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, 1682 &adev->gfx.kiq[xcc_id].ring.mqd_ptr); 1683 amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring); 1684 } 1685 1686 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1687 mes_v12_1_free_ucode_buffers(adev, 1688 AMDGPU_MES_KIQ_PIPE, xcc_id); 1689 mes_v12_1_free_ucode_buffers(adev, 1690 AMDGPU_MES_SCHED_PIPE, xcc_id); 1691 } 1692 } 1693 1694 amdgpu_mes_fini(adev); 1695 return 0; 1696 } 1697 1698 static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev, 1699 int xcc_id) 1700 { 1701 uint32_t data; 1702 int i; 1703 1704 mutex_lock(&adev->srbm_mutex); 1705 soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0, 1706 GET_INST(GC, xcc_id)); 1707 1708 /* disable the queue if it's active */ 1709 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1710 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1711 for (i = 0; i < adev->usec_timeout; i++) { 1712 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1713 break; 1714 udelay(1); 1715 } 1716 } 1717 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1718 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1719 DOORBELL_EN, 0); 1720 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1721 DOORBELL_HIT, 1); 1722 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); 1723 1724 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1725 1726 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1727 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1728 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1729 1730 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1731 mutex_unlock(&adev->srbm_mutex); 1732 1733 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false; 1734 } 1735 1736 static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1737 { 1738 uint32_t tmp; 1739 struct amdgpu_device *adev = ring->adev; 1740 1741 /* tell RLC which is KIQ queue */ 1742 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1743 tmp &= 0xffffff00; 1744 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1745 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1746 tmp |= 0x80; 1747 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1748 } 1749 1750 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1751 { 1752 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); 1753 int r = 0; 1754 struct amdgpu_ip_block *ip_block; 1755 1756 if (adev->enable_uni_mes) 1757 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id); 1758 else 1759 mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id); 1760 1761 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1762 1763 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, 1764 false, xcc_id); 1765 if (r) { 1766 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1767 return r; 1768 } 1769 1770 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, 1771 true, xcc_id); 1772 if (r) { 1773 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1774 return r; 1775 } 1776 1777 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1778 1779 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1780 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1781 1782 mes_v12_1_enable(adev, true, xcc_id); 1783 1784 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1785 if (unlikely(!ip_block)) { 1786 dev_err(adev->dev, "Failed to get MES handle\n"); 1787 return -EINVAL; 1788 } 1789 1790 r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id); 1791 if (r) 1792 goto failure; 1793 1794 if (adev->enable_uni_mes) { 1795 r = mes_v12_1_setup_coop_mode(adev, xcc_id); 1796 if (r) 1797 goto failure; 1798 1799 r = mes_v12_1_set_hw_resources(&adev->mes, 1800 AMDGPU_MES_KIQ_PIPE, xcc_id); 1801 if (r) 1802 goto failure; 1803 1804 mes_v12_1_set_hw_resources_1(&adev->mes, 1805 AMDGPU_MES_KIQ_PIPE, xcc_id); 1806 } 1807 1808 if (adev->mes.enable_legacy_queue_map) { 1809 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1810 if (r) 1811 goto failure; 1812 } 1813 1814 return r; 1815 1816 failure: 1817 mes_v12_1_hw_fini(ip_block); 1818 return r; 1819 } 1820 1821 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1822 { 1823 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); 1824 1825 if (adev->mes.ring[inst].sched.ready) { 1826 if (adev->enable_uni_mes) 1827 amdgpu_mes_unmap_legacy_queue(adev, 1828 &adev->mes.ring[inst], 1829 RESET_QUEUES, 0, 0, xcc_id); 1830 else 1831 mes_v12_1_kiq_dequeue_sched(adev, xcc_id); 1832 1833 adev->mes.ring[inst].sched.ready = false; 1834 } 1835 1836 mes_v12_1_enable(adev, false, xcc_id); 1837 1838 return 0; 1839 } 1840 1841 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id) 1842 { 1843 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1844 int r = 0; 1845 1846 if (num_xcc == 1) 1847 return r; 1848 1849 if (adev->gfx.funcs && 1850 adev->gfx.funcs->get_xccs_per_xcp) 1851 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 1852 else 1853 return -EINVAL; 1854 1855 switch (adev->xcp_mgr->mode) { 1856 case AMDGPU_SPX_PARTITION_MODE: 1857 adev->mes.enable_coop_mode = 1; 1858 adev->mes.master_xcc_ids[xcc_id] = 0; 1859 break; 1860 case AMDGPU_DPX_PARTITION_MODE: 1861 adev->mes.enable_coop_mode = 1; 1862 adev->mes.master_xcc_ids[xcc_id] = 1863 (xcc_id/num_xcc_per_xcp) * (num_xcc / 2); 1864 break; 1865 case AMDGPU_QPX_PARTITION_MODE: 1866 adev->mes.enable_coop_mode = 1; 1867 adev->mes.master_xcc_ids[xcc_id] = 1868 (xcc_id/num_xcc_per_xcp) * (num_xcc / 4); 1869 break; 1870 case AMDGPU_CPX_PARTITION_MODE: 1871 adev->mes.enable_coop_mode = 0; 1872 break; 1873 default: 1874 r = -EINVAL; 1875 break; 1876 } 1877 return r; 1878 } 1879 1880 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) 1881 { 1882 int r; 1883 struct amdgpu_device *adev = ip_block->adev; 1884 1885 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready) 1886 goto out; 1887 1888 if (!adev->enable_mes_kiq) { 1889 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1890 r = mes_v12_1_load_microcode(adev, 1891 AMDGPU_MES_SCHED_PIPE, true, xcc_id); 1892 if (r) { 1893 DRM_ERROR("failed to MES fw, r=%d\n", r); 1894 return r; 1895 } 1896 1897 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1898 1899 } else if (adev->firmware.load_type == 1900 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1901 1902 mes_v12_1_set_ucode_start_addr(adev, xcc_id); 1903 } 1904 1905 mes_v12_1_enable(adev, true, xcc_id); 1906 } 1907 1908 /* Enable the MES to handle doorbell ring on unmapped queue */ 1909 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id); 1910 1911 r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id); 1912 if (r) 1913 goto failure; 1914 1915 r = mes_v12_1_set_hw_resources(&adev->mes, 1916 AMDGPU_MES_SCHED_PIPE, xcc_id); 1917 if (r) 1918 goto failure; 1919 1920 if (adev->enable_uni_mes) { 1921 mes_v12_1_set_hw_resources_1(&adev->mes, 1922 AMDGPU_MES_SCHED_PIPE, xcc_id); 1923 } 1924 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); 1925 1926 r = mes_v12_1_query_sched_status(&adev->mes, 1927 AMDGPU_MES_SCHED_PIPE, xcc_id); 1928 if (r) { 1929 DRM_ERROR("MES is busy\n"); 1930 goto failure; 1931 } 1932 1933 amdgpu_mes_validate_fw_version(adev); 1934 out: 1935 /* 1936 * Disable KIQ ring usage from the driver once MES is enabled. 1937 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1938 * with MES enabled. 1939 */ 1940 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1941 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true; 1942 1943 return 0; 1944 1945 failure: 1946 mes_v12_1_hw_fini(ip_block); 1947 return r; 1948 } 1949 1950 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 1951 { 1952 struct amdgpu_device *adev = ip_block->adev; 1953 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1954 1955 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1956 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1957 if (r) 1958 return r; 1959 } 1960 1961 return 0; 1962 } 1963 1964 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 1965 { 1966 return 0; 1967 } 1968 1969 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) 1970 { 1971 return mes_v12_1_hw_fini(ip_block); 1972 } 1973 1974 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) 1975 { 1976 return mes_v12_1_hw_init(ip_block); 1977 } 1978 1979 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) 1980 { 1981 struct amdgpu_device *adev = ip_block->adev; 1982 int pipe, r; 1983 1984 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1985 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 1986 1987 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1988 r = amdgpu_mes_init_microcode(adev, pipe); 1989 if (r) 1990 return r; 1991 } 1992 1993 return 0; 1994 } 1995 1996 static const struct amd_ip_funcs mes_v12_1_ip_funcs = { 1997 .name = "mes_v12_1", 1998 .early_init = mes_v12_1_early_init, 1999 .late_init = NULL, 2000 .sw_init = mes_v12_1_sw_init, 2001 .sw_fini = mes_v12_1_sw_fini, 2002 .hw_init = mes_v12_1_hw_init, 2003 .hw_fini = mes_v12_1_hw_fini, 2004 .suspend = mes_v12_1_suspend, 2005 .resume = mes_v12_1_resume, 2006 }; 2007 2008 const struct amdgpu_ip_block_version mes_v12_1_ip_block = { 2009 .type = AMD_IP_BLOCK_TYPE_MES, 2010 .major = 12, 2011 .minor = 1, 2012 .rev = 0, 2013 .funcs = &mes_v12_1_ip_funcs, 2014 }; 2015