1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "gfx_v12_0.h" 28 #include "soc15_common.h" 29 #include "soc21.h" 30 #include "gc/gc_12_0_0_offset.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v12_structs.h" 34 #include "mes_v12_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 42 43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); 45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 #define MES12_HUNG_HQD_INFO_OFFSET 4 52 53 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 54 { 55 struct amdgpu_device *adev = ring->adev; 56 57 if (ring->use_doorbell) { 58 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 59 ring->wptr); 60 WDOORBELL64(ring->doorbell_index, ring->wptr); 61 } else { 62 BUG(); 63 } 64 } 65 66 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 67 { 68 return *ring->rptr_cpu_addr; 69 } 70 71 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 72 { 73 u64 wptr; 74 75 if (ring->use_doorbell) 76 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 77 else 78 BUG(); 79 return wptr; 80 } 81 82 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 83 .type = AMDGPU_RING_TYPE_MES, 84 .align_mask = 1, 85 .nop = 0, 86 .support_64bit_ptrs = true, 87 .get_rptr = mes_v12_0_ring_get_rptr, 88 .get_wptr = mes_v12_0_ring_get_wptr, 89 .set_wptr = mes_v12_0_ring_set_wptr, 90 .insert_nop = amdgpu_ring_insert_nop, 91 }; 92 93 static const char *mes_v12_0_opcodes[] = { 94 "SET_HW_RSRC", 95 "SET_SCHEDULING_CONFIG", 96 "ADD_QUEUE", 97 "REMOVE_QUEUE", 98 "PERFORM_YIELD", 99 "SET_GANG_PRIORITY_LEVEL", 100 "SUSPEND", 101 "RESUME", 102 "RESET", 103 "SET_LOG_BUFFER", 104 "CHANGE_GANG_PRORITY", 105 "QUERY_SCHEDULER_STATUS", 106 "unused", 107 "SET_DEBUG_VMID", 108 "MISC", 109 "UPDATE_ROOT_PAGE_TABLE", 110 "AMD_LOG", 111 "SET_SE_MODE", 112 "SET_GANG_SUBMIT", 113 "SET_HW_RSRC_1", 114 "INVALIDATE_TLBS", 115 }; 116 117 static const char *mes_v12_0_misc_opcodes[] = { 118 "WRITE_REG", 119 "INV_GART", 120 "QUERY_STATUS", 121 "READ_REG", 122 "WAIT_REG_MEM", 123 "SET_SHADER_DEBUGGER", 124 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 125 "NOTIFY_TO_UNMAP_PROCESSES", 126 }; 127 128 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 129 { 130 const char *op_str = NULL; 131 132 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 133 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 134 135 return op_str; 136 } 137 138 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 139 { 140 const char *op_str = NULL; 141 142 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 143 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 144 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 145 146 return op_str; 147 } 148 149 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 150 int pipe, void *pkt, int size, 151 int api_status_off) 152 { 153 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 154 signed long timeout = 2100000; /* 2100 ms */ 155 struct amdgpu_device *adev = mes->adev; 156 struct amdgpu_ring *ring = &mes->ring[pipe]; 157 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 158 struct MES_API_STATUS *api_status; 159 union MESAPI__MISC *x_pkt = pkt; 160 const char *op_str, *misc_op_str; 161 unsigned long flags; 162 u64 status_gpu_addr; 163 u32 seq, status_offset; 164 u64 *status_ptr; 165 signed long r; 166 int ret; 167 168 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 169 return -EINVAL; 170 171 if (amdgpu_emu_mode) { 172 timeout *= 100; 173 } else if (amdgpu_sriov_vf(adev)) { 174 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 175 timeout = 15 * 600 * 1000; 176 } 177 178 ret = amdgpu_device_wb_get(adev, &status_offset); 179 if (ret) 180 return ret; 181 182 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 183 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 184 *status_ptr = 0; 185 186 spin_lock_irqsave(ring_lock, flags); 187 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 188 if (r) 189 goto error_unlock_free; 190 191 seq = ++ring->fence_drv.sync_seq; 192 r = amdgpu_fence_wait_polling(ring, 193 seq - ring->fence_drv.num_fences_mask, 194 timeout); 195 if (r < 1) 196 goto error_undo; 197 198 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 199 api_status->api_completion_fence_addr = status_gpu_addr; 200 api_status->api_completion_fence_value = 1; 201 202 amdgpu_ring_write_multiple(ring, pkt, size / 4); 203 204 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 205 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 206 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 207 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 208 mes_status_pkt.api_status.api_completion_fence_addr = 209 ring->fence_drv.gpu_addr; 210 mes_status_pkt.api_status.api_completion_fence_value = seq; 211 212 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 213 sizeof(mes_status_pkt) / 4); 214 215 amdgpu_ring_commit(ring); 216 spin_unlock_irqrestore(ring_lock, flags); 217 218 op_str = mes_v12_0_get_op_string(x_pkt); 219 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 220 221 if (misc_op_str) 222 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 223 pipe, op_str, misc_op_str); 224 else if (op_str) 225 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 226 pipe, op_str); 227 else 228 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 229 pipe, x_pkt->header.opcode); 230 231 r = amdgpu_fence_wait_polling(ring, seq, timeout); 232 233 /* 234 * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success). 235 * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information. 236 */ 237 if (r < 1 || !(lower_32_bits(*status_ptr))) { 238 239 if (misc_op_str) 240 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 241 pipe, op_str, misc_op_str); 242 else if (op_str) 243 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 244 pipe, op_str); 245 else 246 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 247 pipe, x_pkt->header.opcode); 248 249 while (halt_if_hws_hang) 250 schedule(); 251 252 r = -ETIMEDOUT; 253 goto error_wb_free; 254 } 255 256 amdgpu_device_wb_free(adev, status_offset); 257 return 0; 258 259 error_undo: 260 dev_err(adev->dev, "MES ring buffer is full.\n"); 261 amdgpu_ring_undo(ring); 262 263 error_unlock_free: 264 spin_unlock_irqrestore(ring_lock, flags); 265 266 error_wb_free: 267 amdgpu_device_wb_free(adev, status_offset); 268 return r; 269 } 270 271 static int convert_to_mes_queue_type(int queue_type) 272 { 273 if (queue_type == AMDGPU_RING_TYPE_GFX) 274 return MES_QUEUE_TYPE_GFX; 275 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 276 return MES_QUEUE_TYPE_COMPUTE; 277 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 278 return MES_QUEUE_TYPE_SDMA; 279 else if (queue_type == AMDGPU_RING_TYPE_MES) 280 return MES_QUEUE_TYPE_SCHQ; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int convert_to_mes_priority_level(int priority_level) 287 { 288 switch (priority_level) { 289 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 290 return AMD_PRIORITY_LEVEL_LOW; 291 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 292 default: 293 return AMD_PRIORITY_LEVEL_NORMAL; 294 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 295 return AMD_PRIORITY_LEVEL_MEDIUM; 296 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 297 return AMD_PRIORITY_LEVEL_HIGH; 298 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 299 return AMD_PRIORITY_LEVEL_REALTIME; 300 } 301 } 302 303 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 304 struct mes_add_queue_input *input) 305 { 306 struct amdgpu_device *adev = mes->adev; 307 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 308 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 309 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 310 311 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 312 313 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 314 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 315 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 316 317 mes_add_queue_pkt.process_id = input->process_id; 318 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 319 mes_add_queue_pkt.process_va_start = input->process_va_start; 320 mes_add_queue_pkt.process_va_end = input->process_va_end; 321 mes_add_queue_pkt.process_quantum = input->process_quantum; 322 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 323 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 324 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 325 mes_add_queue_pkt.inprocess_gang_priority = 326 convert_to_mes_priority_level(input->inprocess_gang_priority); 327 mes_add_queue_pkt.gang_global_priority_level = 328 convert_to_mes_priority_level(input->gang_global_priority_level); 329 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 330 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 331 332 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 333 334 mes_add_queue_pkt.queue_type = 335 convert_to_mes_queue_type(input->queue_type); 336 mes_add_queue_pkt.paging = input->paging; 337 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 338 mes_add_queue_pkt.gws_base = input->gws_base; 339 mes_add_queue_pkt.gws_size = input->gws_size; 340 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 341 mes_add_queue_pkt.tma_addr = input->tma_addr; 342 mes_add_queue_pkt.trap_en = input->trap_en; 343 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 344 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 345 346 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 347 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 348 mes_add_queue_pkt.gds_size = input->queue_size; 349 350 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 351 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 352 mes_add_queue_pkt.gds_size = input->queue_size; 353 354 return mes_v12_0_submit_pkt_and_poll_completion(mes, 355 AMDGPU_MES_SCHED_PIPE, 356 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 357 offsetof(union MESAPI__ADD_QUEUE, api_status)); 358 } 359 360 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 361 struct mes_remove_queue_input *input) 362 { 363 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 364 365 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 366 367 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 368 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 369 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 370 371 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 372 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 373 374 return mes_v12_0_submit_pkt_and_poll_completion(mes, 375 AMDGPU_MES_SCHED_PIPE, 376 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 377 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 378 } 379 380 int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev, 381 bool req) 382 { 383 u32 i, tmp, val; 384 385 for (i = 0; i < adev->usec_timeout; i++) { 386 /* Request with MeId=2, PipeId=0 */ 387 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 388 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 389 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 390 391 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 392 if (req) { 393 if (val == tmp) 394 break; 395 } else { 396 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 397 REQUEST, 1); 398 399 /* unlocked or locked by firmware */ 400 if (val != tmp) 401 break; 402 } 403 udelay(1); 404 } 405 406 if (i >= adev->usec_timeout) 407 return -EINVAL; 408 409 return 0; 410 } 411 412 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 413 uint32_t me_id, uint32_t pipe_id, 414 uint32_t queue_id, uint32_t vmid) 415 { 416 struct amdgpu_device *adev = mes->adev; 417 uint32_t value, reg; 418 int i, r = 0; 419 420 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 421 422 if (queue_type == AMDGPU_RING_TYPE_GFX) { 423 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 424 me_id, pipe_id, queue_id, vmid); 425 426 mutex_lock(&adev->gfx.reset_sem_mutex); 427 gfx_v12_0_request_gfx_index_mutex(adev, true); 428 /* all se allow writes */ 429 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 430 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 431 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 432 if (pipe_id == 0) 433 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 434 else 435 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 436 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 437 gfx_v12_0_request_gfx_index_mutex(adev, false); 438 mutex_unlock(&adev->gfx.reset_sem_mutex); 439 440 mutex_lock(&adev->srbm_mutex); 441 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 442 /* wait till dequeue take effects */ 443 for (i = 0; i < adev->usec_timeout; i++) { 444 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 445 break; 446 udelay(1); 447 } 448 if (i >= adev->usec_timeout) { 449 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 450 r = -ETIMEDOUT; 451 } 452 453 soc21_grbm_select(adev, 0, 0, 0, 0); 454 mutex_unlock(&adev->srbm_mutex); 455 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 456 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 457 me_id, pipe_id, queue_id); 458 mutex_lock(&adev->srbm_mutex); 459 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 460 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 461 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 462 463 /* wait till dequeue take effects */ 464 for (i = 0; i < adev->usec_timeout; i++) { 465 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 466 break; 467 udelay(1); 468 } 469 if (i >= adev->usec_timeout) { 470 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 471 r = -ETIMEDOUT; 472 } 473 soc21_grbm_select(adev, 0, 0, 0, 0); 474 mutex_unlock(&adev->srbm_mutex); 475 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 476 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 477 me_id, pipe_id, queue_id); 478 switch (me_id) { 479 case 1: 480 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 481 break; 482 case 0: 483 default: 484 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 485 break; 486 } 487 488 value = 1 << queue_id; 489 WREG32(reg, value); 490 /* wait for queue reset done */ 491 for (i = 0; i < adev->usec_timeout; i++) { 492 if (!(RREG32(reg) & value)) 493 break; 494 udelay(1); 495 } 496 if (i >= adev->usec_timeout) { 497 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 498 r = -ETIMEDOUT; 499 } 500 } 501 502 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 503 return r; 504 } 505 506 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 507 struct mes_map_legacy_queue_input *input) 508 { 509 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 510 int pipe; 511 512 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 513 514 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 515 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 516 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 517 518 mes_add_queue_pkt.pipe_id = input->pipe_id; 519 mes_add_queue_pkt.queue_id = input->queue_id; 520 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 521 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 522 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 523 mes_add_queue_pkt.queue_type = 524 convert_to_mes_queue_type(input->queue_type); 525 mes_add_queue_pkt.map_legacy_kq = 1; 526 527 if (mes->adev->enable_uni_mes) 528 pipe = AMDGPU_MES_KIQ_PIPE; 529 else 530 pipe = AMDGPU_MES_SCHED_PIPE; 531 532 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 533 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 534 offsetof(union MESAPI__ADD_QUEUE, api_status)); 535 } 536 537 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 538 struct mes_unmap_legacy_queue_input *input) 539 { 540 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 541 int pipe; 542 543 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 544 545 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 546 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 547 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 548 549 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 550 mes_remove_queue_pkt.gang_context_addr = 0; 551 552 mes_remove_queue_pkt.pipe_id = input->pipe_id; 553 mes_remove_queue_pkt.queue_id = input->queue_id; 554 555 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 556 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 557 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 558 mes_remove_queue_pkt.tf_data = 559 lower_32_bits(input->trail_fence_data); 560 } else { 561 mes_remove_queue_pkt.unmap_legacy_queue = 1; 562 mes_remove_queue_pkt.queue_type = 563 convert_to_mes_queue_type(input->queue_type); 564 } 565 566 if (mes->adev->enable_uni_mes) 567 pipe = AMDGPU_MES_KIQ_PIPE; 568 else 569 pipe = AMDGPU_MES_SCHED_PIPE; 570 571 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 572 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 573 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 574 } 575 576 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 577 struct mes_suspend_gang_input *input) 578 { 579 union MESAPI__SUSPEND mes_suspend_gang_pkt; 580 581 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 582 583 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 584 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 585 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 586 587 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 588 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 589 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 590 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 591 592 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 593 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 594 offsetof(union MESAPI__SUSPEND, api_status)); 595 } 596 597 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 598 struct mes_resume_gang_input *input) 599 { 600 union MESAPI__RESUME mes_resume_gang_pkt; 601 602 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 603 604 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 605 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 606 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 607 608 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 609 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 610 611 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 612 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 613 offsetof(union MESAPI__RESUME, api_status)); 614 } 615 616 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 617 { 618 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 619 620 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 621 622 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 623 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 624 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 625 626 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 627 &mes_status_pkt, sizeof(mes_status_pkt), 628 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 629 } 630 631 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 632 struct mes_misc_op_input *input) 633 { 634 union MESAPI__MISC misc_pkt; 635 int pipe; 636 637 if (mes->adev->enable_uni_mes) 638 pipe = AMDGPU_MES_KIQ_PIPE; 639 else 640 pipe = AMDGPU_MES_SCHED_PIPE; 641 642 memset(&misc_pkt, 0, sizeof(misc_pkt)); 643 644 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 645 misc_pkt.header.opcode = MES_SCH_API_MISC; 646 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 647 648 switch (input->op) { 649 case MES_MISC_OP_READ_REG: 650 misc_pkt.opcode = MESAPI_MISC__READ_REG; 651 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 652 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 653 break; 654 case MES_MISC_OP_WRITE_REG: 655 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 656 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 657 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 658 break; 659 case MES_MISC_OP_WRM_REG_WAIT: 660 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 661 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 662 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 663 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 664 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 665 misc_pkt.wait_reg_mem.reg_offset2 = 0; 666 break; 667 case MES_MISC_OP_WRM_REG_WR_WAIT: 668 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 669 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 670 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 671 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 672 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 673 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 674 break; 675 case MES_MISC_OP_SET_SHADER_DEBUGGER: 676 pipe = AMDGPU_MES_SCHED_PIPE; 677 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 678 misc_pkt.set_shader_debugger.process_context_addr = 679 input->set_shader_debugger.process_context_addr; 680 misc_pkt.set_shader_debugger.flags.u32all = 681 input->set_shader_debugger.flags.u32all; 682 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 683 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 684 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 685 input->set_shader_debugger.tcp_watch_cntl, 686 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 687 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 688 break; 689 case MES_MISC_OP_CHANGE_CONFIG: 690 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 691 misc_pkt.change_config.opcode = 692 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 693 misc_pkt.change_config.option.bits.limit_single_process = 694 input->change_config.option.limit_single_process; 695 break; 696 697 default: 698 DRM_ERROR("unsupported misc op (%d) \n", input->op); 699 return -EINVAL; 700 } 701 702 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 703 &misc_pkt, sizeof(misc_pkt), 704 offsetof(union MESAPI__MISC, api_status)); 705 } 706 707 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 708 { 709 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 710 711 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 712 713 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 714 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 715 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 716 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa; 717 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr = 718 mes->resource_1_gpu_addr[pipe]; 719 720 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 721 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 722 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 723 } 724 725 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 726 { 727 int i; 728 struct amdgpu_device *adev = mes->adev; 729 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 730 731 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 732 733 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 734 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 735 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 736 737 if (pipe == AMDGPU_MES_SCHED_PIPE) { 738 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 739 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 740 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 741 mes_set_hw_res_pkt.paging_vmid = 0; 742 743 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 744 mes_set_hw_res_pkt.compute_hqd_mask[i] = 745 mes->compute_hqd_mask[i]; 746 747 for (i = 0; i < MAX_GFX_PIPES; i++) 748 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 749 mes->gfx_hqd_mask[i]; 750 751 for (i = 0; i < MAX_SDMA_PIPES; i++) 752 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 753 mes->sdma_hqd_mask[i]; 754 755 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 756 mes_set_hw_res_pkt.aggregated_doorbells[i] = 757 mes->aggregated_doorbells[i]; 758 } 759 760 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 761 mes->sch_ctx_gpu_addr[pipe]; 762 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 763 mes->query_status_fence_gpu_addr[pipe]; 764 765 for (i = 0; i < 5; i++) { 766 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 767 mes_set_hw_res_pkt.mmhub_base[i] = 768 adev->reg_offset[MMHUB_HWIP][0][i]; 769 mes_set_hw_res_pkt.osssys_base[i] = 770 adev->reg_offset[OSSSYS_HWIP][0][i]; 771 } 772 773 mes_set_hw_res_pkt.disable_reset = 1; 774 mes_set_hw_res_pkt.disable_mes_log = 1; 775 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 776 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 777 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 778 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82) 779 mes_set_hw_res_pkt.enable_lr_compute_wa = 1; 780 else 781 dev_info_once(adev->dev, 782 "MES FW version must be >= 0x82 to enable LR compute workaround.\n"); 783 784 /* 785 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 786 * handling support, other queue will not use the oversubscribe timer. 787 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 788 */ 789 mes_set_hw_res_pkt.oversubscription_timer = 50; 790 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 791 792 if (amdgpu_mes_log_enable) { 793 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 794 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + 795 pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 796 } 797 798 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 799 mes_set_hw_res_pkt.limit_single_process = 1; 800 801 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 802 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 803 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 804 } 805 806 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 807 { 808 struct amdgpu_device *adev = mes->adev; 809 uint32_t data; 810 811 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 812 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 813 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 814 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 815 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 816 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 817 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 818 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 819 820 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 821 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 822 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 823 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 824 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 825 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 826 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 827 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 828 829 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 830 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 831 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 832 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 833 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 834 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 835 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 836 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 837 838 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 839 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 840 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 841 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 842 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 843 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 844 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 845 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 846 847 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 848 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 849 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 850 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 851 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 852 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 853 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 854 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 855 856 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 857 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 858 } 859 860 861 static void mes_v12_0_enable_unmapped_doorbell_handling( 862 struct amdgpu_mes *mes, bool enable) 863 { 864 struct amdgpu_device *adev = mes->adev; 865 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 866 867 /* 868 * The default PROC_LSB settng is 0xc which means doorbell 869 * addr[16:12] gives the doorbell page number. For kfd, each 870 * process will use 2 pages of doorbell, we need to change the 871 * setting to 0xd 872 */ 873 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 874 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 875 876 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 877 878 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 879 } 880 881 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 882 struct mes_reset_queue_input *input) 883 { 884 union MESAPI__RESET mes_reset_queue_pkt; 885 int pipe; 886 887 if (input->use_mmio) 888 return mes_v12_0_reset_queue_mmio(mes, input->queue_type, 889 input->me_id, input->pipe_id, 890 input->queue_id, input->vmid); 891 892 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 893 894 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 895 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 896 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 897 898 mes_reset_queue_pkt.queue_type = 899 convert_to_mes_queue_type(input->queue_type); 900 901 if (input->legacy_gfx) { 902 mes_reset_queue_pkt.reset_legacy_gfx = 1; 903 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 904 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 905 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 906 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 907 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 908 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 909 } else { 910 mes_reset_queue_pkt.reset_queue_only = 1; 911 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 912 } 913 914 if (input->is_kq) 915 pipe = AMDGPU_MES_KIQ_PIPE; 916 else 917 pipe = AMDGPU_MES_SCHED_PIPE; 918 919 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 920 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 921 offsetof(union MESAPI__RESET, api_status)); 922 } 923 924 static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 925 struct mes_detect_and_reset_queue_input *input) 926 { 927 union MESAPI__RESET mes_reset_queue_pkt; 928 929 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 930 931 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 932 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 933 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 934 935 mes_reset_queue_pkt.queue_type = 936 convert_to_mes_queue_type(input->queue_type); 937 mes_reset_queue_pkt.doorbell_offset_addr = 938 mes->hung_queue_db_array_gpu_addr; 939 940 if (input->detect_only) 941 mes_reset_queue_pkt.hang_detect_only = 1; 942 else 943 mes_reset_queue_pkt.hang_detect_then_reset = 1; 944 945 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 946 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 947 offsetof(union MESAPI__RESET, api_status)); 948 } 949 950 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 951 { 952 /* 953 * MES doesn't support invalidate gc_hub on slave xcc individually 954 * master xcc will invalidate all gc_hub for the partition 955 */ 956 if (AMDGPU_IS_GFXHUB(id)) 957 return 0; 958 else if (AMDGPU_IS_MMHUB0(id)) 959 return 1; 960 else 961 return -EINVAL; 962 963 } 964 965 static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, 966 struct mes_inv_tlbs_pasid_input *input) 967 { 968 union MESAPI__INV_TLBS mes_inv_tlbs; 969 int ret; 970 971 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 972 973 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 974 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 975 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 976 977 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 978 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 979 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 980 981 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 982 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 983 if (ret < 0) 984 return -EINVAL; 985 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 986 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, 987 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 988 offsetof(union MESAPI__INV_TLBS, api_status)); 989 990 } 991 992 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 993 .add_hw_queue = mes_v12_0_add_hw_queue, 994 .remove_hw_queue = mes_v12_0_remove_hw_queue, 995 .map_legacy_queue = mes_v12_0_map_legacy_queue, 996 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 997 .suspend_gang = mes_v12_0_suspend_gang, 998 .resume_gang = mes_v12_0_resume_gang, 999 .misc_op = mes_v12_0_misc_op, 1000 .reset_hw_queue = mes_v12_0_reset_hw_queue, 1001 .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, 1002 .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, 1003 }; 1004 1005 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1006 enum amdgpu_mes_pipe pipe) 1007 { 1008 int r; 1009 const struct mes_firmware_header_v1_0 *mes_hdr; 1010 const __le32 *fw_data; 1011 unsigned fw_size; 1012 1013 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1014 adev->mes.fw[pipe]->data; 1015 1016 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1017 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1018 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1019 1020 r = amdgpu_bo_create_reserved(adev, fw_size, 1021 PAGE_SIZE, 1022 AMDGPU_GEM_DOMAIN_VRAM, 1023 &adev->mes.ucode_fw_obj[pipe], 1024 &adev->mes.ucode_fw_gpu_addr[pipe], 1025 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1026 if (r) { 1027 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1028 return r; 1029 } 1030 1031 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1032 1033 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1034 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1035 1036 return 0; 1037 } 1038 1039 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1040 enum amdgpu_mes_pipe pipe) 1041 { 1042 int r; 1043 const struct mes_firmware_header_v1_0 *mes_hdr; 1044 const __le32 *fw_data; 1045 unsigned fw_size; 1046 1047 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1048 adev->mes.fw[pipe]->data; 1049 1050 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1051 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1052 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1053 1054 r = amdgpu_bo_create_reserved(adev, fw_size, 1055 64 * 1024, 1056 AMDGPU_GEM_DOMAIN_VRAM, 1057 &adev->mes.data_fw_obj[pipe], 1058 &adev->mes.data_fw_gpu_addr[pipe], 1059 (void **)&adev->mes.data_fw_ptr[pipe]); 1060 if (r) { 1061 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1062 return r; 1063 } 1064 1065 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1066 1067 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1068 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1069 1070 return 0; 1071 } 1072 1073 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 1074 enum amdgpu_mes_pipe pipe) 1075 { 1076 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1077 &adev->mes.data_fw_gpu_addr[pipe], 1078 (void **)&adev->mes.data_fw_ptr[pipe]); 1079 1080 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1081 &adev->mes.ucode_fw_gpu_addr[pipe], 1082 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1083 } 1084 1085 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 1086 { 1087 uint64_t ucode_addr; 1088 uint32_t pipe, data = 0; 1089 1090 if (enable) { 1091 mutex_lock(&adev->srbm_mutex); 1092 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1093 soc21_grbm_select(adev, 3, pipe, 0, 0); 1094 if (amdgpu_mes_log_enable) { 1095 u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1096 /* In case uni mes is not enabled, only program for pipe 0 */ 1097 if (adev->mes.event_log_size >= (pipe + 1) * log_size) { 1098 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1099 lower_32_bits(adev->mes.event_log_gpu_addr + 1100 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1101 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1102 upper_32_bits(adev->mes.event_log_gpu_addr + 1103 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1104 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1105 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1106 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1107 } 1108 } 1109 1110 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1111 if (pipe == 0) 1112 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1113 else 1114 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1115 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1116 1117 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1118 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1119 lower_32_bits(ucode_addr)); 1120 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1121 upper_32_bits(ucode_addr)); 1122 1123 /* unhalt MES and activate one pipe each loop */ 1124 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1125 if (pipe) 1126 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1127 dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data); 1128 1129 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1130 1131 } 1132 soc21_grbm_select(adev, 0, 0, 0, 0); 1133 mutex_unlock(&adev->srbm_mutex); 1134 1135 if (amdgpu_emu_mode) 1136 msleep(100); 1137 else if (adev->enable_uni_mes) 1138 udelay(500); 1139 else 1140 udelay(50); 1141 } else { 1142 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1143 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1144 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1145 data = REG_SET_FIELD(data, CP_MES_CNTL, 1146 MES_INVALIDATE_ICACHE, 1); 1147 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1148 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1149 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1150 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1151 } 1152 } 1153 1154 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 1155 { 1156 uint64_t ucode_addr; 1157 int pipe; 1158 1159 mes_v12_0_enable(adev, false); 1160 1161 mutex_lock(&adev->srbm_mutex); 1162 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1163 /* me=3, queue=0 */ 1164 soc21_grbm_select(adev, 3, pipe, 0, 0); 1165 1166 /* set ucode start address */ 1167 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1168 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1169 lower_32_bits(ucode_addr)); 1170 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1171 upper_32_bits(ucode_addr)); 1172 1173 soc21_grbm_select(adev, 0, 0, 0, 0); 1174 } 1175 mutex_unlock(&adev->srbm_mutex); 1176 } 1177 1178 /* This function is for backdoor MES firmware */ 1179 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 1180 enum amdgpu_mes_pipe pipe, bool prime_icache) 1181 { 1182 int r; 1183 uint32_t data; 1184 1185 mes_v12_0_enable(adev, false); 1186 1187 if (!adev->mes.fw[pipe]) 1188 return -EINVAL; 1189 1190 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 1191 if (r) 1192 return r; 1193 1194 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 1195 if (r) { 1196 mes_v12_0_free_ucode_buffers(adev, pipe); 1197 return r; 1198 } 1199 1200 mutex_lock(&adev->srbm_mutex); 1201 /* me=3, pipe=0, queue=0 */ 1202 soc21_grbm_select(adev, 3, pipe, 0, 0); 1203 1204 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1205 1206 /* set ucode fimrware address */ 1207 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1208 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1209 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1210 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1211 1212 /* set ucode instruction cache boundary to 2M-1 */ 1213 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1214 1215 /* set ucode data firmware address */ 1216 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1217 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1218 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1219 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1220 1221 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1222 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1223 1224 if (prime_icache) { 1225 /* invalidate ICACHE */ 1226 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1227 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1228 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1229 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1230 1231 /* prime the ICACHE. */ 1232 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1233 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1234 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1235 } 1236 1237 soc21_grbm_select(adev, 0, 0, 0, 0); 1238 mutex_unlock(&adev->srbm_mutex); 1239 1240 return 0; 1241 } 1242 1243 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 1244 enum amdgpu_mes_pipe pipe) 1245 { 1246 int r; 1247 u32 *eop; 1248 1249 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1250 AMDGPU_GEM_DOMAIN_GTT, 1251 &adev->mes.eop_gpu_obj[pipe], 1252 &adev->mes.eop_gpu_addr[pipe], 1253 (void **)&eop); 1254 if (r) { 1255 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1256 return r; 1257 } 1258 1259 memset(eop, 0, 1260 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1261 1262 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1263 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1264 1265 return 0; 1266 } 1267 1268 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 1269 { 1270 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1271 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1272 uint32_t tmp; 1273 1274 mqd->header = 0xC0310800; 1275 mqd->compute_pipelinestat_enable = 0x00000001; 1276 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1277 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1278 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1279 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1280 mqd->compute_misc_reserved = 0x00000007; 1281 1282 eop_base_addr = ring->eop_gpu_addr >> 8; 1283 1284 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1285 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1286 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1287 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1288 1289 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1290 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1291 mqd->cp_hqd_eop_control = tmp; 1292 1293 /* disable the queue if it's active */ 1294 ring->wptr = 0; 1295 mqd->cp_hqd_pq_rptr = 0; 1296 mqd->cp_hqd_pq_wptr_lo = 0; 1297 mqd->cp_hqd_pq_wptr_hi = 0; 1298 1299 /* set the pointer to the MQD */ 1300 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1301 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1302 1303 /* set MQD vmid to 0 */ 1304 tmp = regCP_MQD_CONTROL_DEFAULT; 1305 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1306 mqd->cp_mqd_control = tmp; 1307 1308 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1309 hqd_gpu_addr = ring->gpu_addr >> 8; 1310 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1311 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1312 1313 /* set the wb address whether it's enabled or not */ 1314 wb_gpu_addr = ring->rptr_gpu_addr; 1315 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1316 mqd->cp_hqd_pq_rptr_report_addr_hi = 1317 upper_32_bits(wb_gpu_addr) & 0xffff; 1318 1319 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1320 wb_gpu_addr = ring->wptr_gpu_addr; 1321 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1322 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1323 1324 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1325 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1326 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1327 (order_base_2(ring->ring_size / 4) - 1)); 1328 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1329 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1330 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1331 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1332 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1333 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1334 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1335 mqd->cp_hqd_pq_control = tmp; 1336 1337 /* enable doorbell */ 1338 tmp = 0; 1339 if (ring->use_doorbell) { 1340 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1341 DOORBELL_OFFSET, ring->doorbell_index); 1342 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1343 DOORBELL_EN, 1); 1344 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1345 DOORBELL_SOURCE, 0); 1346 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1347 DOORBELL_HIT, 0); 1348 } else { 1349 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1350 DOORBELL_EN, 0); 1351 } 1352 mqd->cp_hqd_pq_doorbell_control = tmp; 1353 1354 mqd->cp_hqd_vmid = 0; 1355 /* activate the queue */ 1356 mqd->cp_hqd_active = 1; 1357 1358 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1359 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1360 PRELOAD_SIZE, 0x55); 1361 mqd->cp_hqd_persistent_state = tmp; 1362 1363 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1364 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1365 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1366 1367 /* 1368 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1369 * doorbell handling. This is a reserved CP internal register can 1370 * not be accesss by others 1371 */ 1372 mqd->reserved_184 = BIT(15); 1373 1374 return 0; 1375 } 1376 1377 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1378 { 1379 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1380 struct amdgpu_device *adev = ring->adev; 1381 uint32_t data = 0; 1382 1383 mutex_lock(&adev->srbm_mutex); 1384 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1385 1386 /* set CP_HQD_VMID.VMID = 0. */ 1387 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1388 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1389 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1390 1391 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1392 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1393 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1394 DOORBELL_EN, 0); 1395 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1396 1397 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1398 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1399 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1400 1401 /* set CP_MQD_CONTROL.VMID=0 */ 1402 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1403 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1404 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1405 1406 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1407 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1408 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1409 1410 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1411 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1412 mqd->cp_hqd_pq_rptr_report_addr_lo); 1413 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1414 mqd->cp_hqd_pq_rptr_report_addr_hi); 1415 1416 /* set CP_HQD_PQ_CONTROL */ 1417 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1418 1419 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1420 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1421 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1422 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1423 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1424 1425 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1426 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1427 mqd->cp_hqd_pq_doorbell_control); 1428 1429 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1430 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1431 1432 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1433 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1434 1435 soc21_grbm_select(adev, 0, 0, 0, 0); 1436 mutex_unlock(&adev->srbm_mutex); 1437 } 1438 1439 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1440 { 1441 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1442 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1443 int r; 1444 1445 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1446 return -EINVAL; 1447 1448 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1449 if (r) { 1450 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1451 return r; 1452 } 1453 1454 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1455 1456 r = amdgpu_ring_test_ring(kiq_ring); 1457 if (r) { 1458 DRM_ERROR("kfq enable failed\n"); 1459 kiq_ring->sched.ready = false; 1460 } 1461 return r; 1462 } 1463 1464 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1465 enum amdgpu_mes_pipe pipe) 1466 { 1467 struct amdgpu_ring *ring; 1468 int r; 1469 1470 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1471 ring = &adev->gfx.kiq[0].ring; 1472 else 1473 ring = &adev->mes.ring[pipe]; 1474 1475 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1476 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1477 *(ring->wptr_cpu_addr) = 0; 1478 *(ring->rptr_cpu_addr) = 0; 1479 amdgpu_ring_clear_ring(ring); 1480 } 1481 1482 r = mes_v12_0_mqd_init(ring); 1483 if (r) 1484 return r; 1485 1486 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1487 if (adev->enable_uni_mes) 1488 r = amdgpu_mes_map_legacy_queue(adev, ring); 1489 else 1490 r = mes_v12_0_kiq_enable_queue(adev); 1491 if (r) 1492 return r; 1493 } else { 1494 mes_v12_0_queue_init_register(ring); 1495 } 1496 1497 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) || 1498 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) { 1499 /* get MES scheduler/KIQ versions */ 1500 mutex_lock(&adev->srbm_mutex); 1501 soc21_grbm_select(adev, 3, pipe, 0, 0); 1502 1503 if (pipe == AMDGPU_MES_SCHED_PIPE) 1504 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1505 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1506 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1507 1508 soc21_grbm_select(adev, 0, 0, 0, 0); 1509 mutex_unlock(&adev->srbm_mutex); 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1516 { 1517 struct amdgpu_ring *ring; 1518 1519 ring = &adev->mes.ring[pipe]; 1520 1521 ring->funcs = &mes_v12_0_ring_funcs; 1522 1523 ring->me = 3; 1524 ring->pipe = pipe; 1525 ring->queue = 0; 1526 1527 ring->ring_obj = NULL; 1528 ring->use_doorbell = true; 1529 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1530 ring->no_scheduler = true; 1531 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1532 1533 if (pipe == AMDGPU_MES_SCHED_PIPE) 1534 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1535 else 1536 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1537 1538 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1539 AMDGPU_RING_PRIO_DEFAULT, NULL); 1540 } 1541 1542 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1543 { 1544 struct amdgpu_ring *ring; 1545 1546 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1547 1548 ring = &adev->gfx.kiq[0].ring; 1549 1550 ring->me = 3; 1551 ring->pipe = 1; 1552 ring->queue = 0; 1553 1554 ring->adev = NULL; 1555 ring->ring_obj = NULL; 1556 ring->use_doorbell = true; 1557 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1558 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1559 ring->no_scheduler = true; 1560 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1561 ring->me, ring->pipe, ring->queue); 1562 1563 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1564 AMDGPU_RING_PRIO_DEFAULT, NULL); 1565 } 1566 1567 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1568 enum amdgpu_mes_pipe pipe) 1569 { 1570 int r, mqd_size = sizeof(struct v12_compute_mqd); 1571 struct amdgpu_ring *ring; 1572 1573 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1574 ring = &adev->gfx.kiq[0].ring; 1575 else 1576 ring = &adev->mes.ring[pipe]; 1577 1578 if (ring->mqd_obj) 1579 return 0; 1580 1581 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1582 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1583 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1584 if (r) { 1585 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1586 return r; 1587 } 1588 1589 memset(ring->mqd_ptr, 0, mqd_size); 1590 1591 /* prepare MQD backup */ 1592 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1593 if (!adev->mes.mqd_backup[pipe]) 1594 dev_warn(adev->dev, 1595 "no memory to create MQD backup for ring %s\n", 1596 ring->name); 1597 1598 return 0; 1599 } 1600 1601 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1602 { 1603 struct amdgpu_device *adev = ip_block->adev; 1604 int pipe, r; 1605 1606 adev->mes.funcs = &mes_v12_0_funcs; 1607 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1608 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1609 adev->mes.enable_legacy_queue_map = true; 1610 1611 adev->mes.event_log_size = adev->enable_uni_mes ? 1612 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : 1613 (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 1614 r = amdgpu_mes_init(adev); 1615 if (r) 1616 return r; 1617 1618 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1619 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1620 if (r) 1621 return r; 1622 1623 r = mes_v12_0_mqd_sw_init(adev, pipe); 1624 if (r) 1625 return r; 1626 1627 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) { 1628 r = mes_v12_0_kiq_ring_init(adev); 1629 } 1630 else { 1631 r = mes_v12_0_ring_init(adev, pipe); 1632 if (r) 1633 return r; 1634 r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1635 AMDGPU_GEM_DOMAIN_VRAM, 1636 &adev->mes.resource_1[pipe], 1637 &adev->mes.resource_1_gpu_addr[pipe], 1638 &adev->mes.resource_1_addr[pipe]); 1639 if (r) { 1640 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe); 1641 return r; 1642 } 1643 } 1644 } 1645 1646 return 0; 1647 } 1648 1649 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1650 { 1651 struct amdgpu_device *adev = ip_block->adev; 1652 int pipe; 1653 1654 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1655 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], 1656 &adev->mes.resource_1_gpu_addr[pipe], 1657 &adev->mes.resource_1_addr[pipe]); 1658 1659 kfree(adev->mes.mqd_backup[pipe]); 1660 1661 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1662 &adev->mes.eop_gpu_addr[pipe], 1663 NULL); 1664 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1665 1666 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1667 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1668 &adev->mes.ring[pipe].mqd_gpu_addr, 1669 &adev->mes.ring[pipe].mqd_ptr); 1670 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1671 } 1672 } 1673 1674 if (!adev->enable_uni_mes) { 1675 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1676 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1677 &adev->gfx.kiq[0].ring.mqd_ptr); 1678 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1679 } 1680 1681 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1682 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1683 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1684 } 1685 1686 amdgpu_mes_fini(adev); 1687 return 0; 1688 } 1689 1690 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1691 { 1692 uint32_t data; 1693 int i; 1694 1695 mutex_lock(&adev->srbm_mutex); 1696 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1697 1698 /* disable the queue if it's active */ 1699 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1700 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1701 for (i = 0; i < adev->usec_timeout; i++) { 1702 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1703 break; 1704 udelay(1); 1705 } 1706 } 1707 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1708 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1709 DOORBELL_EN, 0); 1710 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1711 DOORBELL_HIT, 1); 1712 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1713 1714 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1715 1716 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1717 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1718 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1719 1720 soc21_grbm_select(adev, 0, 0, 0, 0); 1721 mutex_unlock(&adev->srbm_mutex); 1722 1723 adev->mes.ring[0].sched.ready = false; 1724 } 1725 1726 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1727 { 1728 uint32_t tmp; 1729 struct amdgpu_device *adev = ring->adev; 1730 1731 /* tell RLC which is KIQ queue */ 1732 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1733 tmp &= 0xffffff00; 1734 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1735 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1736 } 1737 1738 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1739 { 1740 int r = 0; 1741 struct amdgpu_ip_block *ip_block; 1742 1743 if (adev->enable_uni_mes) 1744 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1745 else 1746 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1747 1748 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1749 1750 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1751 if (r) { 1752 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1753 return r; 1754 } 1755 1756 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1757 if (r) { 1758 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1759 return r; 1760 } 1761 1762 mes_v12_0_set_ucode_start_addr(adev); 1763 1764 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1765 mes_v12_0_set_ucode_start_addr(adev); 1766 1767 mes_v12_0_enable(adev, true); 1768 1769 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1770 if (unlikely(!ip_block)) { 1771 dev_err(adev->dev, "Failed to get MES handle\n"); 1772 return -EINVAL; 1773 } 1774 1775 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1776 if (r) 1777 goto failure; 1778 1779 if (adev->enable_uni_mes) { 1780 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1781 if (r) 1782 goto failure; 1783 1784 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1785 } 1786 1787 if (adev->mes.enable_legacy_queue_map) { 1788 r = mes_v12_0_hw_init(ip_block); 1789 if (r) 1790 goto failure; 1791 } 1792 1793 return r; 1794 1795 failure: 1796 mes_v12_0_hw_fini(ip_block); 1797 return r; 1798 } 1799 1800 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1801 { 1802 if (adev->mes.ring[0].sched.ready) { 1803 if (adev->enable_uni_mes) 1804 amdgpu_mes_unmap_legacy_queue(adev, 1805 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 1806 RESET_QUEUES, 0, 0); 1807 else 1808 mes_v12_0_kiq_dequeue_sched(adev); 1809 1810 adev->mes.ring[0].sched.ready = false; 1811 } 1812 1813 mes_v12_0_enable(adev, false); 1814 1815 return 0; 1816 } 1817 1818 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 1819 { 1820 int r; 1821 struct amdgpu_device *adev = ip_block->adev; 1822 1823 if (adev->mes.ring[0].sched.ready) 1824 goto out; 1825 1826 if (!adev->enable_mes_kiq) { 1827 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1828 r = mes_v12_0_load_microcode(adev, 1829 AMDGPU_MES_SCHED_PIPE, true); 1830 if (r) { 1831 DRM_ERROR("failed to MES fw, r=%d\n", r); 1832 return r; 1833 } 1834 1835 mes_v12_0_set_ucode_start_addr(adev); 1836 1837 } else if (adev->firmware.load_type == 1838 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1839 1840 mes_v12_0_set_ucode_start_addr(adev); 1841 } 1842 1843 mes_v12_0_enable(adev, true); 1844 } 1845 1846 /* Enable the MES to handle doorbell ring on unmapped queue */ 1847 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1848 1849 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1850 if (r) 1851 goto failure; 1852 1853 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1854 if (r) 1855 goto failure; 1856 1857 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b) 1858 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1859 1860 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1861 1862 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1863 if (r) { 1864 DRM_ERROR("MES is busy\n"); 1865 goto failure; 1866 } 1867 1868 r = amdgpu_mes_update_enforce_isolation(adev); 1869 if (r) 1870 goto failure; 1871 1872 out: 1873 /* 1874 * Disable KIQ ring usage from the driver once MES is enabled. 1875 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1876 * with MES enabled. 1877 */ 1878 adev->gfx.kiq[0].ring.sched.ready = false; 1879 adev->mes.ring[0].sched.ready = true; 1880 1881 return 0; 1882 1883 failure: 1884 mes_v12_0_hw_fini(ip_block); 1885 return r; 1886 } 1887 1888 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 1889 { 1890 return 0; 1891 } 1892 1893 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) 1894 { 1895 return mes_v12_0_hw_fini(ip_block); 1896 } 1897 1898 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) 1899 { 1900 return mes_v12_0_hw_init(ip_block); 1901 } 1902 1903 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) 1904 { 1905 struct amdgpu_device *adev = ip_block->adev; 1906 int pipe, r; 1907 1908 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1909 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 1910 1911 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1912 r = amdgpu_mes_init_microcode(adev, pipe); 1913 if (r) 1914 return r; 1915 } 1916 1917 return 0; 1918 } 1919 1920 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1921 .name = "mes_v12_0", 1922 .early_init = mes_v12_0_early_init, 1923 .late_init = NULL, 1924 .sw_init = mes_v12_0_sw_init, 1925 .sw_fini = mes_v12_0_sw_fini, 1926 .hw_init = mes_v12_0_hw_init, 1927 .hw_fini = mes_v12_0_hw_fini, 1928 .suspend = mes_v12_0_suspend, 1929 .resume = mes_v12_0_resume, 1930 }; 1931 1932 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1933 .type = AMD_IP_BLOCK_TYPE_MES, 1934 .major = 12, 1935 .minor = 0, 1936 .rev = 0, 1937 .funcs = &mes_v12_0_ip_funcs, 1938 }; 1939