1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_12_0_0_offset.h" 30 #include "gc/gc_12_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 41 42 static int mes_v12_0_hw_init(void *handle); 43 static int mes_v12_0_hw_fini(void *handle); 44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v12_0_ring_get_rptr, 84 .get_wptr = mes_v12_0_ring_get_wptr, 85 .set_wptr = mes_v12_0_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static const char *mes_v12_0_opcodes[] = { 90 "SET_HW_RSRC", 91 "SET_SCHEDULING_CONFIG", 92 "ADD_QUEUE", 93 "REMOVE_QUEUE", 94 "PERFORM_YIELD", 95 "SET_GANG_PRIORITY_LEVEL", 96 "SUSPEND", 97 "RESUME", 98 "RESET", 99 "SET_LOG_BUFFER", 100 "CHANGE_GANG_PRORITY", 101 "QUERY_SCHEDULER_STATUS", 102 "unused", 103 "SET_DEBUG_VMID", 104 "MISC", 105 "UPDATE_ROOT_PAGE_TABLE", 106 "AMD_LOG", 107 "SET_SE_MODE", 108 "SET_GANG_SUBMIT", 109 "SET_HW_RSRC_1", 110 }; 111 112 static const char *mes_v12_0_misc_opcodes[] = { 113 "WRITE_REG", 114 "INV_GART", 115 "QUERY_STATUS", 116 "READ_REG", 117 "WAIT_REG_MEM", 118 "SET_SHADER_DEBUGGER", 119 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 120 "NOTIFY_TO_UNMAP_PROCESSES", 121 }; 122 123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 124 { 125 const char *op_str = NULL; 126 127 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 128 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 129 130 return op_str; 131 } 132 133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 134 { 135 const char *op_str = NULL; 136 137 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 138 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 139 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 140 141 return op_str; 142 } 143 144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 145 void *pkt, int size, 146 int api_status_off) 147 { 148 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 149 signed long timeout = 3000000; /* 3000 ms */ 150 struct amdgpu_device *adev = mes->adev; 151 struct amdgpu_ring *ring = &mes->ring; 152 struct MES_API_STATUS *api_status; 153 union MESAPI__MISC *x_pkt = pkt; 154 const char *op_str, *misc_op_str; 155 unsigned long flags; 156 u64 status_gpu_addr; 157 u32 status_offset; 158 u64 *status_ptr; 159 signed long r; 160 int ret; 161 162 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 163 return -EINVAL; 164 165 if (amdgpu_emu_mode) { 166 timeout *= 100; 167 } else if (amdgpu_sriov_vf(adev)) { 168 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 169 timeout = 15 * 600 * 1000; 170 } 171 172 ret = amdgpu_device_wb_get(adev, &status_offset); 173 if (ret) 174 return ret; 175 176 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 177 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 178 *status_ptr = 0; 179 180 spin_lock_irqsave(&mes->ring_lock, flags); 181 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 182 if (r) 183 goto error_unlock_free; 184 185 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 186 api_status->api_completion_fence_addr = status_gpu_addr; 187 api_status->api_completion_fence_value = 1; 188 189 amdgpu_ring_write_multiple(ring, pkt, size / 4); 190 191 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 192 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 193 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 194 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 195 mes_status_pkt.api_status.api_completion_fence_addr = 196 ring->fence_drv.gpu_addr; 197 mes_status_pkt.api_status.api_completion_fence_value = 198 ++ring->fence_drv.sync_seq; 199 200 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 201 sizeof(mes_status_pkt) / 4); 202 203 amdgpu_ring_commit(ring); 204 spin_unlock_irqrestore(&mes->ring_lock, flags); 205 206 op_str = mes_v12_0_get_op_string(x_pkt); 207 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 208 209 if (misc_op_str) 210 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 211 misc_op_str); 212 else if (op_str) 213 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 214 else 215 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 216 x_pkt->header.opcode); 217 218 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, timeout); 219 if (r < 1 || !*status_ptr) { 220 221 if (misc_op_str) 222 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 223 op_str, misc_op_str); 224 else if (op_str) 225 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 226 op_str); 227 else 228 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 229 x_pkt->header.opcode); 230 231 while (halt_if_hws_hang) 232 schedule(); 233 234 r = -ETIMEDOUT; 235 goto error_wb_free; 236 } 237 238 amdgpu_device_wb_free(adev, status_offset); 239 return 0; 240 241 error_unlock_free: 242 spin_unlock_irqrestore(&mes->ring_lock, flags); 243 244 error_wb_free: 245 amdgpu_device_wb_free(adev, status_offset); 246 return r; 247 } 248 249 static int convert_to_mes_queue_type(int queue_type) 250 { 251 if (queue_type == AMDGPU_RING_TYPE_GFX) 252 return MES_QUEUE_TYPE_GFX; 253 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 254 return MES_QUEUE_TYPE_COMPUTE; 255 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 256 return MES_QUEUE_TYPE_SDMA; 257 else 258 BUG(); 259 return -1; 260 } 261 262 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 263 struct mes_add_queue_input *input) 264 { 265 struct amdgpu_device *adev = mes->adev; 266 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 267 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 268 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 269 270 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 271 272 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 273 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 274 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 275 276 mes_add_queue_pkt.process_id = input->process_id; 277 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 278 mes_add_queue_pkt.process_va_start = input->process_va_start; 279 mes_add_queue_pkt.process_va_end = input->process_va_end; 280 mes_add_queue_pkt.process_quantum = input->process_quantum; 281 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 282 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 283 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 284 mes_add_queue_pkt.inprocess_gang_priority = 285 input->inprocess_gang_priority; 286 mes_add_queue_pkt.gang_global_priority_level = 287 input->gang_global_priority_level; 288 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 289 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 290 291 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 292 293 mes_add_queue_pkt.queue_type = 294 convert_to_mes_queue_type(input->queue_type); 295 mes_add_queue_pkt.paging = input->paging; 296 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 297 mes_add_queue_pkt.gws_base = input->gws_base; 298 mes_add_queue_pkt.gws_size = input->gws_size; 299 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 300 mes_add_queue_pkt.tma_addr = input->tma_addr; 301 mes_add_queue_pkt.trap_en = input->trap_en; 302 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 303 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 304 305 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 306 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 307 mes_add_queue_pkt.gds_size = input->queue_size; 308 309 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 310 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 311 mes_add_queue_pkt.gds_size = input->queue_size; 312 313 return mes_v12_0_submit_pkt_and_poll_completion(mes, 314 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 315 offsetof(union MESAPI__ADD_QUEUE, api_status)); 316 } 317 318 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 319 struct mes_remove_queue_input *input) 320 { 321 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 322 323 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 324 325 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 326 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 327 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 328 329 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 330 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 331 332 return mes_v12_0_submit_pkt_and_poll_completion(mes, 333 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 334 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 335 } 336 337 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 338 struct mes_map_legacy_queue_input *input) 339 { 340 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 341 342 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 343 344 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 345 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 346 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 347 348 mes_add_queue_pkt.pipe_id = input->pipe_id; 349 mes_add_queue_pkt.queue_id = input->queue_id; 350 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 351 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 352 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 353 mes_add_queue_pkt.queue_type = 354 convert_to_mes_queue_type(input->queue_type); 355 mes_add_queue_pkt.map_legacy_kq = 1; 356 357 return mes_v12_0_submit_pkt_and_poll_completion(mes, 358 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 359 offsetof(union MESAPI__ADD_QUEUE, api_status)); 360 } 361 362 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 363 struct mes_unmap_legacy_queue_input *input) 364 { 365 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 366 367 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 368 369 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 370 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 371 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 372 373 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 374 mes_remove_queue_pkt.gang_context_addr = 0; 375 376 mes_remove_queue_pkt.pipe_id = input->pipe_id; 377 mes_remove_queue_pkt.queue_id = input->queue_id; 378 379 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 380 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 381 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 382 mes_remove_queue_pkt.tf_data = 383 lower_32_bits(input->trail_fence_data); 384 } else { 385 mes_remove_queue_pkt.unmap_legacy_queue = 1; 386 mes_remove_queue_pkt.queue_type = 387 convert_to_mes_queue_type(input->queue_type); 388 } 389 390 return mes_v12_0_submit_pkt_and_poll_completion(mes, 391 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 392 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 393 } 394 395 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 396 struct mes_suspend_gang_input *input) 397 { 398 return 0; 399 } 400 401 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 402 struct mes_resume_gang_input *input) 403 { 404 return 0; 405 } 406 407 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes) 408 { 409 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 410 411 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 412 413 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 414 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 415 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 416 417 return mes_v12_0_submit_pkt_and_poll_completion(mes, 418 &mes_status_pkt, sizeof(mes_status_pkt), 419 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 420 } 421 422 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 423 struct mes_misc_op_input *input) 424 { 425 union MESAPI__MISC misc_pkt; 426 427 memset(&misc_pkt, 0, sizeof(misc_pkt)); 428 429 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 430 misc_pkt.header.opcode = MES_SCH_API_MISC; 431 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 432 433 switch (input->op) { 434 case MES_MISC_OP_READ_REG: 435 misc_pkt.opcode = MESAPI_MISC__READ_REG; 436 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 437 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 438 break; 439 case MES_MISC_OP_WRITE_REG: 440 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 441 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 442 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 443 break; 444 case MES_MISC_OP_WRM_REG_WAIT: 445 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 446 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 447 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 448 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 449 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 450 misc_pkt.wait_reg_mem.reg_offset2 = 0; 451 break; 452 case MES_MISC_OP_WRM_REG_WR_WAIT: 453 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 454 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 455 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 456 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 457 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 458 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 459 break; 460 case MES_MISC_OP_SET_SHADER_DEBUGGER: 461 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 462 misc_pkt.set_shader_debugger.process_context_addr = 463 input->set_shader_debugger.process_context_addr; 464 misc_pkt.set_shader_debugger.flags.u32all = 465 input->set_shader_debugger.flags.u32all; 466 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 467 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 468 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 469 input->set_shader_debugger.tcp_watch_cntl, 470 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 471 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 472 break; 473 default: 474 DRM_ERROR("unsupported misc op (%d) \n", input->op); 475 return -EINVAL; 476 } 477 478 return mes_v12_0_submit_pkt_and_poll_completion(mes, 479 &misc_pkt, sizeof(misc_pkt), 480 offsetof(union MESAPI__MISC, api_status)); 481 } 482 483 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes) 484 { 485 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 486 487 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 488 489 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 490 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 491 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 492 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 493 494 return mes_v12_0_submit_pkt_and_poll_completion(mes, 495 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 496 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 497 } 498 499 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) 500 { 501 int i; 502 struct amdgpu_device *adev = mes->adev; 503 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 504 505 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 506 507 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 508 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 509 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 510 511 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 512 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 513 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 514 mes_set_hw_res_pkt.paging_vmid = 0; 515 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 516 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 517 mes->query_status_fence_gpu_addr; 518 519 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 520 mes_set_hw_res_pkt.compute_hqd_mask[i] = 521 mes->compute_hqd_mask[i]; 522 523 for (i = 0; i < MAX_GFX_PIPES; i++) 524 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 525 526 for (i = 0; i < MAX_SDMA_PIPES; i++) 527 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 528 529 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 530 mes_set_hw_res_pkt.aggregated_doorbells[i] = 531 mes->aggregated_doorbells[i]; 532 533 for (i = 0; i < 5; i++) { 534 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 535 mes_set_hw_res_pkt.mmhub_base[i] = 536 adev->reg_offset[MMHUB_HWIP][0][i]; 537 mes_set_hw_res_pkt.osssys_base[i] = 538 adev->reg_offset[OSSSYS_HWIP][0][i]; 539 } 540 541 mes_set_hw_res_pkt.disable_reset = 1; 542 mes_set_hw_res_pkt.disable_mes_log = 1; 543 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 544 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 545 546 /* 547 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 548 * handling support, other queue will not use the oversubscribe timer. 549 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 550 */ 551 mes_set_hw_res_pkt.oversubscription_timer = 50; 552 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 553 554 mes_set_hw_res_pkt.enable_mes_event_int_logging = 0; 555 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 556 557 return mes_v12_0_submit_pkt_and_poll_completion(mes, 558 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 559 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 560 } 561 562 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 563 { 564 struct amdgpu_device *adev = mes->adev; 565 uint32_t data; 566 567 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 568 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 569 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 570 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 571 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 572 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 573 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 574 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 575 576 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 577 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 578 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 579 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 580 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 581 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 582 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 583 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 584 585 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 586 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 587 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 588 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 589 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 590 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 591 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 592 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 593 594 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 595 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 596 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 597 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 598 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 599 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 600 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 601 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 602 603 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 604 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 605 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 606 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 607 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 608 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 609 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 610 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 611 612 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 613 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 614 } 615 616 617 static void mes_v12_0_enable_unmapped_doorbell_handling( 618 struct amdgpu_mes *mes, bool enable) 619 { 620 struct amdgpu_device *adev = mes->adev; 621 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 622 623 /* 624 * The default PROC_LSB settng is 0xc which means doorbell 625 * addr[16:12] gives the doorbell page number. For kfd, each 626 * process will use 2 pages of doorbell, we need to change the 627 * setting to 0xd 628 */ 629 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 630 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 631 632 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 633 634 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 635 } 636 637 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 638 .add_hw_queue = mes_v12_0_add_hw_queue, 639 .remove_hw_queue = mes_v12_0_remove_hw_queue, 640 .map_legacy_queue = mes_v12_0_map_legacy_queue, 641 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 642 .suspend_gang = mes_v12_0_suspend_gang, 643 .resume_gang = mes_v12_0_resume_gang, 644 .misc_op = mes_v12_0_misc_op, 645 }; 646 647 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 648 enum admgpu_mes_pipe pipe) 649 { 650 int r; 651 const struct mes_firmware_header_v1_0 *mes_hdr; 652 const __le32 *fw_data; 653 unsigned fw_size; 654 655 mes_hdr = (const struct mes_firmware_header_v1_0 *) 656 adev->mes.fw[pipe]->data; 657 658 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 659 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 660 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 661 662 r = amdgpu_bo_create_reserved(adev, fw_size, 663 PAGE_SIZE, 664 AMDGPU_GEM_DOMAIN_VRAM, 665 &adev->mes.ucode_fw_obj[pipe], 666 &adev->mes.ucode_fw_gpu_addr[pipe], 667 (void **)&adev->mes.ucode_fw_ptr[pipe]); 668 if (r) { 669 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 670 return r; 671 } 672 673 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 674 675 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 676 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 677 678 return 0; 679 } 680 681 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 682 enum admgpu_mes_pipe pipe) 683 { 684 int r; 685 const struct mes_firmware_header_v1_0 *mes_hdr; 686 const __le32 *fw_data; 687 unsigned fw_size; 688 689 mes_hdr = (const struct mes_firmware_header_v1_0 *) 690 adev->mes.fw[pipe]->data; 691 692 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 693 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 694 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 695 696 r = amdgpu_bo_create_reserved(adev, fw_size, 697 64 * 1024, 698 AMDGPU_GEM_DOMAIN_VRAM, 699 &adev->mes.data_fw_obj[pipe], 700 &adev->mes.data_fw_gpu_addr[pipe], 701 (void **)&adev->mes.data_fw_ptr[pipe]); 702 if (r) { 703 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 704 return r; 705 } 706 707 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 708 709 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 710 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 711 712 return 0; 713 } 714 715 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 716 enum admgpu_mes_pipe pipe) 717 { 718 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 719 &adev->mes.data_fw_gpu_addr[pipe], 720 (void **)&adev->mes.data_fw_ptr[pipe]); 721 722 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 723 &adev->mes.ucode_fw_gpu_addr[pipe], 724 (void **)&adev->mes.ucode_fw_ptr[pipe]); 725 } 726 727 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 728 { 729 uint64_t ucode_addr; 730 uint32_t pipe, data = 0; 731 732 if (enable) { 733 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 734 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 735 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 736 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 737 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 738 739 mutex_lock(&adev->srbm_mutex); 740 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 741 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 742 pipe == AMDGPU_MES_KIQ_PIPE) 743 continue; 744 745 soc21_grbm_select(adev, 3, pipe, 0, 0); 746 747 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 748 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 749 lower_32_bits(ucode_addr)); 750 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 751 upper_32_bits(ucode_addr)); 752 } 753 soc21_grbm_select(adev, 0, 0, 0, 0); 754 mutex_unlock(&adev->srbm_mutex); 755 756 /* unhalt MES and activate pipe0 */ 757 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 758 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 759 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 760 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 761 762 if (amdgpu_emu_mode) 763 msleep(100); 764 else if (adev->enable_uni_mes) 765 udelay(500); 766 else 767 udelay(50); 768 } else { 769 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 770 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 771 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 772 data = REG_SET_FIELD(data, CP_MES_CNTL, 773 MES_INVALIDATE_ICACHE, 1); 774 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 775 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 776 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 777 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 778 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 779 } 780 } 781 782 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 783 { 784 uint64_t ucode_addr; 785 int pipe; 786 787 mes_v12_0_enable(adev, false); 788 789 mutex_lock(&adev->srbm_mutex); 790 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 791 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 792 pipe == AMDGPU_MES_KIQ_PIPE) 793 continue; 794 795 /* me=3, queue=0 */ 796 soc21_grbm_select(adev, 3, pipe, 0, 0); 797 798 /* set ucode start address */ 799 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 800 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 801 lower_32_bits(ucode_addr)); 802 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 803 upper_32_bits(ucode_addr)); 804 805 soc21_grbm_select(adev, 0, 0, 0, 0); 806 } 807 mutex_unlock(&adev->srbm_mutex); 808 } 809 810 /* This function is for backdoor MES firmware */ 811 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 812 enum admgpu_mes_pipe pipe, bool prime_icache) 813 { 814 int r; 815 uint32_t data; 816 817 mes_v12_0_enable(adev, false); 818 819 if (!adev->mes.fw[pipe]) 820 return -EINVAL; 821 822 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 823 if (r) 824 return r; 825 826 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 827 if (r) { 828 mes_v12_0_free_ucode_buffers(adev, pipe); 829 return r; 830 } 831 832 mutex_lock(&adev->srbm_mutex); 833 /* me=3, pipe=0, queue=0 */ 834 soc21_grbm_select(adev, 3, pipe, 0, 0); 835 836 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 837 838 /* set ucode fimrware address */ 839 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 840 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 841 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 842 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 843 844 /* set ucode instruction cache boundary to 2M-1 */ 845 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 846 847 /* set ucode data firmware address */ 848 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 849 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 850 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 851 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 852 853 /* Set data cache boundary CP_MES_MDBOUND_LO */ 854 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 855 856 if (prime_icache) { 857 /* invalidate ICACHE */ 858 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 859 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 860 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 861 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 862 863 /* prime the ICACHE. */ 864 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 865 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 866 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 867 } 868 869 soc21_grbm_select(adev, 0, 0, 0, 0); 870 mutex_unlock(&adev->srbm_mutex); 871 872 return 0; 873 } 874 875 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 876 enum admgpu_mes_pipe pipe) 877 { 878 int r; 879 u32 *eop; 880 881 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 882 AMDGPU_GEM_DOMAIN_GTT, 883 &adev->mes.eop_gpu_obj[pipe], 884 &adev->mes.eop_gpu_addr[pipe], 885 (void **)&eop); 886 if (r) { 887 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 888 return r; 889 } 890 891 memset(eop, 0, 892 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 893 894 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 895 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 896 897 return 0; 898 } 899 900 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 901 { 902 struct v12_compute_mqd *mqd = ring->mqd_ptr; 903 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 904 uint32_t tmp; 905 906 mqd->header = 0xC0310800; 907 mqd->compute_pipelinestat_enable = 0x00000001; 908 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 909 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 910 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 911 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 912 mqd->compute_misc_reserved = 0x00000007; 913 914 eop_base_addr = ring->eop_gpu_addr >> 8; 915 916 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 917 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 918 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 919 (order_base_2(MES_EOP_SIZE / 4) - 1)); 920 921 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 922 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 923 mqd->cp_hqd_eop_control = tmp; 924 925 /* disable the queue if it's active */ 926 ring->wptr = 0; 927 mqd->cp_hqd_pq_rptr = 0; 928 mqd->cp_hqd_pq_wptr_lo = 0; 929 mqd->cp_hqd_pq_wptr_hi = 0; 930 931 /* set the pointer to the MQD */ 932 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 933 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 934 935 /* set MQD vmid to 0 */ 936 tmp = regCP_MQD_CONTROL_DEFAULT; 937 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 938 mqd->cp_mqd_control = tmp; 939 940 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 941 hqd_gpu_addr = ring->gpu_addr >> 8; 942 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 943 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 944 945 /* set the wb address whether it's enabled or not */ 946 wb_gpu_addr = ring->rptr_gpu_addr; 947 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 948 mqd->cp_hqd_pq_rptr_report_addr_hi = 949 upper_32_bits(wb_gpu_addr) & 0xffff; 950 951 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 952 wb_gpu_addr = ring->wptr_gpu_addr; 953 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 954 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 955 956 /* set up the HQD, this is similar to CP_RB0_CNTL */ 957 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 958 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 959 (order_base_2(ring->ring_size / 4) - 1)); 960 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 961 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 962 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 963 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 964 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 965 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 966 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 967 mqd->cp_hqd_pq_control = tmp; 968 969 /* enable doorbell */ 970 tmp = 0; 971 if (ring->use_doorbell) { 972 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 973 DOORBELL_OFFSET, ring->doorbell_index); 974 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 975 DOORBELL_EN, 1); 976 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 977 DOORBELL_SOURCE, 0); 978 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 979 DOORBELL_HIT, 0); 980 } else { 981 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 982 DOORBELL_EN, 0); 983 } 984 mqd->cp_hqd_pq_doorbell_control = tmp; 985 986 mqd->cp_hqd_vmid = 0; 987 /* activate the queue */ 988 mqd->cp_hqd_active = 1; 989 990 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 991 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 992 PRELOAD_SIZE, 0x55); 993 mqd->cp_hqd_persistent_state = tmp; 994 995 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 996 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 997 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 998 999 /* 1000 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1001 * doorbell handling. This is a reserved CP internal register can 1002 * not be accesss by others 1003 */ 1004 mqd->reserved_184 = BIT(15); 1005 1006 return 0; 1007 } 1008 1009 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1010 { 1011 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1012 struct amdgpu_device *adev = ring->adev; 1013 uint32_t data = 0; 1014 1015 mutex_lock(&adev->srbm_mutex); 1016 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1017 1018 /* set CP_HQD_VMID.VMID = 0. */ 1019 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1020 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1021 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1022 1023 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1024 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1025 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1026 DOORBELL_EN, 0); 1027 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1028 1029 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1030 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1031 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1032 1033 /* set CP_MQD_CONTROL.VMID=0 */ 1034 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1035 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1036 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1037 1038 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1039 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1040 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1041 1042 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1043 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1044 mqd->cp_hqd_pq_rptr_report_addr_lo); 1045 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1046 mqd->cp_hqd_pq_rptr_report_addr_hi); 1047 1048 /* set CP_HQD_PQ_CONTROL */ 1049 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1050 1051 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1052 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1053 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1054 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1055 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1056 1057 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1058 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1059 mqd->cp_hqd_pq_doorbell_control); 1060 1061 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1062 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1063 1064 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1065 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1066 1067 soc21_grbm_select(adev, 0, 0, 0, 0); 1068 mutex_unlock(&adev->srbm_mutex); 1069 } 1070 1071 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1072 { 1073 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1074 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1075 int r; 1076 1077 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1078 return -EINVAL; 1079 1080 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1081 if (r) { 1082 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1083 return r; 1084 } 1085 1086 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 1087 1088 r = amdgpu_ring_test_ring(kiq_ring); 1089 if (r) { 1090 DRM_ERROR("kfq enable failed\n"); 1091 kiq_ring->sched.ready = false; 1092 } 1093 return r; 1094 } 1095 1096 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1097 enum admgpu_mes_pipe pipe) 1098 { 1099 struct amdgpu_ring *ring; 1100 int r; 1101 1102 if (pipe == AMDGPU_MES_KIQ_PIPE) 1103 ring = &adev->gfx.kiq[0].ring; 1104 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1105 ring = &adev->mes.ring; 1106 else 1107 BUG(); 1108 1109 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1110 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1111 *(ring->wptr_cpu_addr) = 0; 1112 *(ring->rptr_cpu_addr) = 0; 1113 amdgpu_ring_clear_ring(ring); 1114 } 1115 1116 r = mes_v12_0_mqd_init(ring); 1117 if (r) 1118 return r; 1119 1120 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1121 if (adev->enable_uni_mes) { 1122 mes_v12_0_queue_init_register(ring); 1123 } else { 1124 r = mes_v12_0_kiq_enable_queue(adev); 1125 if (r) 1126 return r; 1127 } 1128 } else { 1129 mes_v12_0_queue_init_register(ring); 1130 } 1131 1132 /* get MES scheduler/KIQ versions */ 1133 mutex_lock(&adev->srbm_mutex); 1134 soc21_grbm_select(adev, 3, pipe, 0, 0); 1135 1136 if (pipe == AMDGPU_MES_SCHED_PIPE) 1137 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1138 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1139 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1140 1141 soc21_grbm_select(adev, 0, 0, 0, 0); 1142 mutex_unlock(&adev->srbm_mutex); 1143 1144 return 0; 1145 } 1146 1147 static int mes_v12_0_ring_init(struct amdgpu_device *adev) 1148 { 1149 struct amdgpu_ring *ring; 1150 1151 ring = &adev->mes.ring; 1152 1153 ring->funcs = &mes_v12_0_ring_funcs; 1154 1155 ring->me = 3; 1156 ring->pipe = 0; 1157 ring->queue = 0; 1158 1159 ring->ring_obj = NULL; 1160 ring->use_doorbell = true; 1161 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1162 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1163 ring->no_scheduler = true; 1164 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1165 1166 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1167 AMDGPU_RING_PRIO_DEFAULT, NULL); 1168 } 1169 1170 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1171 { 1172 struct amdgpu_ring *ring; 1173 1174 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1175 1176 ring = &adev->gfx.kiq[0].ring; 1177 1178 ring->me = 3; 1179 ring->pipe = adev->enable_uni_mes ? 0 : 1; 1180 ring->queue = 0; 1181 1182 ring->adev = NULL; 1183 ring->ring_obj = NULL; 1184 ring->use_doorbell = true; 1185 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1186 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1187 ring->no_scheduler = true; 1188 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1189 ring->me, ring->pipe, ring->queue); 1190 1191 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1192 AMDGPU_RING_PRIO_DEFAULT, NULL); 1193 } 1194 1195 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1196 enum admgpu_mes_pipe pipe) 1197 { 1198 int r, mqd_size = sizeof(struct v12_compute_mqd); 1199 struct amdgpu_ring *ring; 1200 1201 if (pipe == AMDGPU_MES_KIQ_PIPE) 1202 ring = &adev->gfx.kiq[0].ring; 1203 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1204 ring = &adev->mes.ring; 1205 else 1206 BUG(); 1207 1208 if (ring->mqd_obj) 1209 return 0; 1210 1211 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1212 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1213 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1214 if (r) { 1215 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1216 return r; 1217 } 1218 1219 memset(ring->mqd_ptr, 0, mqd_size); 1220 1221 /* prepare MQD backup */ 1222 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1223 if (!adev->mes.mqd_backup[pipe]) 1224 dev_warn(adev->dev, 1225 "no memory to create MQD backup for ring %s\n", 1226 ring->name); 1227 1228 return 0; 1229 } 1230 1231 static int mes_v12_0_sw_init(void *handle) 1232 { 1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1234 int pipe, r; 1235 1236 adev->mes.funcs = &mes_v12_0_funcs; 1237 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1238 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1239 1240 r = amdgpu_mes_init(adev); 1241 if (r) 1242 return r; 1243 1244 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1245 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1246 continue; 1247 1248 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1249 if (r) 1250 return r; 1251 1252 r = mes_v12_0_mqd_sw_init(adev, pipe); 1253 if (r) 1254 return r; 1255 } 1256 1257 if (adev->enable_mes_kiq) { 1258 r = mes_v12_0_kiq_ring_init(adev); 1259 if (r) 1260 return r; 1261 } 1262 1263 r = mes_v12_0_ring_init(adev); 1264 if (r) 1265 return r; 1266 1267 return 0; 1268 } 1269 1270 static int mes_v12_0_sw_fini(void *handle) 1271 { 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 int pipe; 1274 1275 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1276 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1277 1278 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1279 kfree(adev->mes.mqd_backup[pipe]); 1280 1281 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1282 &adev->mes.eop_gpu_addr[pipe], 1283 NULL); 1284 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1285 } 1286 1287 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1288 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1289 &adev->gfx.kiq[0].ring.mqd_ptr); 1290 1291 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1292 &adev->mes.ring.mqd_gpu_addr, 1293 &adev->mes.ring.mqd_ptr); 1294 1295 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1296 amdgpu_ring_fini(&adev->mes.ring); 1297 1298 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1299 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1300 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1301 } 1302 1303 amdgpu_mes_fini(adev); 1304 return 0; 1305 } 1306 1307 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1308 { 1309 uint32_t data; 1310 int i; 1311 1312 mutex_lock(&adev->srbm_mutex); 1313 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1314 1315 /* disable the queue if it's active */ 1316 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1317 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1318 for (i = 0; i < adev->usec_timeout; i++) { 1319 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1320 break; 1321 udelay(1); 1322 } 1323 } 1324 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1325 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1326 DOORBELL_EN, 0); 1327 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1328 DOORBELL_HIT, 1); 1329 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1330 1331 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1332 1333 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1334 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1335 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1336 1337 soc21_grbm_select(adev, 0, 0, 0, 0); 1338 mutex_unlock(&adev->srbm_mutex); 1339 1340 adev->mes.ring.sched.ready = false; 1341 } 1342 1343 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1344 { 1345 uint32_t tmp; 1346 struct amdgpu_device *adev = ring->adev; 1347 1348 /* tell RLC which is KIQ queue */ 1349 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1350 tmp &= 0xffffff00; 1351 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1352 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1353 tmp |= 0x80; 1354 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1355 } 1356 1357 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1358 { 1359 int r = 0; 1360 1361 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1362 1363 if (adev->enable_uni_mes) 1364 return mes_v12_0_hw_init(adev); 1365 1366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1367 1368 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1369 if (r) { 1370 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1371 return r; 1372 } 1373 1374 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1375 if (r) { 1376 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1377 return r; 1378 } 1379 1380 mes_v12_0_set_ucode_start_addr(adev); 1381 1382 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1383 mes_v12_0_set_ucode_start_addr(adev); 1384 1385 mes_v12_0_enable(adev, true); 1386 1387 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1388 if (r) 1389 goto failure; 1390 1391 r = mes_v12_0_hw_init(adev); 1392 if (r) 1393 goto failure; 1394 1395 return r; 1396 1397 failure: 1398 mes_v12_0_hw_fini(adev); 1399 return r; 1400 } 1401 1402 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1403 { 1404 if (adev->mes.ring.sched.ready) { 1405 mes_v12_0_kiq_dequeue_sched(adev); 1406 adev->mes.ring.sched.ready = false; 1407 } 1408 1409 mes_v12_0_enable(adev, false); 1410 1411 return 0; 1412 } 1413 1414 static int mes_v12_0_hw_init(void *handle) 1415 { 1416 int r; 1417 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1418 1419 if (adev->mes.ring.sched.ready) 1420 goto out; 1421 1422 if (!adev->enable_mes_kiq || adev->enable_uni_mes) { 1423 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1424 r = mes_v12_0_load_microcode(adev, 1425 AMDGPU_MES_SCHED_PIPE, true); 1426 if (r) { 1427 DRM_ERROR("failed to MES fw, r=%d\n", r); 1428 return r; 1429 } 1430 1431 mes_v12_0_set_ucode_start_addr(adev); 1432 1433 } else if (adev->firmware.load_type == 1434 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1435 1436 mes_v12_0_set_ucode_start_addr(adev); 1437 } 1438 1439 mes_v12_0_enable(adev, true); 1440 } 1441 1442 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1443 if (r) 1444 goto failure; 1445 1446 r = mes_v12_0_set_hw_resources(&adev->mes); 1447 if (r) 1448 goto failure; 1449 1450 if (adev->enable_uni_mes) 1451 mes_v12_0_set_hw_resources_1(&adev->mes); 1452 1453 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1454 1455 /* Enable the MES to handle doorbell ring on unmapped queue */ 1456 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1457 1458 r = mes_v12_0_query_sched_status(&adev->mes); 1459 if (r) { 1460 DRM_ERROR("MES is busy\n"); 1461 goto failure; 1462 } 1463 1464 out: 1465 /* 1466 * Disable KIQ ring usage from the driver once MES is enabled. 1467 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1468 * with MES enabled. 1469 */ 1470 adev->gfx.kiq[0].ring.sched.ready = false; 1471 adev->mes.ring.sched.ready = true; 1472 1473 return 0; 1474 1475 failure: 1476 mes_v12_0_hw_fini(adev); 1477 return r; 1478 } 1479 1480 static int mes_v12_0_hw_fini(void *handle) 1481 { 1482 return 0; 1483 } 1484 1485 static int mes_v12_0_suspend(void *handle) 1486 { 1487 int r; 1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1489 1490 r = amdgpu_mes_suspend(adev); 1491 if (r) 1492 return r; 1493 1494 return mes_v12_0_hw_fini(adev); 1495 } 1496 1497 static int mes_v12_0_resume(void *handle) 1498 { 1499 int r; 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1501 1502 r = mes_v12_0_hw_init(adev); 1503 if (r) 1504 return r; 1505 1506 return amdgpu_mes_resume(adev); 1507 } 1508 1509 static int mes_v12_0_early_init(void *handle) 1510 { 1511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1512 int pipe, r; 1513 1514 if (adev->enable_uni_mes) { 1515 r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1516 if (!r) 1517 return 0; 1518 1519 adev->enable_uni_mes = false; 1520 } 1521 1522 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1523 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1524 continue; 1525 r = amdgpu_mes_init_microcode(adev, pipe); 1526 if (r) 1527 return r; 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int mes_v12_0_late_init(void *handle) 1534 { 1535 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1536 1537 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1538 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) 1539 amdgpu_mes_self_test(adev); 1540 1541 return 0; 1542 } 1543 1544 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1545 .name = "mes_v12_0", 1546 .early_init = mes_v12_0_early_init, 1547 .late_init = mes_v12_0_late_init, 1548 .sw_init = mes_v12_0_sw_init, 1549 .sw_fini = mes_v12_0_sw_fini, 1550 .hw_init = mes_v12_0_hw_init, 1551 .hw_fini = mes_v12_0_hw_fini, 1552 .suspend = mes_v12_0_suspend, 1553 .resume = mes_v12_0_resume, 1554 }; 1555 1556 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1557 .type = AMD_IP_BLOCK_TYPE_MES, 1558 .major = 12, 1559 .minor = 0, 1560 .rev = 0, 1561 .funcs = &mes_v12_0_ip_funcs, 1562 }; 1563