1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_12_0_0_offset.h" 30 #include "gc/gc_12_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 41 42 static int mes_v12_0_hw_init(void *handle); 43 static int mes_v12_0_hw_fini(void *handle); 44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v12_0_ring_get_rptr, 84 .get_wptr = mes_v12_0_ring_get_wptr, 85 .set_wptr = mes_v12_0_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static const char *mes_v12_0_opcodes[] = { 90 "SET_HW_RSRC", 91 "SET_SCHEDULING_CONFIG", 92 "ADD_QUEUE", 93 "REMOVE_QUEUE", 94 "PERFORM_YIELD", 95 "SET_GANG_PRIORITY_LEVEL", 96 "SUSPEND", 97 "RESUME", 98 "RESET", 99 "SET_LOG_BUFFER", 100 "CHANGE_GANG_PRORITY", 101 "QUERY_SCHEDULER_STATUS", 102 "unused", 103 "SET_DEBUG_VMID", 104 "MISC", 105 "UPDATE_ROOT_PAGE_TABLE", 106 "AMD_LOG", 107 "SET_SE_MODE", 108 "SET_GANG_SUBMIT", 109 "SET_HW_RSRC_1", 110 }; 111 112 static const char *mes_v12_0_misc_opcodes[] = { 113 "WRITE_REG", 114 "INV_GART", 115 "QUERY_STATUS", 116 "READ_REG", 117 "WAIT_REG_MEM", 118 "SET_SHADER_DEBUGGER", 119 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 120 "NOTIFY_TO_UNMAP_PROCESSES", 121 }; 122 123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 124 { 125 const char *op_str = NULL; 126 127 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 128 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 129 130 return op_str; 131 } 132 133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 134 { 135 const char *op_str = NULL; 136 137 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 138 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 139 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 140 141 return op_str; 142 } 143 144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 145 int pipe, void *pkt, int size, 146 int api_status_off) 147 { 148 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 149 signed long timeout = 3000000; /* 3000 ms */ 150 struct amdgpu_device *adev = mes->adev; 151 struct amdgpu_ring *ring = &mes->ring[pipe]; 152 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 153 struct MES_API_STATUS *api_status; 154 union MESAPI__MISC *x_pkt = pkt; 155 const char *op_str, *misc_op_str; 156 unsigned long flags; 157 u64 status_gpu_addr; 158 u32 seq, status_offset; 159 u64 *status_ptr; 160 signed long r; 161 int ret; 162 163 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 164 return -EINVAL; 165 166 if (amdgpu_emu_mode) { 167 timeout *= 100; 168 } else if (amdgpu_sriov_vf(adev)) { 169 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 170 timeout = 15 * 600 * 1000; 171 } 172 173 ret = amdgpu_device_wb_get(adev, &status_offset); 174 if (ret) 175 return ret; 176 177 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 178 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 179 *status_ptr = 0; 180 181 spin_lock_irqsave(ring_lock, flags); 182 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 183 if (r) 184 goto error_unlock_free; 185 186 seq = ++ring->fence_drv.sync_seq; 187 r = amdgpu_fence_wait_polling(ring, 188 seq - ring->fence_drv.num_fences_mask, 189 timeout); 190 if (r < 1) 191 goto error_undo; 192 193 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 194 api_status->api_completion_fence_addr = status_gpu_addr; 195 api_status->api_completion_fence_value = 1; 196 197 amdgpu_ring_write_multiple(ring, pkt, size / 4); 198 199 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 200 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 201 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 202 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 203 mes_status_pkt.api_status.api_completion_fence_addr = 204 ring->fence_drv.gpu_addr; 205 mes_status_pkt.api_status.api_completion_fence_value = seq; 206 207 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 208 sizeof(mes_status_pkt) / 4); 209 210 amdgpu_ring_commit(ring); 211 spin_unlock_irqrestore(ring_lock, flags); 212 213 op_str = mes_v12_0_get_op_string(x_pkt); 214 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 215 216 if (misc_op_str) 217 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 218 pipe, op_str, misc_op_str); 219 else if (op_str) 220 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 221 pipe, op_str); 222 else 223 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 224 pipe, x_pkt->header.opcode); 225 226 r = amdgpu_fence_wait_polling(ring, seq, timeout); 227 if (r < 1 || !*status_ptr) { 228 229 if (misc_op_str) 230 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 231 pipe, op_str, misc_op_str); 232 else if (op_str) 233 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 234 pipe, op_str); 235 else 236 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 237 pipe, x_pkt->header.opcode); 238 239 while (halt_if_hws_hang) 240 schedule(); 241 242 r = -ETIMEDOUT; 243 goto error_wb_free; 244 } 245 246 amdgpu_device_wb_free(adev, status_offset); 247 return 0; 248 249 error_undo: 250 dev_err(adev->dev, "MES ring buffer is full.\n"); 251 amdgpu_ring_undo(ring); 252 253 error_unlock_free: 254 spin_unlock_irqrestore(ring_lock, flags); 255 256 error_wb_free: 257 amdgpu_device_wb_free(adev, status_offset); 258 return r; 259 } 260 261 static int convert_to_mes_queue_type(int queue_type) 262 { 263 if (queue_type == AMDGPU_RING_TYPE_GFX) 264 return MES_QUEUE_TYPE_GFX; 265 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 266 return MES_QUEUE_TYPE_COMPUTE; 267 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 268 return MES_QUEUE_TYPE_SDMA; 269 else if (queue_type == AMDGPU_RING_TYPE_MES) 270 return MES_QUEUE_TYPE_SCHQ; 271 else 272 BUG(); 273 return -1; 274 } 275 276 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 277 struct mes_add_queue_input *input) 278 { 279 struct amdgpu_device *adev = mes->adev; 280 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 281 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 282 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 283 284 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 285 286 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 287 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 288 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 289 290 mes_add_queue_pkt.process_id = input->process_id; 291 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 292 mes_add_queue_pkt.process_va_start = input->process_va_start; 293 mes_add_queue_pkt.process_va_end = input->process_va_end; 294 mes_add_queue_pkt.process_quantum = input->process_quantum; 295 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 296 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 297 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 298 mes_add_queue_pkt.inprocess_gang_priority = 299 input->inprocess_gang_priority; 300 mes_add_queue_pkt.gang_global_priority_level = 301 input->gang_global_priority_level; 302 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 303 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 304 305 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 306 307 mes_add_queue_pkt.queue_type = 308 convert_to_mes_queue_type(input->queue_type); 309 mes_add_queue_pkt.paging = input->paging; 310 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 311 mes_add_queue_pkt.gws_base = input->gws_base; 312 mes_add_queue_pkt.gws_size = input->gws_size; 313 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 314 mes_add_queue_pkt.tma_addr = input->tma_addr; 315 mes_add_queue_pkt.trap_en = input->trap_en; 316 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 317 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 318 319 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 320 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 321 mes_add_queue_pkt.gds_size = input->queue_size; 322 323 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 324 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 325 mes_add_queue_pkt.gds_size = input->queue_size; 326 327 return mes_v12_0_submit_pkt_and_poll_completion(mes, 328 AMDGPU_MES_SCHED_PIPE, 329 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 330 offsetof(union MESAPI__ADD_QUEUE, api_status)); 331 } 332 333 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 334 struct mes_remove_queue_input *input) 335 { 336 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 337 338 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 339 340 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 341 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 342 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 343 344 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 345 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 346 347 return mes_v12_0_submit_pkt_and_poll_completion(mes, 348 AMDGPU_MES_SCHED_PIPE, 349 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 350 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 351 } 352 353 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 354 struct mes_reset_queue_input *input) 355 { 356 union MESAPI__RESET mes_reset_queue_pkt; 357 int pipe; 358 359 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 360 361 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 362 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 363 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 364 365 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 366 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; 367 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 368 369 if (mes->adev->enable_uni_mes) 370 pipe = AMDGPU_MES_KIQ_PIPE; 371 else 372 pipe = AMDGPU_MES_SCHED_PIPE; 373 374 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 375 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 376 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 377 } 378 379 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 380 struct mes_map_legacy_queue_input *input) 381 { 382 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 383 int pipe; 384 385 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 386 387 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 388 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 389 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 390 391 mes_add_queue_pkt.pipe_id = input->pipe_id; 392 mes_add_queue_pkt.queue_id = input->queue_id; 393 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 394 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 395 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 396 mes_add_queue_pkt.queue_type = 397 convert_to_mes_queue_type(input->queue_type); 398 mes_add_queue_pkt.map_legacy_kq = 1; 399 400 if (mes->adev->enable_uni_mes) 401 pipe = AMDGPU_MES_KIQ_PIPE; 402 else 403 pipe = AMDGPU_MES_SCHED_PIPE; 404 405 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 406 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 407 offsetof(union MESAPI__ADD_QUEUE, api_status)); 408 } 409 410 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 411 struct mes_unmap_legacy_queue_input *input) 412 { 413 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 414 int pipe; 415 416 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 417 418 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 419 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 420 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 421 422 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 423 mes_remove_queue_pkt.gang_context_addr = 0; 424 425 mes_remove_queue_pkt.pipe_id = input->pipe_id; 426 mes_remove_queue_pkt.queue_id = input->queue_id; 427 428 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 429 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 430 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 431 mes_remove_queue_pkt.tf_data = 432 lower_32_bits(input->trail_fence_data); 433 } else { 434 mes_remove_queue_pkt.unmap_legacy_queue = 1; 435 mes_remove_queue_pkt.queue_type = 436 convert_to_mes_queue_type(input->queue_type); 437 } 438 439 if (mes->adev->enable_uni_mes) 440 pipe = AMDGPU_MES_KIQ_PIPE; 441 else 442 pipe = AMDGPU_MES_SCHED_PIPE; 443 444 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 445 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 446 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 447 } 448 449 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 450 struct mes_suspend_gang_input *input) 451 { 452 return 0; 453 } 454 455 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 456 struct mes_resume_gang_input *input) 457 { 458 return 0; 459 } 460 461 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 462 { 463 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 464 465 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 466 467 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 468 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 469 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 470 471 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 472 &mes_status_pkt, sizeof(mes_status_pkt), 473 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 474 } 475 476 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 477 struct mes_misc_op_input *input) 478 { 479 union MESAPI__MISC misc_pkt; 480 int pipe; 481 482 if (mes->adev->enable_uni_mes) 483 pipe = AMDGPU_MES_KIQ_PIPE; 484 else 485 pipe = AMDGPU_MES_SCHED_PIPE; 486 487 memset(&misc_pkt, 0, sizeof(misc_pkt)); 488 489 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 490 misc_pkt.header.opcode = MES_SCH_API_MISC; 491 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 492 493 switch (input->op) { 494 case MES_MISC_OP_READ_REG: 495 misc_pkt.opcode = MESAPI_MISC__READ_REG; 496 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 497 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 498 break; 499 case MES_MISC_OP_WRITE_REG: 500 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 501 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 502 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 503 break; 504 case MES_MISC_OP_WRM_REG_WAIT: 505 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 506 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 507 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 508 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 509 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 510 misc_pkt.wait_reg_mem.reg_offset2 = 0; 511 break; 512 case MES_MISC_OP_WRM_REG_WR_WAIT: 513 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 514 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 515 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 516 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 517 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 518 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 519 break; 520 case MES_MISC_OP_SET_SHADER_DEBUGGER: 521 pipe = AMDGPU_MES_SCHED_PIPE; 522 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 523 misc_pkt.set_shader_debugger.process_context_addr = 524 input->set_shader_debugger.process_context_addr; 525 misc_pkt.set_shader_debugger.flags.u32all = 526 input->set_shader_debugger.flags.u32all; 527 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 528 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 529 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 530 input->set_shader_debugger.tcp_watch_cntl, 531 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 532 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 533 break; 534 default: 535 DRM_ERROR("unsupported misc op (%d) \n", input->op); 536 return -EINVAL; 537 } 538 539 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 540 &misc_pkt, sizeof(misc_pkt), 541 offsetof(union MESAPI__MISC, api_status)); 542 } 543 544 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 545 { 546 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 547 548 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 549 550 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 551 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 552 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 553 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 554 555 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 556 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 557 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 558 } 559 560 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 561 { 562 int i; 563 struct amdgpu_device *adev = mes->adev; 564 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 565 566 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 567 568 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 569 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 570 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 571 572 if (pipe == AMDGPU_MES_SCHED_PIPE) { 573 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 574 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 575 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 576 mes_set_hw_res_pkt.paging_vmid = 0; 577 578 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 579 mes_set_hw_res_pkt.compute_hqd_mask[i] = 580 mes->compute_hqd_mask[i]; 581 582 for (i = 0; i < MAX_GFX_PIPES; i++) 583 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 584 mes->gfx_hqd_mask[i]; 585 586 for (i = 0; i < MAX_SDMA_PIPES; i++) 587 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 588 mes->sdma_hqd_mask[i]; 589 590 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 591 mes_set_hw_res_pkt.aggregated_doorbells[i] = 592 mes->aggregated_doorbells[i]; 593 } 594 595 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 596 mes->sch_ctx_gpu_addr[pipe]; 597 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 598 mes->query_status_fence_gpu_addr[pipe]; 599 600 for (i = 0; i < 5; i++) { 601 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 602 mes_set_hw_res_pkt.mmhub_base[i] = 603 adev->reg_offset[MMHUB_HWIP][0][i]; 604 mes_set_hw_res_pkt.osssys_base[i] = 605 adev->reg_offset[OSSSYS_HWIP][0][i]; 606 } 607 608 mes_set_hw_res_pkt.disable_reset = 1; 609 mes_set_hw_res_pkt.disable_mes_log = 1; 610 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 611 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 612 613 /* 614 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 615 * handling support, other queue will not use the oversubscribe timer. 616 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 617 */ 618 mes_set_hw_res_pkt.oversubscription_timer = 50; 619 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 620 621 if (amdgpu_mes_log_enable) { 622 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 623 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 624 } 625 626 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 627 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 628 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 629 } 630 631 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 632 { 633 struct amdgpu_device *adev = mes->adev; 634 uint32_t data; 635 636 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 637 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 638 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 639 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 640 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 641 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 642 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 643 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 644 645 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 646 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 647 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 648 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 649 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 650 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 651 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 652 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 653 654 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 655 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 656 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 657 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 658 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 659 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 660 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 661 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 662 663 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 664 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 665 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 666 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 667 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 668 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 669 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 670 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 671 672 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 673 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 674 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 675 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 676 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 677 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 678 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 679 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 680 681 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 682 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 683 } 684 685 686 static void mes_v12_0_enable_unmapped_doorbell_handling( 687 struct amdgpu_mes *mes, bool enable) 688 { 689 struct amdgpu_device *adev = mes->adev; 690 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 691 692 /* 693 * The default PROC_LSB settng is 0xc which means doorbell 694 * addr[16:12] gives the doorbell page number. For kfd, each 695 * process will use 2 pages of doorbell, we need to change the 696 * setting to 0xd 697 */ 698 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 699 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 700 701 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 702 703 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 704 } 705 706 static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes, 707 struct mes_reset_legacy_queue_input *input) 708 { 709 union MESAPI__RESET mes_reset_queue_pkt; 710 int pipe; 711 712 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 713 714 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 715 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 716 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 717 718 mes_reset_queue_pkt.queue_type = 719 convert_to_mes_queue_type(input->queue_type); 720 721 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 722 mes_reset_queue_pkt.reset_legacy_gfx = 1; 723 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 724 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 725 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 726 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 727 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 728 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 729 } else { 730 mes_reset_queue_pkt.reset_queue_only = 1; 731 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 732 } 733 734 if (mes->adev->enable_uni_mes) 735 pipe = AMDGPU_MES_KIQ_PIPE; 736 else 737 pipe = AMDGPU_MES_SCHED_PIPE; 738 739 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 740 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 741 offsetof(union MESAPI__RESET, api_status)); 742 } 743 744 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 745 .add_hw_queue = mes_v12_0_add_hw_queue, 746 .remove_hw_queue = mes_v12_0_remove_hw_queue, 747 .map_legacy_queue = mes_v12_0_map_legacy_queue, 748 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 749 .suspend_gang = mes_v12_0_suspend_gang, 750 .resume_gang = mes_v12_0_resume_gang, 751 .misc_op = mes_v12_0_misc_op, 752 .reset_legacy_queue = mes_v12_0_reset_legacy_queue, 753 .reset_hw_queue = mes_v12_0_reset_hw_queue, 754 }; 755 756 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 757 enum admgpu_mes_pipe pipe) 758 { 759 int r; 760 const struct mes_firmware_header_v1_0 *mes_hdr; 761 const __le32 *fw_data; 762 unsigned fw_size; 763 764 mes_hdr = (const struct mes_firmware_header_v1_0 *) 765 adev->mes.fw[pipe]->data; 766 767 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 768 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 769 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 770 771 r = amdgpu_bo_create_reserved(adev, fw_size, 772 PAGE_SIZE, 773 AMDGPU_GEM_DOMAIN_VRAM, 774 &adev->mes.ucode_fw_obj[pipe], 775 &adev->mes.ucode_fw_gpu_addr[pipe], 776 (void **)&adev->mes.ucode_fw_ptr[pipe]); 777 if (r) { 778 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 779 return r; 780 } 781 782 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 783 784 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 785 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 786 787 return 0; 788 } 789 790 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 791 enum admgpu_mes_pipe pipe) 792 { 793 int r; 794 const struct mes_firmware_header_v1_0 *mes_hdr; 795 const __le32 *fw_data; 796 unsigned fw_size; 797 798 mes_hdr = (const struct mes_firmware_header_v1_0 *) 799 adev->mes.fw[pipe]->data; 800 801 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 802 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 803 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 804 805 r = amdgpu_bo_create_reserved(adev, fw_size, 806 64 * 1024, 807 AMDGPU_GEM_DOMAIN_VRAM, 808 &adev->mes.data_fw_obj[pipe], 809 &adev->mes.data_fw_gpu_addr[pipe], 810 (void **)&adev->mes.data_fw_ptr[pipe]); 811 if (r) { 812 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 813 return r; 814 } 815 816 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 817 818 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 819 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 820 821 return 0; 822 } 823 824 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 825 enum admgpu_mes_pipe pipe) 826 { 827 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 828 &adev->mes.data_fw_gpu_addr[pipe], 829 (void **)&adev->mes.data_fw_ptr[pipe]); 830 831 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 832 &adev->mes.ucode_fw_gpu_addr[pipe], 833 (void **)&adev->mes.ucode_fw_ptr[pipe]); 834 } 835 836 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 837 { 838 uint64_t ucode_addr; 839 uint32_t pipe, data = 0; 840 841 if (enable) { 842 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 843 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 844 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 845 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 846 847 mutex_lock(&adev->srbm_mutex); 848 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 849 soc21_grbm_select(adev, 3, pipe, 0, 0); 850 851 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 852 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 853 lower_32_bits(ucode_addr)); 854 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 855 upper_32_bits(ucode_addr)); 856 } 857 soc21_grbm_select(adev, 0, 0, 0, 0); 858 mutex_unlock(&adev->srbm_mutex); 859 860 /* unhalt MES and activate pipe0 */ 861 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 862 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 863 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 864 865 if (amdgpu_emu_mode) 866 msleep(100); 867 else if (adev->enable_uni_mes) 868 udelay(500); 869 else 870 udelay(50); 871 } else { 872 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 873 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 874 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 875 data = REG_SET_FIELD(data, CP_MES_CNTL, 876 MES_INVALIDATE_ICACHE, 1); 877 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 878 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 879 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 880 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 881 } 882 } 883 884 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 885 { 886 uint64_t ucode_addr; 887 int pipe; 888 889 mes_v12_0_enable(adev, false); 890 891 mutex_lock(&adev->srbm_mutex); 892 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 893 /* me=3, queue=0 */ 894 soc21_grbm_select(adev, 3, pipe, 0, 0); 895 896 /* set ucode start address */ 897 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 898 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 899 lower_32_bits(ucode_addr)); 900 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 901 upper_32_bits(ucode_addr)); 902 903 soc21_grbm_select(adev, 0, 0, 0, 0); 904 } 905 mutex_unlock(&adev->srbm_mutex); 906 } 907 908 /* This function is for backdoor MES firmware */ 909 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 910 enum admgpu_mes_pipe pipe, bool prime_icache) 911 { 912 int r; 913 uint32_t data; 914 915 mes_v12_0_enable(adev, false); 916 917 if (!adev->mes.fw[pipe]) 918 return -EINVAL; 919 920 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 921 if (r) 922 return r; 923 924 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 925 if (r) { 926 mes_v12_0_free_ucode_buffers(adev, pipe); 927 return r; 928 } 929 930 mutex_lock(&adev->srbm_mutex); 931 /* me=3, pipe=0, queue=0 */ 932 soc21_grbm_select(adev, 3, pipe, 0, 0); 933 934 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 935 936 /* set ucode fimrware address */ 937 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 938 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 939 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 940 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 941 942 /* set ucode instruction cache boundary to 2M-1 */ 943 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 944 945 /* set ucode data firmware address */ 946 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 947 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 948 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 949 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 950 951 /* Set data cache boundary CP_MES_MDBOUND_LO */ 952 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 953 954 if (prime_icache) { 955 /* invalidate ICACHE */ 956 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 957 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 958 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 959 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 960 961 /* prime the ICACHE. */ 962 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 963 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 964 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 965 } 966 967 soc21_grbm_select(adev, 0, 0, 0, 0); 968 mutex_unlock(&adev->srbm_mutex); 969 970 return 0; 971 } 972 973 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 974 enum admgpu_mes_pipe pipe) 975 { 976 int r; 977 u32 *eop; 978 979 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 980 AMDGPU_GEM_DOMAIN_GTT, 981 &adev->mes.eop_gpu_obj[pipe], 982 &adev->mes.eop_gpu_addr[pipe], 983 (void **)&eop); 984 if (r) { 985 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 986 return r; 987 } 988 989 memset(eop, 0, 990 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 991 992 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 993 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 994 995 return 0; 996 } 997 998 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 999 { 1000 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1001 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1002 uint32_t tmp; 1003 1004 mqd->header = 0xC0310800; 1005 mqd->compute_pipelinestat_enable = 0x00000001; 1006 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1007 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1008 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1009 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1010 mqd->compute_misc_reserved = 0x00000007; 1011 1012 eop_base_addr = ring->eop_gpu_addr >> 8; 1013 1014 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1015 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1016 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1017 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1018 1019 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1020 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1021 mqd->cp_hqd_eop_control = tmp; 1022 1023 /* disable the queue if it's active */ 1024 ring->wptr = 0; 1025 mqd->cp_hqd_pq_rptr = 0; 1026 mqd->cp_hqd_pq_wptr_lo = 0; 1027 mqd->cp_hqd_pq_wptr_hi = 0; 1028 1029 /* set the pointer to the MQD */ 1030 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1031 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1032 1033 /* set MQD vmid to 0 */ 1034 tmp = regCP_MQD_CONTROL_DEFAULT; 1035 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1036 mqd->cp_mqd_control = tmp; 1037 1038 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1039 hqd_gpu_addr = ring->gpu_addr >> 8; 1040 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1041 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1042 1043 /* set the wb address whether it's enabled or not */ 1044 wb_gpu_addr = ring->rptr_gpu_addr; 1045 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1046 mqd->cp_hqd_pq_rptr_report_addr_hi = 1047 upper_32_bits(wb_gpu_addr) & 0xffff; 1048 1049 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1050 wb_gpu_addr = ring->wptr_gpu_addr; 1051 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1052 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1053 1054 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1055 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1056 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1057 (order_base_2(ring->ring_size / 4) - 1)); 1058 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1059 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1064 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1065 mqd->cp_hqd_pq_control = tmp; 1066 1067 /* enable doorbell */ 1068 tmp = 0; 1069 if (ring->use_doorbell) { 1070 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1071 DOORBELL_OFFSET, ring->doorbell_index); 1072 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1073 DOORBELL_EN, 1); 1074 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1075 DOORBELL_SOURCE, 0); 1076 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1077 DOORBELL_HIT, 0); 1078 } else { 1079 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1080 DOORBELL_EN, 0); 1081 } 1082 mqd->cp_hqd_pq_doorbell_control = tmp; 1083 1084 mqd->cp_hqd_vmid = 0; 1085 /* activate the queue */ 1086 mqd->cp_hqd_active = 1; 1087 1088 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1089 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1090 PRELOAD_SIZE, 0x55); 1091 mqd->cp_hqd_persistent_state = tmp; 1092 1093 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1094 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1095 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1096 1097 /* 1098 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1099 * doorbell handling. This is a reserved CP internal register can 1100 * not be accesss by others 1101 */ 1102 mqd->reserved_184 = BIT(15); 1103 1104 return 0; 1105 } 1106 1107 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1108 { 1109 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1110 struct amdgpu_device *adev = ring->adev; 1111 uint32_t data = 0; 1112 1113 mutex_lock(&adev->srbm_mutex); 1114 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1115 1116 /* set CP_HQD_VMID.VMID = 0. */ 1117 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1118 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1119 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1120 1121 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1122 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1123 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1124 DOORBELL_EN, 0); 1125 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1126 1127 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1128 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1129 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1130 1131 /* set CP_MQD_CONTROL.VMID=0 */ 1132 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1133 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1134 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1135 1136 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1137 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1138 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1139 1140 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1141 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1142 mqd->cp_hqd_pq_rptr_report_addr_lo); 1143 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1144 mqd->cp_hqd_pq_rptr_report_addr_hi); 1145 1146 /* set CP_HQD_PQ_CONTROL */ 1147 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1148 1149 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1150 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1151 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1152 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1153 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1154 1155 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1156 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1157 mqd->cp_hqd_pq_doorbell_control); 1158 1159 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1160 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1161 1162 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1163 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1164 1165 soc21_grbm_select(adev, 0, 0, 0, 0); 1166 mutex_unlock(&adev->srbm_mutex); 1167 } 1168 1169 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1170 { 1171 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1172 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1173 int r; 1174 1175 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1176 return -EINVAL; 1177 1178 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1179 if (r) { 1180 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1181 return r; 1182 } 1183 1184 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1185 1186 r = amdgpu_ring_test_ring(kiq_ring); 1187 if (r) { 1188 DRM_ERROR("kfq enable failed\n"); 1189 kiq_ring->sched.ready = false; 1190 } 1191 return r; 1192 } 1193 1194 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1195 enum admgpu_mes_pipe pipe) 1196 { 1197 struct amdgpu_ring *ring; 1198 int r; 1199 1200 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1201 ring = &adev->gfx.kiq[0].ring; 1202 else 1203 ring = &adev->mes.ring[pipe]; 1204 1205 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1206 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1207 *(ring->wptr_cpu_addr) = 0; 1208 *(ring->rptr_cpu_addr) = 0; 1209 amdgpu_ring_clear_ring(ring); 1210 } 1211 1212 r = mes_v12_0_mqd_init(ring); 1213 if (r) 1214 return r; 1215 1216 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1217 if (adev->enable_uni_mes) 1218 r = amdgpu_mes_map_legacy_queue(adev, ring); 1219 else 1220 r = mes_v12_0_kiq_enable_queue(adev); 1221 if (r) 1222 return r; 1223 } else { 1224 mes_v12_0_queue_init_register(ring); 1225 } 1226 1227 /* get MES scheduler/KIQ versions */ 1228 mutex_lock(&adev->srbm_mutex); 1229 soc21_grbm_select(adev, 3, pipe, 0, 0); 1230 1231 if (pipe == AMDGPU_MES_SCHED_PIPE) 1232 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1233 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1234 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1235 1236 soc21_grbm_select(adev, 0, 0, 0, 0); 1237 mutex_unlock(&adev->srbm_mutex); 1238 1239 return 0; 1240 } 1241 1242 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1243 { 1244 struct amdgpu_ring *ring; 1245 1246 ring = &adev->mes.ring[pipe]; 1247 1248 ring->funcs = &mes_v12_0_ring_funcs; 1249 1250 ring->me = 3; 1251 ring->pipe = pipe; 1252 ring->queue = 0; 1253 1254 ring->ring_obj = NULL; 1255 ring->use_doorbell = true; 1256 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1257 ring->no_scheduler = true; 1258 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1259 1260 if (pipe == AMDGPU_MES_SCHED_PIPE) 1261 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1262 else 1263 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1264 1265 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1266 AMDGPU_RING_PRIO_DEFAULT, NULL); 1267 } 1268 1269 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1270 { 1271 struct amdgpu_ring *ring; 1272 1273 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1274 1275 ring = &adev->gfx.kiq[0].ring; 1276 1277 ring->me = 3; 1278 ring->pipe = 1; 1279 ring->queue = 0; 1280 1281 ring->adev = NULL; 1282 ring->ring_obj = NULL; 1283 ring->use_doorbell = true; 1284 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1285 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1286 ring->no_scheduler = true; 1287 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1288 ring->me, ring->pipe, ring->queue); 1289 1290 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1291 AMDGPU_RING_PRIO_DEFAULT, NULL); 1292 } 1293 1294 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1295 enum admgpu_mes_pipe pipe) 1296 { 1297 int r, mqd_size = sizeof(struct v12_compute_mqd); 1298 struct amdgpu_ring *ring; 1299 1300 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1301 ring = &adev->gfx.kiq[0].ring; 1302 else 1303 ring = &adev->mes.ring[pipe]; 1304 1305 if (ring->mqd_obj) 1306 return 0; 1307 1308 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1309 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1310 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1311 if (r) { 1312 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1313 return r; 1314 } 1315 1316 memset(ring->mqd_ptr, 0, mqd_size); 1317 1318 /* prepare MQD backup */ 1319 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1320 if (!adev->mes.mqd_backup[pipe]) 1321 dev_warn(adev->dev, 1322 "no memory to create MQD backup for ring %s\n", 1323 ring->name); 1324 1325 return 0; 1326 } 1327 1328 static int mes_v12_0_sw_init(void *handle) 1329 { 1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1331 int pipe, r; 1332 1333 adev->mes.funcs = &mes_v12_0_funcs; 1334 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1335 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1336 adev->mes.enable_legacy_queue_map = true; 1337 1338 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; 1339 1340 r = amdgpu_mes_init(adev); 1341 if (r) 1342 return r; 1343 1344 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1345 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1346 if (r) 1347 return r; 1348 1349 r = mes_v12_0_mqd_sw_init(adev, pipe); 1350 if (r) 1351 return r; 1352 1353 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1354 r = mes_v12_0_kiq_ring_init(adev); 1355 else 1356 r = mes_v12_0_ring_init(adev, pipe); 1357 if (r) 1358 return r; 1359 } 1360 1361 return 0; 1362 } 1363 1364 static int mes_v12_0_sw_fini(void *handle) 1365 { 1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1367 int pipe; 1368 1369 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1370 kfree(adev->mes.mqd_backup[pipe]); 1371 1372 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1373 &adev->mes.eop_gpu_addr[pipe], 1374 NULL); 1375 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1376 1377 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1378 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1379 &adev->mes.ring[pipe].mqd_gpu_addr, 1380 &adev->mes.ring[pipe].mqd_ptr); 1381 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1382 } 1383 } 1384 1385 if (!adev->enable_uni_mes) { 1386 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1387 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1388 &adev->gfx.kiq[0].ring.mqd_ptr); 1389 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1390 } 1391 1392 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1393 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1394 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1395 } 1396 1397 amdgpu_mes_fini(adev); 1398 return 0; 1399 } 1400 1401 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1402 { 1403 uint32_t data; 1404 int i; 1405 1406 mutex_lock(&adev->srbm_mutex); 1407 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1408 1409 /* disable the queue if it's active */ 1410 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1411 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1412 for (i = 0; i < adev->usec_timeout; i++) { 1413 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1414 break; 1415 udelay(1); 1416 } 1417 } 1418 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1419 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1420 DOORBELL_EN, 0); 1421 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1422 DOORBELL_HIT, 1); 1423 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1424 1425 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1426 1427 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1428 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1429 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1430 1431 soc21_grbm_select(adev, 0, 0, 0, 0); 1432 mutex_unlock(&adev->srbm_mutex); 1433 1434 adev->mes.ring[0].sched.ready = false; 1435 } 1436 1437 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1438 { 1439 uint32_t tmp; 1440 struct amdgpu_device *adev = ring->adev; 1441 1442 /* tell RLC which is KIQ queue */ 1443 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1444 tmp &= 0xffffff00; 1445 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1446 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1447 tmp |= 0x80; 1448 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1449 } 1450 1451 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1452 { 1453 int r = 0; 1454 1455 if (adev->enable_uni_mes) 1456 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1457 else 1458 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1459 1460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1461 1462 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1463 if (r) { 1464 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1465 return r; 1466 } 1467 1468 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1469 if (r) { 1470 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1471 return r; 1472 } 1473 1474 mes_v12_0_set_ucode_start_addr(adev); 1475 1476 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1477 mes_v12_0_set_ucode_start_addr(adev); 1478 1479 mes_v12_0_enable(adev, true); 1480 1481 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1482 if (r) 1483 goto failure; 1484 1485 if (adev->enable_uni_mes) { 1486 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1487 if (r) 1488 goto failure; 1489 1490 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1491 } 1492 1493 if (adev->mes.enable_legacy_queue_map) { 1494 r = mes_v12_0_hw_init(adev); 1495 if (r) 1496 goto failure; 1497 } 1498 1499 return r; 1500 1501 failure: 1502 mes_v12_0_hw_fini(adev); 1503 return r; 1504 } 1505 1506 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1507 { 1508 if (adev->mes.ring[0].sched.ready) { 1509 if (adev->enable_uni_mes) 1510 amdgpu_mes_unmap_legacy_queue(adev, 1511 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 1512 RESET_QUEUES, 0, 0); 1513 else 1514 mes_v12_0_kiq_dequeue_sched(adev); 1515 1516 adev->mes.ring[0].sched.ready = false; 1517 } 1518 1519 mes_v12_0_enable(adev, false); 1520 1521 return 0; 1522 } 1523 1524 static int mes_v12_0_hw_init(void *handle) 1525 { 1526 int r; 1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1528 1529 if (adev->mes.ring[0].sched.ready) 1530 goto out; 1531 1532 if (!adev->enable_mes_kiq) { 1533 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1534 r = mes_v12_0_load_microcode(adev, 1535 AMDGPU_MES_SCHED_PIPE, true); 1536 if (r) { 1537 DRM_ERROR("failed to MES fw, r=%d\n", r); 1538 return r; 1539 } 1540 1541 mes_v12_0_set_ucode_start_addr(adev); 1542 1543 } else if (adev->firmware.load_type == 1544 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1545 1546 mes_v12_0_set_ucode_start_addr(adev); 1547 } 1548 1549 mes_v12_0_enable(adev, true); 1550 } 1551 1552 /* Enable the MES to handle doorbell ring on unmapped queue */ 1553 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1554 1555 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1556 if (r) 1557 goto failure; 1558 1559 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1560 if (r) 1561 goto failure; 1562 1563 if (adev->enable_uni_mes) 1564 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1565 1566 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1567 1568 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1569 if (r) { 1570 DRM_ERROR("MES is busy\n"); 1571 goto failure; 1572 } 1573 1574 out: 1575 /* 1576 * Disable KIQ ring usage from the driver once MES is enabled. 1577 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1578 * with MES enabled. 1579 */ 1580 adev->gfx.kiq[0].ring.sched.ready = false; 1581 adev->mes.ring[0].sched.ready = true; 1582 1583 return 0; 1584 1585 failure: 1586 mes_v12_0_hw_fini(adev); 1587 return r; 1588 } 1589 1590 static int mes_v12_0_hw_fini(void *handle) 1591 { 1592 return 0; 1593 } 1594 1595 static int mes_v12_0_suspend(void *handle) 1596 { 1597 int r; 1598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1599 1600 r = amdgpu_mes_suspend(adev); 1601 if (r) 1602 return r; 1603 1604 return mes_v12_0_hw_fini(adev); 1605 } 1606 1607 static int mes_v12_0_resume(void *handle) 1608 { 1609 int r; 1610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1611 1612 r = mes_v12_0_hw_init(adev); 1613 if (r) 1614 return r; 1615 1616 return amdgpu_mes_resume(adev); 1617 } 1618 1619 static int mes_v12_0_early_init(void *handle) 1620 { 1621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1622 int pipe, r; 1623 1624 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1625 r = amdgpu_mes_init_microcode(adev, pipe); 1626 if (r) 1627 return r; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int mes_v12_0_late_init(void *handle) 1634 { 1635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1636 1637 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1638 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) 1639 amdgpu_mes_self_test(adev); 1640 1641 return 0; 1642 } 1643 1644 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1645 .name = "mes_v12_0", 1646 .early_init = mes_v12_0_early_init, 1647 .late_init = mes_v12_0_late_init, 1648 .sw_init = mes_v12_0_sw_init, 1649 .sw_fini = mes_v12_0_sw_fini, 1650 .hw_init = mes_v12_0_hw_init, 1651 .hw_fini = mes_v12_0_hw_fini, 1652 .suspend = mes_v12_0_suspend, 1653 .resume = mes_v12_0_resume, 1654 }; 1655 1656 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1657 .type = AMD_IP_BLOCK_TYPE_MES, 1658 .major = 12, 1659 .minor = 0, 1660 .rev = 0, 1661 .funcs = &mes_v12_0_ip_funcs, 1662 }; 1663