1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "gfx_v12_0.h" 28 #include "soc15_common.h" 29 #include "soc24.h" 30 #include "gc/gc_12_0_0_offset.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v12_structs.h" 34 #include "mes_v12_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 42 43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); 45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 47 48 #define MES_EOP_SIZE 2048 49 50 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 #define MES12_HUNG_HQD_INFO_OFFSET 4 52 53 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 54 { 55 struct amdgpu_device *adev = ring->adev; 56 57 if (ring->use_doorbell) { 58 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 59 ring->wptr); 60 WDOORBELL64(ring->doorbell_index, ring->wptr); 61 } else { 62 BUG(); 63 } 64 } 65 66 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 67 { 68 return *ring->rptr_cpu_addr; 69 } 70 71 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 72 { 73 u64 wptr; 74 75 if (ring->use_doorbell) 76 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 77 else 78 BUG(); 79 return wptr; 80 } 81 82 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 83 .type = AMDGPU_RING_TYPE_MES, 84 .align_mask = 1, 85 .nop = 0, 86 .support_64bit_ptrs = true, 87 .get_rptr = mes_v12_0_ring_get_rptr, 88 .get_wptr = mes_v12_0_ring_get_wptr, 89 .set_wptr = mes_v12_0_ring_set_wptr, 90 .insert_nop = amdgpu_ring_insert_nop, 91 }; 92 93 static const char *mes_v12_0_opcodes[] = { 94 "SET_HW_RSRC", 95 "SET_SCHEDULING_CONFIG", 96 "ADD_QUEUE", 97 "REMOVE_QUEUE", 98 "PERFORM_YIELD", 99 "SET_GANG_PRIORITY_LEVEL", 100 "SUSPEND", 101 "RESUME", 102 "RESET", 103 "SET_LOG_BUFFER", 104 "CHANGE_GANG_PRORITY", 105 "QUERY_SCHEDULER_STATUS", 106 "unused", 107 "SET_DEBUG_VMID", 108 "MISC", 109 "UPDATE_ROOT_PAGE_TABLE", 110 "AMD_LOG", 111 "SET_SE_MODE", 112 "SET_GANG_SUBMIT", 113 "SET_HW_RSRC_1", 114 "INVALIDATE_TLBS", 115 }; 116 117 static const char *mes_v12_0_misc_opcodes[] = { 118 "WRITE_REG", 119 "INV_GART", 120 "QUERY_STATUS", 121 "READ_REG", 122 "WAIT_REG_MEM", 123 "SET_SHADER_DEBUGGER", 124 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 125 "NOTIFY_TO_UNMAP_PROCESSES", 126 }; 127 128 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 129 { 130 const char *op_str = NULL; 131 132 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 133 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 134 135 return op_str; 136 } 137 138 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 139 { 140 const char *op_str = NULL; 141 142 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 143 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 144 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 145 146 return op_str; 147 } 148 149 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 150 int pipe, void *pkt, int size, 151 int api_status_off) 152 { 153 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 154 signed long timeout = 2100000; /* 2100 ms */ 155 struct amdgpu_device *adev = mes->adev; 156 struct amdgpu_ring *ring = &mes->ring[pipe]; 157 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 158 struct MES_API_STATUS *api_status; 159 union MESAPI__MISC *x_pkt = pkt; 160 const char *op_str, *misc_op_str; 161 unsigned long flags; 162 u64 status_gpu_addr; 163 u32 seq, status_offset; 164 u64 *status_ptr; 165 signed long r; 166 int ret; 167 168 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 169 return -EINVAL; 170 171 if (amdgpu_emu_mode) { 172 timeout *= 100; 173 } else if (amdgpu_sriov_vf(adev)) { 174 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 175 timeout = 15 * 600 * 1000; 176 } 177 178 ret = amdgpu_device_wb_get(adev, &status_offset); 179 if (ret) 180 return ret; 181 182 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 183 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 184 *status_ptr = 0; 185 186 spin_lock_irqsave(ring_lock, flags); 187 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 188 if (r) 189 goto error_unlock_free; 190 191 seq = ++ring->fence_drv.sync_seq; 192 r = amdgpu_fence_wait_polling(ring, 193 seq - ring->fence_drv.num_fences_mask, 194 timeout); 195 if (r < 1) 196 goto error_undo; 197 198 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 199 api_status->api_completion_fence_addr = status_gpu_addr; 200 api_status->api_completion_fence_value = 1; 201 202 amdgpu_ring_write_multiple(ring, pkt, size / 4); 203 204 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 205 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 206 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 207 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 208 mes_status_pkt.api_status.api_completion_fence_addr = 209 ring->fence_drv.gpu_addr; 210 mes_status_pkt.api_status.api_completion_fence_value = seq; 211 212 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 213 sizeof(mes_status_pkt) / 4); 214 215 amdgpu_ring_commit(ring); 216 spin_unlock_irqrestore(ring_lock, flags); 217 218 op_str = mes_v12_0_get_op_string(x_pkt); 219 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 220 221 if (misc_op_str) 222 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 223 pipe, op_str, misc_op_str); 224 else if (op_str) 225 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 226 pipe, op_str); 227 else 228 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 229 pipe, x_pkt->header.opcode); 230 231 r = amdgpu_fence_wait_polling(ring, seq, timeout); 232 233 /* 234 * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success). 235 * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information. 236 */ 237 if (r < 1 || !(lower_32_bits(*status_ptr))) { 238 239 if (misc_op_str) 240 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 241 pipe, op_str, misc_op_str); 242 else if (op_str) 243 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 244 pipe, op_str); 245 else 246 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 247 pipe, x_pkt->header.opcode); 248 249 while (halt_if_hws_hang) 250 schedule(); 251 252 r = -ETIMEDOUT; 253 goto error_wb_free; 254 } 255 256 amdgpu_device_wb_free(adev, status_offset); 257 return 0; 258 259 error_undo: 260 dev_err(adev->dev, "MES ring buffer is full.\n"); 261 amdgpu_ring_undo(ring); 262 263 error_unlock_free: 264 spin_unlock_irqrestore(ring_lock, flags); 265 266 error_wb_free: 267 amdgpu_device_wb_free(adev, status_offset); 268 return r; 269 } 270 271 static int convert_to_mes_queue_type(int queue_type) 272 { 273 if (queue_type == AMDGPU_RING_TYPE_GFX) 274 return MES_QUEUE_TYPE_GFX; 275 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 276 return MES_QUEUE_TYPE_COMPUTE; 277 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 278 return MES_QUEUE_TYPE_SDMA; 279 else if (queue_type == AMDGPU_RING_TYPE_MES) 280 return MES_QUEUE_TYPE_SCHQ; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int convert_to_mes_priority_level(int priority_level) 287 { 288 switch (priority_level) { 289 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 290 return AMD_PRIORITY_LEVEL_LOW; 291 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 292 default: 293 return AMD_PRIORITY_LEVEL_NORMAL; 294 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 295 return AMD_PRIORITY_LEVEL_MEDIUM; 296 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 297 return AMD_PRIORITY_LEVEL_HIGH; 298 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 299 return AMD_PRIORITY_LEVEL_REALTIME; 300 } 301 } 302 303 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 304 struct mes_add_queue_input *input) 305 { 306 struct amdgpu_device *adev = mes->adev; 307 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 308 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 309 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 310 311 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 312 313 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 314 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 315 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 316 317 mes_add_queue_pkt.process_id = input->process_id; 318 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 319 mes_add_queue_pkt.process_va_start = input->process_va_start; 320 mes_add_queue_pkt.process_va_end = input->process_va_end; 321 mes_add_queue_pkt.process_quantum = input->process_quantum; 322 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 323 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 324 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 325 mes_add_queue_pkt.inprocess_gang_priority = 326 convert_to_mes_priority_level(input->inprocess_gang_priority); 327 mes_add_queue_pkt.gang_global_priority_level = 328 convert_to_mes_priority_level(input->gang_global_priority_level); 329 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 330 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 331 332 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 333 334 mes_add_queue_pkt.queue_type = 335 convert_to_mes_queue_type(input->queue_type); 336 mes_add_queue_pkt.paging = input->paging; 337 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 338 mes_add_queue_pkt.gws_base = input->gws_base; 339 mes_add_queue_pkt.gws_size = input->gws_size; 340 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 341 mes_add_queue_pkt.tma_addr = input->tma_addr; 342 mes_add_queue_pkt.trap_en = input->trap_en; 343 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 344 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 345 346 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 347 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 348 mes_add_queue_pkt.gds_size = input->queue_size; 349 350 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 351 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 352 mes_add_queue_pkt.gds_size = input->queue_size; 353 354 return mes_v12_0_submit_pkt_and_poll_completion(mes, 355 AMDGPU_MES_SCHED_PIPE, 356 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 357 offsetof(union MESAPI__ADD_QUEUE, api_status)); 358 } 359 360 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 361 struct mes_remove_queue_input *input) 362 { 363 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 364 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 365 366 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 367 368 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 369 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 370 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 371 372 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 373 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 374 375 if (mes_rev >= 0x5a) 376 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 377 378 return mes_v12_0_submit_pkt_and_poll_completion(mes, 379 AMDGPU_MES_SCHED_PIPE, 380 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 381 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 382 } 383 384 int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev, 385 bool req) 386 { 387 u32 i, tmp, val; 388 389 for (i = 0; i < adev->usec_timeout; i++) { 390 /* Request with MeId=2, PipeId=0 */ 391 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 392 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 393 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 394 395 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 396 if (req) { 397 if (val == tmp) 398 break; 399 } else { 400 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 401 REQUEST, 1); 402 403 /* unlocked or locked by firmware */ 404 if (val != tmp) 405 break; 406 } 407 udelay(1); 408 } 409 410 if (i >= adev->usec_timeout) 411 return -EINVAL; 412 413 return 0; 414 } 415 416 static bool mes_v12_0_pipe_reset_support(struct amdgpu_device *adev) 417 { 418 /* Disable the pipe reset until the CPFW fully support it.*/ 419 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 420 return false; 421 } 422 423 static int mes_v12_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 424 u32 me, u32 pipe, u32 queue) 425 { 426 uint32_t reset_pipe = 0, clean_pipe = 0; 427 int r; 428 429 if (!mes_v12_0_pipe_reset_support(adev)) 430 return -EOPNOTSUPP; 431 432 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 433 mutex_lock(&adev->srbm_mutex); 434 soc24_grbm_select(adev, me, pipe, queue, 0); 435 436 switch (pipe) { 437 case 0: 438 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 439 PFP_PIPE0_RESET, 1); 440 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 441 ME_PIPE0_RESET, 1); 442 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 443 PFP_PIPE0_RESET, 0); 444 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 445 ME_PIPE0_RESET, 0); 446 break; 447 case 1: 448 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 449 PFP_PIPE1_RESET, 1); 450 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 451 ME_PIPE1_RESET, 1); 452 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 453 PFP_PIPE1_RESET, 0); 454 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 455 ME_PIPE1_RESET, 0); 456 break; 457 default: 458 break; 459 } 460 461 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 462 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 463 464 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 465 RS64_FW_UC_START_ADDR_LO; 466 soc24_grbm_select(adev, 0, 0, 0, 0); 467 mutex_unlock(&adev->srbm_mutex); 468 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 469 470 dev_info(adev->dev, "The gfx pipe reset: %s\n", 471 r == 0 ? "successfully" : "failed"); 472 /* Sometimes the ME start pc counter can't cache correctly, so the 473 * PC check only as a reference and pipe reset result rely on the 474 * later ring test. 475 */ 476 return 0; 477 } 478 479 /* 480 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 481 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 482 * asserted; only then clear the pipe reset bit. 483 * Caller must hold adev->srbm_mutex. 484 */ 485 static void mes_v12_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 486 u32 pipe) 487 { 488 unsigned int q; 489 490 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 491 soc24_grbm_select(adev, me, pipe, q, 0); 492 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 493 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 494 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 495 } 496 } 497 498 static int mes_v12_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 499 u32 me, u32 pipe, u32 queue) 500 { 501 uint32_t reset_val, clean_val; 502 int r = 0; 503 504 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 505 mutex_lock(&adev->srbm_mutex); 506 soc24_grbm_select(adev, me, pipe, queue, 0); 507 if (adev->gfx.rs64_enable) { 508 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 509 clean_val = reset_val; 510 511 switch (pipe) { 512 case 0: 513 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 514 MEC_PIPE0_RESET, 1); 515 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 516 MEC_PIPE0_RESET, 0); 517 break; 518 case 1: 519 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 520 MEC_PIPE1_RESET, 1); 521 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 522 MEC_PIPE1_RESET, 0); 523 break; 524 case 2: 525 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 526 MEC_PIPE2_RESET, 1); 527 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 528 MEC_PIPE2_RESET, 0); 529 break; 530 case 3: 531 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 532 MEC_PIPE3_RESET, 1); 533 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 534 MEC_PIPE3_RESET, 0); 535 break; 536 default: 537 break; 538 } 539 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 540 mes_v12_0_clear_hqds_on_mec_pipe(adev, me, pipe); 541 soc24_grbm_select(adev, me, pipe, queue, 0); 542 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 543 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 544 RS64_FW_UC_START_ADDR_LO; 545 } else { 546 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 547 clean_val = reset_val; 548 549 switch (pipe) { 550 case 0: 551 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 552 MEC_ME1_PIPE0_RESET, 1); 553 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 554 MEC_ME1_PIPE0_RESET, 0); 555 break; 556 case 1: 557 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 558 MEC_ME1_PIPE1_RESET, 1); 559 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 560 MEC_ME1_PIPE1_RESET, 0); 561 break; 562 default: 563 break; 564 } 565 566 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 567 mes_v12_0_clear_hqds_on_mec_pipe(adev, me, pipe); 568 soc24_grbm_select(adev, me, pipe, queue, 0); 569 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 570 } 571 572 soc24_grbm_select(adev, 0, 0, 0, 0); 573 mutex_unlock(&adev->srbm_mutex); 574 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 575 576 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 577 me, pipe, queue, r == 0 ? "successfully" : "failed"); 578 return 0; 579 } 580 581 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 582 uint32_t me_id, uint32_t pipe_id, 583 uint32_t queue_id, uint32_t vmid) 584 { 585 struct amdgpu_device *adev = mes->adev; 586 uint32_t value, reg; 587 int i, r = 0; 588 589 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 590 591 if (queue_type == AMDGPU_RING_TYPE_GFX) { 592 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 593 me_id, pipe_id, queue_id, vmid); 594 595 mutex_lock(&adev->gfx.reset_sem_mutex); 596 gfx_v12_0_request_gfx_index_mutex(adev, true); 597 /* all se allow writes */ 598 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 599 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 600 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 601 if (pipe_id == 0) 602 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 603 else 604 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 605 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 606 gfx_v12_0_request_gfx_index_mutex(adev, false); 607 mutex_unlock(&adev->gfx.reset_sem_mutex); 608 609 mutex_lock(&adev->srbm_mutex); 610 soc24_grbm_select(adev, me_id, pipe_id, queue_id, 0); 611 /* wait till dequeue take effects */ 612 for (i = 0; i < adev->usec_timeout; i++) { 613 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 614 break; 615 udelay(1); 616 } 617 if (i >= adev->usec_timeout) { 618 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 619 r = -ETIMEDOUT; 620 } 621 622 soc24_grbm_select(adev, 0, 0, 0, 0); 623 mutex_unlock(&adev->srbm_mutex); 624 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 625 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 626 me_id, pipe_id, queue_id); 627 mutex_lock(&adev->srbm_mutex); 628 soc24_grbm_select(adev, me_id, pipe_id, queue_id, 0); 629 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 630 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 631 632 /* wait till dequeue take effects */ 633 for (i = 0; i < adev->usec_timeout; i++) { 634 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 635 break; 636 udelay(1); 637 } 638 if (i >= adev->usec_timeout) { 639 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 640 r = -ETIMEDOUT; 641 } 642 soc24_grbm_select(adev, 0, 0, 0, 0); 643 mutex_unlock(&adev->srbm_mutex); 644 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 645 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 646 me_id, pipe_id, queue_id); 647 switch (me_id) { 648 case 1: 649 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 650 break; 651 case 0: 652 default: 653 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 654 break; 655 } 656 657 value = 1 << queue_id; 658 WREG32(reg, value); 659 /* wait for queue reset done */ 660 for (i = 0; i < adev->usec_timeout; i++) { 661 if (!(RREG32(reg) & value)) 662 break; 663 udelay(1); 664 } 665 if (i >= adev->usec_timeout) { 666 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 667 r = -ETIMEDOUT; 668 } 669 } 670 671 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 672 return r; 673 } 674 675 static int mes_v12_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 676 uint32_t me_id, uint32_t pipe_id, 677 uint32_t queue_id, uint32_t vmid) 678 { 679 struct amdgpu_device *adev = mes->adev; 680 681 if (queue_type == AMDGPU_RING_TYPE_GFX) 682 return mes_v12_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 683 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 684 return mes_v12_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 685 else 686 return -EOPNOTSUPP; 687 } 688 689 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 690 struct mes_map_legacy_queue_input *input) 691 { 692 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 693 int pipe; 694 695 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 696 697 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 698 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 699 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 700 701 mes_add_queue_pkt.pipe_id = input->pipe_id; 702 mes_add_queue_pkt.queue_id = input->queue_id; 703 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 704 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 705 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 706 mes_add_queue_pkt.queue_type = 707 convert_to_mes_queue_type(input->queue_type); 708 mes_add_queue_pkt.map_legacy_kq = 1; 709 710 if (mes->adev->enable_uni_mes) { 711 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 712 if (input->queue_type == AMDGPU_RING_TYPE_MES) 713 pipe = AMDGPU_MES_KIQ_PIPE; 714 else 715 pipe = AMDGPU_MES_SCHED_PIPE; 716 } else { 717 pipe = AMDGPU_MES_SCHED_PIPE; 718 } 719 720 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 721 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 722 offsetof(union MESAPI__ADD_QUEUE, api_status)); 723 } 724 725 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 726 struct mes_unmap_legacy_queue_input *input) 727 { 728 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 729 int pipe; 730 731 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 732 733 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 734 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 735 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 736 737 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 738 mes_remove_queue_pkt.gang_context_addr = 0; 739 740 mes_remove_queue_pkt.pipe_id = input->pipe_id; 741 mes_remove_queue_pkt.queue_id = input->queue_id; 742 743 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 744 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 745 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 746 mes_remove_queue_pkt.tf_data = 747 lower_32_bits(input->trail_fence_data); 748 } else { 749 mes_remove_queue_pkt.unmap_legacy_queue = 1; 750 mes_remove_queue_pkt.queue_type = 751 convert_to_mes_queue_type(input->queue_type); 752 /* 753 * A reset-time unmap: the queue was already reset via MMIO while 754 * gangs are suspended and it is on the MES hung/fail list. Tell 755 * MES to just drop its internal state for it. Without this flag 756 * MES asks CP to unmap the already-reset (still wedged) queue 757 * again, which times out and forces a GPU reset. 758 */ 759 if (input->action == RESET_QUEUES && 760 (mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x5a) 761 mes_remove_queue_pkt.remove_queue_after_reset = 1; 762 763 } 764 765 if (mes->adev->enable_uni_mes) { 766 /* Keep scheduler queue on KIQ pipe; unmap all other kernel queues on sched pipe. */ 767 if (input->queue_type == AMDGPU_RING_TYPE_MES) 768 pipe = AMDGPU_MES_KIQ_PIPE; 769 else 770 pipe = AMDGPU_MES_SCHED_PIPE; 771 } else { 772 pipe = AMDGPU_MES_SCHED_PIPE; 773 } 774 775 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 776 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 777 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 778 } 779 780 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 781 struct mes_suspend_gang_input *input) 782 { 783 union MESAPI__SUSPEND mes_suspend_gang_pkt; 784 785 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 786 787 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 788 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 789 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 790 791 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 792 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 793 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 794 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 795 796 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 797 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 798 offsetof(union MESAPI__SUSPEND, api_status)); 799 } 800 801 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 802 struct mes_resume_gang_input *input) 803 { 804 union MESAPI__RESUME mes_resume_gang_pkt; 805 806 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 807 808 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 809 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 810 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 811 812 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 813 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 814 815 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 816 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 817 offsetof(union MESAPI__RESUME, api_status)); 818 } 819 820 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 821 { 822 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 823 824 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 825 826 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 827 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 828 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 829 830 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 831 &mes_status_pkt, sizeof(mes_status_pkt), 832 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 833 } 834 835 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 836 struct mes_misc_op_input *input) 837 { 838 union MESAPI__MISC misc_pkt; 839 int pipe; 840 841 if (mes->adev->enable_uni_mes) 842 pipe = AMDGPU_MES_KIQ_PIPE; 843 else 844 pipe = AMDGPU_MES_SCHED_PIPE; 845 846 memset(&misc_pkt, 0, sizeof(misc_pkt)); 847 848 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 849 misc_pkt.header.opcode = MES_SCH_API_MISC; 850 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 851 852 switch (input->op) { 853 case MES_MISC_OP_READ_REG: 854 misc_pkt.opcode = MESAPI_MISC__READ_REG; 855 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 856 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 857 break; 858 case MES_MISC_OP_WRITE_REG: 859 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 860 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 861 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 862 break; 863 case MES_MISC_OP_WRM_REG_WAIT: 864 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 865 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 866 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 867 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 868 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 869 misc_pkt.wait_reg_mem.reg_offset2 = 0; 870 break; 871 case MES_MISC_OP_WRM_REG_WR_WAIT: 872 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 873 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 874 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 875 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 876 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 877 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 878 break; 879 case MES_MISC_OP_SET_SHADER_DEBUGGER: 880 pipe = AMDGPU_MES_SCHED_PIPE; 881 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 882 misc_pkt.set_shader_debugger.process_context_addr = 883 input->set_shader_debugger.process_context_addr; 884 misc_pkt.set_shader_debugger.flags.u32all = 885 input->set_shader_debugger.flags.u32all; 886 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 887 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 888 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 889 input->set_shader_debugger.tcp_watch_cntl, 890 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 891 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 892 break; 893 case MES_MISC_OP_CHANGE_CONFIG: 894 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 895 misc_pkt.change_config.opcode = 896 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 897 misc_pkt.change_config.option.bits.limit_single_process = 898 input->change_config.option.limit_single_process; 899 break; 900 901 default: 902 DRM_ERROR("unsupported misc op (%d)\n", input->op); 903 return -EINVAL; 904 } 905 906 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 907 &misc_pkt, sizeof(misc_pkt), 908 offsetof(union MESAPI__MISC, api_status)); 909 } 910 911 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 912 { 913 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 914 915 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 916 917 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 918 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 919 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 920 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa; 921 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr = 922 mes->resource_1_gpu_addr[pipe]; 923 924 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 925 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 926 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 927 } 928 929 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 930 { 931 int i; 932 struct amdgpu_device *adev = mes->adev; 933 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 934 uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ? 935 (mes->sched_version & AMDGPU_MES_VERSION_MASK) : 936 (mes->kiq_version & AMDGPU_MES_VERSION_MASK); 937 938 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 939 940 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 941 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 942 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 943 944 if (pipe == AMDGPU_MES_SCHED_PIPE) { 945 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 946 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 947 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 948 mes_set_hw_res_pkt.paging_vmid = 0; 949 950 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 951 mes_set_hw_res_pkt.compute_hqd_mask[i] = 952 mes->compute_hqd_mask[i]; 953 954 for (i = 0; i < MAX_GFX_PIPES; i++) 955 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 956 mes->gfx_hqd_mask[i]; 957 958 for (i = 0; i < MAX_SDMA_PIPES; i++) 959 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 960 mes->sdma_hqd_mask[i]; 961 962 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 963 mes_set_hw_res_pkt.aggregated_doorbells[i] = 964 mes->aggregated_doorbells[i]; 965 } 966 967 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 968 mes->sch_ctx_gpu_addr[pipe]; 969 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 970 mes->query_status_fence_gpu_addr[pipe]; 971 972 for (i = 0; i < 5; i++) { 973 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 974 mes_set_hw_res_pkt.mmhub_base[i] = 975 adev->reg_offset[MMHUB_HWIP][0][i]; 976 mes_set_hw_res_pkt.osssys_base[i] = 977 adev->reg_offset[OSSSYS_HWIP][0][i]; 978 } 979 980 mes_set_hw_res_pkt.disable_reset = 1; 981 mes_set_hw_res_pkt.disable_mes_log = 1; 982 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 983 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 984 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 985 986 /* 987 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 988 * handling support, other queue will not use the oversubscribe timer. 989 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 990 */ 991 mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50; 992 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 993 994 if (amdgpu_mes_log_enable) { 995 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 996 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + 997 pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 998 } 999 1000 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 1001 mes_set_hw_res_pkt.limit_single_process = 1; 1002 1003 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 1004 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1005 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 1006 } 1007 1008 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 1009 { 1010 struct amdgpu_device *adev = mes->adev; 1011 uint32_t data; 1012 1013 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 1014 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 1015 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 1016 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 1017 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 1018 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 1019 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 1020 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 1021 1022 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 1023 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 1024 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 1025 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 1026 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 1027 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 1028 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 1029 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 1030 1031 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 1032 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 1033 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 1034 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 1035 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 1036 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 1037 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 1038 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 1039 1040 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 1041 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 1042 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 1043 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 1044 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 1045 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 1046 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 1047 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 1048 1049 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 1050 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 1051 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 1052 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 1053 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 1054 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 1055 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 1056 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 1057 1058 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 1059 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 1060 } 1061 1062 1063 static void mes_v12_0_enable_unmapped_doorbell_handling( 1064 struct amdgpu_mes *mes, bool enable) 1065 { 1066 struct amdgpu_device *adev = mes->adev; 1067 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 1068 1069 /* 1070 * The default PROC_LSB settng is 0xc which means doorbell 1071 * addr[16:12] gives the doorbell page number. For kfd, each 1072 * process will use 2 pages of doorbell, we need to change the 1073 * setting to 0xd 1074 */ 1075 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 1076 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 1077 1078 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 1079 1080 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 1081 } 1082 1083 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 1084 struct mes_reset_queue_input *input) 1085 { 1086 union MESAPI__RESET mes_reset_queue_pkt; 1087 int pipe; 1088 1089 if (input->use_mmio) { 1090 int r = mes_v12_0_reset_queue_mmio(mes, input->queue_type, 1091 input->me_id, input->pipe_id, 1092 input->queue_id, input->vmid); 1093 if (r) 1094 return mes_v12_0_reset_pipe_mmio(mes, input->queue_type, 1095 input->me_id, input->pipe_id, 1096 input->queue_id, input->vmid); 1097 return 0; 1098 } 1099 1100 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1101 1102 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1103 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1104 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1105 1106 mes_reset_queue_pkt.queue_type = 1107 convert_to_mes_queue_type(input->queue_type); 1108 1109 if (input->legacy_gfx) { 1110 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1111 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1112 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1113 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1114 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1115 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1116 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1117 } else { 1118 mes_reset_queue_pkt.reset_queue_only = 1; 1119 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1120 } 1121 1122 pipe = AMDGPU_MES_SCHED_PIPE; 1123 1124 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 1125 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1126 offsetof(union MESAPI__RESET, api_status)); 1127 } 1128 1129 static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1130 struct mes_detect_and_reset_queue_input *input) 1131 { 1132 union MESAPI__RESET mes_reset_queue_pkt; 1133 1134 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1135 1136 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1137 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1138 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1139 1140 mes_reset_queue_pkt.queue_type = 1141 convert_to_mes_queue_type(input->queue_type); 1142 mes_reset_queue_pkt.doorbell_offset_addr = 1143 mes->hung_queue_db_array_gpu_addr[0]; 1144 1145 if (input->detect_only) 1146 mes_reset_queue_pkt.hang_detect_only = 1; 1147 else 1148 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1149 1150 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 1151 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1152 offsetof(union MESAPI__RESET, api_status)); 1153 } 1154 1155 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 1156 { 1157 /* 1158 * MES doesn't support invalidate gc_hub on slave xcc individually 1159 * master xcc will invalidate all gc_hub for the partition 1160 */ 1161 if (AMDGPU_IS_GFXHUB(id)) 1162 return 0; 1163 else if (AMDGPU_IS_MMHUB0(id)) 1164 return 1; 1165 else 1166 return -EINVAL; 1167 1168 } 1169 1170 static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, 1171 struct mes_inv_tlbs_pasid_input *input) 1172 { 1173 union MESAPI__INV_TLBS mes_inv_tlbs; 1174 int ret; 1175 1176 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 1177 1178 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 1179 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 1180 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1181 1182 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 1183 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 1184 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 1185 1186 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 1187 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 1188 if (ret < 0) 1189 return -EINVAL; 1190 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 1191 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, 1192 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 1193 offsetof(union MESAPI__INV_TLBS, api_status)); 1194 1195 } 1196 1197 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 1198 .add_hw_queue = mes_v12_0_add_hw_queue, 1199 .remove_hw_queue = mes_v12_0_remove_hw_queue, 1200 .map_legacy_queue = mes_v12_0_map_legacy_queue, 1201 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 1202 .suspend_gang = mes_v12_0_suspend_gang, 1203 .resume_gang = mes_v12_0_resume_gang, 1204 .misc_op = mes_v12_0_misc_op, 1205 .reset_hw_queue = mes_v12_0_reset_hw_queue, 1206 .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, 1207 .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, 1208 }; 1209 1210 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1211 enum amdgpu_mes_pipe pipe) 1212 { 1213 int r; 1214 const struct mes_firmware_header_v1_0 *mes_hdr; 1215 const __le32 *fw_data; 1216 unsigned fw_size; 1217 1218 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1219 adev->mes.fw[pipe]->data; 1220 1221 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1222 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1223 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1224 1225 r = amdgpu_bo_create_reserved(adev, fw_size, 1226 PAGE_SIZE, 1227 AMDGPU_GEM_DOMAIN_VRAM, 1228 &adev->mes.ucode_fw_obj[pipe], 1229 &adev->mes.ucode_fw_gpu_addr[pipe], 1230 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1231 if (r) { 1232 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1233 return r; 1234 } 1235 1236 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1237 1238 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1239 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1240 1241 return 0; 1242 } 1243 1244 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1245 enum amdgpu_mes_pipe pipe) 1246 { 1247 int r; 1248 const struct mes_firmware_header_v1_0 *mes_hdr; 1249 const __le32 *fw_data; 1250 unsigned fw_size; 1251 1252 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1253 adev->mes.fw[pipe]->data; 1254 1255 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1256 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1257 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1258 1259 r = amdgpu_bo_create_reserved(adev, fw_size, 1260 64 * 1024, 1261 AMDGPU_GEM_DOMAIN_VRAM, 1262 &adev->mes.data_fw_obj[pipe], 1263 &adev->mes.data_fw_gpu_addr[pipe], 1264 (void **)&adev->mes.data_fw_ptr[pipe]); 1265 if (r) { 1266 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1267 return r; 1268 } 1269 1270 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1271 1272 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1273 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1274 1275 return 0; 1276 } 1277 1278 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 1279 enum amdgpu_mes_pipe pipe) 1280 { 1281 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1282 &adev->mes.data_fw_gpu_addr[pipe], 1283 (void **)&adev->mes.data_fw_ptr[pipe]); 1284 1285 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1286 &adev->mes.ucode_fw_gpu_addr[pipe], 1287 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1288 } 1289 1290 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 1291 { 1292 uint64_t ucode_addr; 1293 uint32_t pipe, data = 0; 1294 1295 if (enable) { 1296 mutex_lock(&adev->srbm_mutex); 1297 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1298 soc24_grbm_select(adev, 3, pipe, 0, 0); 1299 if (amdgpu_mes_log_enable) { 1300 u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1301 /* In case uni mes is not enabled, only program for pipe 0 */ 1302 if (adev->mes.event_log_size >= (pipe + 1) * log_size) { 1303 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1304 lower_32_bits(adev->mes.event_log_gpu_addr + 1305 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1306 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1307 upper_32_bits(adev->mes.event_log_gpu_addr + 1308 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1309 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1310 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1311 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1312 } 1313 } 1314 1315 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1316 if (pipe == 0) 1317 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1318 else 1319 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1320 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1321 1322 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1323 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1324 lower_32_bits(ucode_addr)); 1325 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1326 upper_32_bits(ucode_addr)); 1327 1328 /* unhalt MES and activate one pipe each loop */ 1329 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1330 if (pipe) 1331 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1332 dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data); 1333 1334 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1335 1336 } 1337 soc24_grbm_select(adev, 0, 0, 0, 0); 1338 mutex_unlock(&adev->srbm_mutex); 1339 1340 if (amdgpu_emu_mode) 1341 msleep(100); 1342 else if (adev->enable_uni_mes) 1343 udelay(500); 1344 else 1345 udelay(50); 1346 } else { 1347 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1348 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1349 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1350 data = REG_SET_FIELD(data, CP_MES_CNTL, 1351 MES_INVALIDATE_ICACHE, 1); 1352 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1353 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1354 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1355 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1356 } 1357 } 1358 1359 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 1360 { 1361 uint64_t ucode_addr; 1362 int pipe; 1363 1364 mes_v12_0_enable(adev, false); 1365 1366 mutex_lock(&adev->srbm_mutex); 1367 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1368 /* me=3, queue=0 */ 1369 soc24_grbm_select(adev, 3, pipe, 0, 0); 1370 1371 /* set ucode start address */ 1372 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1373 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1374 lower_32_bits(ucode_addr)); 1375 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1376 upper_32_bits(ucode_addr)); 1377 1378 soc24_grbm_select(adev, 0, 0, 0, 0); 1379 } 1380 mutex_unlock(&adev->srbm_mutex); 1381 } 1382 1383 /* This function is for backdoor MES firmware */ 1384 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 1385 enum amdgpu_mes_pipe pipe, bool prime_icache) 1386 { 1387 int r; 1388 uint32_t data; 1389 1390 mes_v12_0_enable(adev, false); 1391 1392 if (!adev->mes.fw[pipe]) 1393 return -EINVAL; 1394 1395 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 1396 if (r) 1397 return r; 1398 1399 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 1400 if (r) { 1401 mes_v12_0_free_ucode_buffers(adev, pipe); 1402 return r; 1403 } 1404 1405 mutex_lock(&adev->srbm_mutex); 1406 /* me=3, pipe=0, queue=0 */ 1407 soc24_grbm_select(adev, 3, pipe, 0, 0); 1408 1409 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1410 1411 /* set ucode fimrware address */ 1412 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1413 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1414 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1415 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1416 1417 /* set ucode instruction cache boundary to 2M-1 */ 1418 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1419 1420 /* set ucode data firmware address */ 1421 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1422 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1423 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1424 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1425 1426 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1427 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1428 1429 if (prime_icache) { 1430 /* invalidate ICACHE */ 1431 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1432 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1433 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1434 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1435 1436 /* prime the ICACHE. */ 1437 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1438 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1439 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1440 } 1441 1442 soc24_grbm_select(adev, 0, 0, 0, 0); 1443 mutex_unlock(&adev->srbm_mutex); 1444 1445 return 0; 1446 } 1447 1448 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 1449 enum amdgpu_mes_pipe pipe) 1450 { 1451 int r; 1452 u32 *eop; 1453 1454 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1455 AMDGPU_GEM_DOMAIN_GTT, 1456 &adev->mes.eop_gpu_obj[pipe], 1457 &adev->mes.eop_gpu_addr[pipe], 1458 (void **)&eop); 1459 if (r) { 1460 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1461 return r; 1462 } 1463 1464 memset(eop, 0, 1465 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1466 1467 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1468 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1469 1470 return 0; 1471 } 1472 1473 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 1474 { 1475 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1476 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1477 uint32_t tmp; 1478 1479 mqd->header = 0xC0310800; 1480 mqd->compute_pipelinestat_enable = 0x00000001; 1481 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1482 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1483 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1484 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1485 mqd->compute_misc_reserved = 0x00000007; 1486 1487 eop_base_addr = ring->eop_gpu_addr >> 8; 1488 1489 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1490 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1491 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1492 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1493 1494 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1495 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1496 mqd->cp_hqd_eop_control = tmp; 1497 1498 /* disable the queue if it's active */ 1499 ring->wptr = 0; 1500 mqd->cp_hqd_pq_rptr = 0; 1501 mqd->cp_hqd_pq_wptr_lo = 0; 1502 mqd->cp_hqd_pq_wptr_hi = 0; 1503 1504 /* set the pointer to the MQD */ 1505 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1506 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1507 1508 /* set MQD vmid to 0 */ 1509 tmp = regCP_MQD_CONTROL_DEFAULT; 1510 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1511 mqd->cp_mqd_control = tmp; 1512 1513 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1514 hqd_gpu_addr = ring->gpu_addr >> 8; 1515 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1516 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1517 1518 /* set the wb address whether it's enabled or not */ 1519 wb_gpu_addr = ring->rptr_gpu_addr; 1520 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1521 mqd->cp_hqd_pq_rptr_report_addr_hi = 1522 upper_32_bits(wb_gpu_addr) & 0xffff; 1523 1524 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1525 wb_gpu_addr = ring->wptr_gpu_addr; 1526 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1527 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1528 1529 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1530 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1532 (order_base_2(ring->ring_size / 4) - 1)); 1533 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1534 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1540 mqd->cp_hqd_pq_control = tmp; 1541 1542 /* enable doorbell */ 1543 tmp = 0; 1544 if (ring->use_doorbell) { 1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1546 DOORBELL_OFFSET, ring->doorbell_index); 1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1548 DOORBELL_EN, 1); 1549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1550 DOORBELL_SOURCE, 0); 1551 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1552 DOORBELL_HIT, 0); 1553 } else { 1554 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1555 DOORBELL_EN, 0); 1556 } 1557 mqd->cp_hqd_pq_doorbell_control = tmp; 1558 1559 mqd->cp_hqd_vmid = 0; 1560 /* activate the queue */ 1561 mqd->cp_hqd_active = 1; 1562 1563 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1564 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1565 PRELOAD_SIZE, 0x55); 1566 mqd->cp_hqd_persistent_state = tmp; 1567 1568 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1569 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1570 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1571 1572 /* 1573 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1574 * doorbell handling. This is a reserved CP internal register can 1575 * not be accesss by others 1576 */ 1577 mqd->reserved_184 = BIT(15); 1578 1579 return 0; 1580 } 1581 1582 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1583 { 1584 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1585 struct amdgpu_device *adev = ring->adev; 1586 uint32_t data = 0; 1587 1588 mutex_lock(&adev->srbm_mutex); 1589 soc24_grbm_select(adev, 3, ring->pipe, 0, 0); 1590 1591 /* set CP_HQD_VMID.VMID = 0. */ 1592 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1593 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1594 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1595 1596 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1597 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1598 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1599 DOORBELL_EN, 0); 1600 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1601 1602 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1603 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1604 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1605 1606 /* set CP_MQD_CONTROL.VMID=0 */ 1607 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1608 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1609 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1610 1611 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1612 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1613 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1614 1615 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1616 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1617 mqd->cp_hqd_pq_rptr_report_addr_lo); 1618 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1619 mqd->cp_hqd_pq_rptr_report_addr_hi); 1620 1621 /* set CP_HQD_PQ_CONTROL */ 1622 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1623 1624 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1625 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1626 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1627 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1628 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1629 1630 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1631 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1632 mqd->cp_hqd_pq_doorbell_control); 1633 1634 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1635 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1636 1637 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1638 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1639 1640 soc24_grbm_select(adev, 0, 0, 0, 0); 1641 mutex_unlock(&adev->srbm_mutex); 1642 } 1643 1644 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1645 { 1646 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1647 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1648 int r; 1649 1650 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1651 return -EINVAL; 1652 1653 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1654 if (r) { 1655 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1656 return r; 1657 } 1658 1659 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1660 1661 r = amdgpu_ring_test_ring(kiq_ring); 1662 if (r) { 1663 DRM_ERROR("kfq enable failed\n"); 1664 kiq_ring->sched.ready = false; 1665 } 1666 return r; 1667 } 1668 1669 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1670 enum amdgpu_mes_pipe pipe) 1671 { 1672 struct amdgpu_ring *ring; 1673 int r; 1674 1675 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1676 ring = &adev->gfx.kiq[0].ring; 1677 else 1678 ring = &adev->mes.ring[pipe]; 1679 1680 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1681 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1682 *(ring->wptr_cpu_addr) = 0; 1683 *(ring->rptr_cpu_addr) = 0; 1684 amdgpu_ring_clear_ring(ring); 1685 } 1686 1687 r = mes_v12_0_mqd_init(ring); 1688 if (r) 1689 return r; 1690 1691 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1692 if (adev->enable_uni_mes) 1693 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 1694 else 1695 r = mes_v12_0_kiq_enable_queue(adev); 1696 if (r) 1697 return r; 1698 } else { 1699 mes_v12_0_queue_init_register(ring); 1700 } 1701 1702 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) || 1703 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) { 1704 /* get MES scheduler/KIQ versions */ 1705 mutex_lock(&adev->srbm_mutex); 1706 soc24_grbm_select(adev, 3, pipe, 0, 0); 1707 1708 if (pipe == AMDGPU_MES_SCHED_PIPE) 1709 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1710 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1711 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1712 1713 soc24_grbm_select(adev, 0, 0, 0, 0); 1714 mutex_unlock(&adev->srbm_mutex); 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1721 { 1722 struct amdgpu_ring *ring; 1723 1724 ring = &adev->mes.ring[pipe]; 1725 1726 ring->funcs = &mes_v12_0_ring_funcs; 1727 1728 ring->me = 3; 1729 ring->pipe = pipe; 1730 ring->queue = 0; 1731 1732 ring->ring_obj = NULL; 1733 ring->use_doorbell = true; 1734 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1735 ring->no_scheduler = true; 1736 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1737 1738 if (pipe == AMDGPU_MES_SCHED_PIPE) 1739 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1740 else 1741 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1742 1743 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1744 AMDGPU_RING_PRIO_DEFAULT, NULL); 1745 } 1746 1747 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1748 { 1749 struct amdgpu_ring *ring; 1750 1751 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1752 1753 ring = &adev->gfx.kiq[0].ring; 1754 1755 ring->me = 3; 1756 ring->pipe = 1; 1757 ring->queue = 0; 1758 1759 ring->adev = NULL; 1760 ring->ring_obj = NULL; 1761 ring->use_doorbell = true; 1762 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1763 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1764 ring->no_scheduler = true; 1765 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1766 ring->me, ring->pipe, ring->queue); 1767 1768 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1769 AMDGPU_RING_PRIO_DEFAULT, NULL); 1770 } 1771 1772 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1773 enum amdgpu_mes_pipe pipe) 1774 { 1775 int r, mqd_size = sizeof(struct v12_compute_mqd); 1776 struct amdgpu_ring *ring; 1777 1778 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1779 ring = &adev->gfx.kiq[0].ring; 1780 else 1781 ring = &adev->mes.ring[pipe]; 1782 1783 if (ring->mqd_obj) 1784 return 0; 1785 1786 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1787 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1788 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1789 if (r) { 1790 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1791 return r; 1792 } 1793 1794 memset(ring->mqd_ptr, 0, mqd_size); 1795 1796 /* prepare MQD backup */ 1797 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1798 if (!adev->mes.mqd_backup[pipe]) 1799 dev_warn(adev->dev, 1800 "no memory to create MQD backup for ring %s\n", 1801 ring->name); 1802 1803 return 0; 1804 } 1805 1806 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1807 { 1808 struct amdgpu_device *adev = ip_block->adev; 1809 int pipe, r; 1810 1811 adev->mes.funcs = &mes_v12_0_funcs; 1812 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1813 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1814 adev->mes.enable_legacy_queue_map = true; 1815 1816 adev->mes.event_log_size = adev->enable_uni_mes ? 1817 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : 1818 (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 1819 r = amdgpu_mes_init(adev); 1820 if (r) 1821 return r; 1822 1823 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1824 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1825 if (r) 1826 return r; 1827 1828 r = mes_v12_0_mqd_sw_init(adev, pipe); 1829 if (r) 1830 return r; 1831 1832 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) { 1833 r = mes_v12_0_kiq_ring_init(adev); 1834 } 1835 else { 1836 r = mes_v12_0_ring_init(adev, pipe); 1837 if (r) 1838 return r; 1839 r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1840 AMDGPU_GEM_DOMAIN_VRAM, 1841 &adev->mes.resource_1[pipe], 1842 &adev->mes.resource_1_gpu_addr[pipe], 1843 &adev->mes.resource_1_addr[pipe]); 1844 if (r) { 1845 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe); 1846 return r; 1847 } 1848 } 1849 } 1850 1851 return 0; 1852 } 1853 1854 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1855 { 1856 struct amdgpu_device *adev = ip_block->adev; 1857 int pipe; 1858 1859 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1860 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], 1861 &adev->mes.resource_1_gpu_addr[pipe], 1862 &adev->mes.resource_1_addr[pipe]); 1863 1864 kfree(adev->mes.mqd_backup[pipe]); 1865 1866 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1867 &adev->mes.eop_gpu_addr[pipe], 1868 NULL); 1869 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1870 1871 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1872 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1873 &adev->mes.ring[pipe].mqd_gpu_addr, 1874 &adev->mes.ring[pipe].mqd_ptr); 1875 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1876 } 1877 } 1878 1879 if (!adev->enable_uni_mes) { 1880 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1881 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1882 &adev->gfx.kiq[0].ring.mqd_ptr); 1883 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1884 } 1885 1886 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1887 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1888 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1889 } 1890 1891 amdgpu_mes_fini(adev); 1892 return 0; 1893 } 1894 1895 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1896 { 1897 uint32_t data; 1898 int i; 1899 1900 mutex_lock(&adev->srbm_mutex); 1901 soc24_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1902 1903 /* disable the queue if it's active */ 1904 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1905 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1906 for (i = 0; i < adev->usec_timeout; i++) { 1907 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1908 break; 1909 udelay(1); 1910 } 1911 } 1912 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1913 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1914 DOORBELL_EN, 0); 1915 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1916 DOORBELL_HIT, 1); 1917 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1918 1919 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1920 1921 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1922 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1923 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1924 1925 soc24_grbm_select(adev, 0, 0, 0, 0); 1926 mutex_unlock(&adev->srbm_mutex); 1927 1928 adev->mes.ring[0].sched.ready = false; 1929 } 1930 1931 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1932 { 1933 uint32_t tmp; 1934 struct amdgpu_device *adev = ring->adev; 1935 1936 /* tell RLC which is KIQ queue */ 1937 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1938 tmp &= 0xffffff00; 1939 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1940 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1941 } 1942 1943 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1944 { 1945 int r = 0; 1946 struct amdgpu_ip_block *ip_block; 1947 1948 if (adev->enable_uni_mes) 1949 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1950 else 1951 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1952 1953 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1954 1955 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1956 if (r) { 1957 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1958 return r; 1959 } 1960 1961 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1962 if (r) { 1963 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1964 return r; 1965 } 1966 1967 mes_v12_0_set_ucode_start_addr(adev); 1968 1969 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1970 mes_v12_0_set_ucode_start_addr(adev); 1971 1972 mes_v12_0_enable(adev, true); 1973 1974 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1975 if (unlikely(!ip_block)) { 1976 dev_err(adev->dev, "Failed to get MES handle\n"); 1977 return -EINVAL; 1978 } 1979 1980 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1981 if (r) 1982 goto failure; 1983 1984 if (adev->enable_uni_mes) { 1985 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1986 if (r) 1987 goto failure; 1988 1989 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1990 } 1991 1992 if (adev->mes.enable_legacy_queue_map) { 1993 r = mes_v12_0_hw_init(ip_block); 1994 if (r) 1995 goto failure; 1996 } 1997 1998 return r; 1999 2000 failure: 2001 mes_v12_0_hw_fini(ip_block); 2002 return r; 2003 } 2004 2005 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 2006 { 2007 if (adev->mes.ring[0].sched.ready) { 2008 if (adev->enable_uni_mes) 2009 amdgpu_mes_unmap_legacy_queue(adev, 2010 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 2011 RESET_QUEUES, 0, 0, 0); 2012 else 2013 mes_v12_0_kiq_dequeue_sched(adev); 2014 2015 adev->mes.ring[0].sched.ready = false; 2016 } 2017 2018 mes_v12_0_enable(adev, false); 2019 2020 return 0; 2021 } 2022 2023 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 2024 { 2025 int r; 2026 struct amdgpu_device *adev = ip_block->adev; 2027 2028 if (adev->mes.ring[0].sched.ready) 2029 goto out; 2030 2031 if (!adev->enable_mes_kiq) { 2032 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2033 r = mes_v12_0_load_microcode(adev, 2034 AMDGPU_MES_SCHED_PIPE, true); 2035 if (r) { 2036 DRM_ERROR("failed to MES fw, r=%d\n", r); 2037 return r; 2038 } 2039 2040 mes_v12_0_set_ucode_start_addr(adev); 2041 2042 } else if (adev->firmware.load_type == 2043 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2044 2045 mes_v12_0_set_ucode_start_addr(adev); 2046 } 2047 2048 mes_v12_0_enable(adev, true); 2049 } 2050 2051 /* Enable the MES to handle doorbell ring on unmapped queue */ 2052 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 2053 2054 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 2055 if (r) 2056 goto failure; 2057 2058 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 2059 if (r) 2060 goto failure; 2061 2062 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b) 2063 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 2064 2065 mes_v12_0_init_aggregated_doorbell(&adev->mes); 2066 2067 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 2068 if (r) { 2069 DRM_ERROR("MES is busy\n"); 2070 goto failure; 2071 } 2072 2073 r = amdgpu_mes_update_enforce_isolation(adev); 2074 if (r) 2075 goto failure; 2076 2077 amdgpu_mes_validate_fw_version(adev); 2078 out: 2079 /* 2080 * Disable KIQ ring usage from the driver once MES is enabled. 2081 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 2082 * with MES enabled. 2083 */ 2084 adev->gfx.kiq[0].ring.sched.ready = false; 2085 adev->mes.ring[0].sched.ready = true; 2086 2087 return 0; 2088 2089 failure: 2090 mes_v12_0_hw_fini(ip_block); 2091 return r; 2092 } 2093 2094 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 2095 { 2096 return 0; 2097 } 2098 2099 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) 2100 { 2101 return mes_v12_0_hw_fini(ip_block); 2102 } 2103 2104 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) 2105 { 2106 return mes_v12_0_hw_init(ip_block); 2107 } 2108 2109 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) 2110 { 2111 struct amdgpu_device *adev = ip_block->adev; 2112 int pipe, r; 2113 2114 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 2115 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 2116 2117 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 2118 r = amdgpu_mes_init_microcode(adev, pipe); 2119 if (r) 2120 return r; 2121 } 2122 2123 return 0; 2124 } 2125 2126 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 2127 .name = "mes_v12_0", 2128 .early_init = mes_v12_0_early_init, 2129 .late_init = NULL, 2130 .sw_init = mes_v12_0_sw_init, 2131 .sw_fini = mes_v12_0_sw_fini, 2132 .hw_init = mes_v12_0_hw_init, 2133 .hw_fini = mes_v12_0_hw_fini, 2134 .suspend = mes_v12_0_suspend, 2135 .resume = mes_v12_0_resume, 2136 }; 2137 2138 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 2139 .type = AMD_IP_BLOCK_TYPE_MES, 2140 .major = 12, 2141 .minor = 0, 2142 .rev = 0, 2143 .funcs = &mes_v12_0_ip_funcs, 2144 }; 2145