1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "gfx_v12_0.h" 28 #include "soc15_common.h" 29 #include "soc24.h" 30 #include "gc/gc_12_0_0_offset.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v12_structs.h" 34 #include "mes_v12_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 42 43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); 45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 47 48 #define MES_EOP_SIZE 2048 49 50 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 #define MES12_HUNG_HQD_INFO_OFFSET 4 52 53 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 54 { 55 struct amdgpu_device *adev = ring->adev; 56 57 if (ring->use_doorbell) { 58 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 59 ring->wptr); 60 WDOORBELL64(ring->doorbell_index, ring->wptr); 61 } else { 62 BUG(); 63 } 64 } 65 66 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 67 { 68 return *ring->rptr_cpu_addr; 69 } 70 71 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 72 { 73 u64 wptr; 74 75 if (ring->use_doorbell) 76 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 77 else 78 BUG(); 79 return wptr; 80 } 81 82 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 83 .type = AMDGPU_RING_TYPE_MES, 84 .align_mask = 1, 85 .nop = 0, 86 .support_64bit_ptrs = true, 87 .get_rptr = mes_v12_0_ring_get_rptr, 88 .get_wptr = mes_v12_0_ring_get_wptr, 89 .set_wptr = mes_v12_0_ring_set_wptr, 90 .insert_nop = amdgpu_ring_insert_nop, 91 }; 92 93 static const char *mes_v12_0_opcodes[] = { 94 "SET_HW_RSRC", 95 "SET_SCHEDULING_CONFIG", 96 "ADD_QUEUE", 97 "REMOVE_QUEUE", 98 "PERFORM_YIELD", 99 "SET_GANG_PRIORITY_LEVEL", 100 "SUSPEND", 101 "RESUME", 102 "RESET", 103 "SET_LOG_BUFFER", 104 "CHANGE_GANG_PRORITY", 105 "QUERY_SCHEDULER_STATUS", 106 "unused", 107 "SET_DEBUG_VMID", 108 "MISC", 109 "UPDATE_ROOT_PAGE_TABLE", 110 "AMD_LOG", 111 "SET_SE_MODE", 112 "SET_GANG_SUBMIT", 113 "SET_HW_RSRC_1", 114 "INVALIDATE_TLBS", 115 }; 116 117 static const char *mes_v12_0_misc_opcodes[] = { 118 "WRITE_REG", 119 "INV_GART", 120 "QUERY_STATUS", 121 "READ_REG", 122 "WAIT_REG_MEM", 123 "SET_SHADER_DEBUGGER", 124 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 125 "NOTIFY_TO_UNMAP_PROCESSES", 126 }; 127 128 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 129 { 130 const char *op_str = NULL; 131 132 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 133 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 134 135 return op_str; 136 } 137 138 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 139 { 140 const char *op_str = NULL; 141 142 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 143 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 144 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 145 146 return op_str; 147 } 148 149 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 150 int pipe, void *pkt, int size, 151 int api_status_off) 152 { 153 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 154 signed long timeout = 2100000; /* 2100 ms */ 155 struct amdgpu_device *adev = mes->adev; 156 struct amdgpu_ring *ring = &mes->ring[pipe]; 157 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 158 struct MES_API_STATUS *api_status; 159 union MESAPI__MISC *x_pkt = pkt; 160 const char *op_str, *misc_op_str; 161 unsigned long flags; 162 u64 status_gpu_addr; 163 u32 seq, status_offset; 164 u64 *status_ptr; 165 signed long r; 166 int ret; 167 168 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 169 return -EINVAL; 170 171 if (amdgpu_emu_mode) { 172 timeout *= 100; 173 } else if (amdgpu_sriov_vf(adev)) { 174 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 175 timeout = 15 * 600 * 1000; 176 } 177 178 ret = amdgpu_wb_get(adev, &status_offset); 179 if (ret) 180 return ret; 181 182 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 183 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 184 *status_ptr = 0; 185 186 spin_lock_irqsave(ring_lock, flags); 187 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 188 if (r) 189 goto error_unlock_free; 190 191 seq = ++ring->fence_drv.sync_seq; 192 r = amdgpu_fence_wait_polling(ring, 193 seq - ring->fence_drv.num_fences_mask, 194 timeout); 195 if (r < 1) 196 goto error_undo; 197 198 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 199 api_status->api_completion_fence_addr = status_gpu_addr; 200 api_status->api_completion_fence_value = 1; 201 202 amdgpu_ring_write_multiple(ring, pkt, size / 4); 203 204 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 205 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 206 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 207 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 208 mes_status_pkt.api_status.api_completion_fence_addr = 209 ring->fence_drv.gpu_addr; 210 mes_status_pkt.api_status.api_completion_fence_value = seq; 211 212 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 213 sizeof(mes_status_pkt) / 4); 214 215 amdgpu_ring_commit(ring); 216 spin_unlock_irqrestore(ring_lock, flags); 217 218 op_str = mes_v12_0_get_op_string(x_pkt); 219 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 220 221 if (misc_op_str) 222 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 223 pipe, op_str, misc_op_str); 224 else if (op_str) 225 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 226 pipe, op_str); 227 else 228 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 229 pipe, x_pkt->header.opcode); 230 231 r = amdgpu_fence_wait_polling(ring, seq, timeout); 232 233 /* 234 * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success). 235 * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information. 236 */ 237 if (r < 1 || !(lower_32_bits(*status_ptr))) { 238 239 if (misc_op_str) 240 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 241 pipe, op_str, misc_op_str); 242 else if (op_str) 243 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 244 pipe, op_str); 245 else 246 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 247 pipe, x_pkt->header.opcode); 248 249 while (halt_if_hws_hang) 250 schedule(); 251 252 r = -ETIMEDOUT; 253 goto error_wb_free; 254 } 255 256 amdgpu_wb_free(adev, status_offset); 257 return 0; 258 259 error_undo: 260 dev_err(adev->dev, "MES ring buffer is full.\n"); 261 amdgpu_ring_undo(ring); 262 263 error_unlock_free: 264 spin_unlock_irqrestore(ring_lock, flags); 265 266 error_wb_free: 267 amdgpu_wb_free(adev, status_offset); 268 return r; 269 } 270 271 static int convert_to_mes_queue_type(int queue_type) 272 { 273 if (queue_type == AMDGPU_RING_TYPE_GFX) 274 return MES_QUEUE_TYPE_GFX; 275 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 276 return MES_QUEUE_TYPE_COMPUTE; 277 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 278 return MES_QUEUE_TYPE_SDMA; 279 else if (queue_type == AMDGPU_RING_TYPE_MES) 280 return MES_QUEUE_TYPE_SCHQ; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int convert_to_mes_priority_level(int priority_level) 287 { 288 switch (priority_level) { 289 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 290 return AMD_PRIORITY_LEVEL_LOW; 291 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 292 default: 293 return AMD_PRIORITY_LEVEL_NORMAL; 294 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 295 return AMD_PRIORITY_LEVEL_MEDIUM; 296 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 297 return AMD_PRIORITY_LEVEL_HIGH; 298 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 299 return AMD_PRIORITY_LEVEL_REALTIME; 300 } 301 } 302 303 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 304 struct mes_add_queue_input *input) 305 { 306 struct amdgpu_device *adev = mes->adev; 307 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 308 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 309 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 310 311 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 312 313 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 314 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 315 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 316 317 mes_add_queue_pkt.process_id = input->process_id; 318 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 319 mes_add_queue_pkt.process_va_start = input->process_va_start; 320 mes_add_queue_pkt.process_va_end = input->process_va_end; 321 mes_add_queue_pkt.process_quantum = input->process_quantum; 322 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 323 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 324 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 325 mes_add_queue_pkt.inprocess_gang_priority = 326 convert_to_mes_priority_level(input->inprocess_gang_priority); 327 mes_add_queue_pkt.gang_global_priority_level = 328 convert_to_mes_priority_level(input->gang_global_priority_level); 329 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 330 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 331 332 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 333 334 mes_add_queue_pkt.queue_type = 335 convert_to_mes_queue_type(input->queue_type); 336 mes_add_queue_pkt.paging = input->paging; 337 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 338 mes_add_queue_pkt.gws_base = input->gws_base; 339 mes_add_queue_pkt.gws_size = input->gws_size; 340 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 341 mes_add_queue_pkt.tma_addr = input->tma_addr; 342 mes_add_queue_pkt.trap_en = input->trap_en; 343 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 344 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 345 346 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 347 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 348 mes_add_queue_pkt.gds_size = input->queue_size; 349 350 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 351 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 352 mes_add_queue_pkt.gds_size = input->queue_size; 353 354 return mes_v12_0_submit_pkt_and_poll_completion(mes, 355 AMDGPU_MES_SCHED_PIPE, 356 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 357 offsetof(union MESAPI__ADD_QUEUE, api_status)); 358 } 359 360 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 361 struct mes_remove_queue_input *input) 362 { 363 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 364 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 365 366 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 367 368 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 369 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 370 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 371 372 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 373 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 374 mes_remove_queue_pkt.queue_type = 375 convert_to_mes_queue_type(input->queue_type); 376 377 if (mes_rev >= 0x5a) 378 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 379 380 return mes_v12_0_submit_pkt_and_poll_completion(mes, 381 AMDGPU_MES_SCHED_PIPE, 382 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 383 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 384 } 385 386 int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev, 387 bool req) 388 { 389 u32 i, tmp, val; 390 391 for (i = 0; i < adev->usec_timeout; i++) { 392 /* Request with MeId=2, PipeId=0 */ 393 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 394 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 395 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 396 397 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 398 if (req) { 399 if (val == tmp) 400 break; 401 } else { 402 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 403 REQUEST, 1); 404 405 /* unlocked or locked by firmware */ 406 if (val != tmp) 407 break; 408 } 409 udelay(1); 410 } 411 412 if (i >= adev->usec_timeout) 413 return -EINVAL; 414 415 return 0; 416 } 417 418 static bool mes_v12_0_pipe_reset_support(struct amdgpu_device *adev) 419 { 420 /* Disable the pipe reset until the CPFW fully support it.*/ 421 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 422 return false; 423 } 424 425 static int mes_v12_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 426 u32 me, u32 pipe, u32 queue) 427 { 428 uint32_t reset_pipe = 0, clean_pipe = 0; 429 int r; 430 431 if (!mes_v12_0_pipe_reset_support(adev)) 432 return -EOPNOTSUPP; 433 434 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 435 mutex_lock(&adev->srbm_mutex); 436 soc24_grbm_select(adev, me, pipe, queue, 0); 437 438 switch (pipe) { 439 case 0: 440 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 441 PFP_PIPE0_RESET, 1); 442 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 443 ME_PIPE0_RESET, 1); 444 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 445 PFP_PIPE0_RESET, 0); 446 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 447 ME_PIPE0_RESET, 0); 448 break; 449 case 1: 450 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 451 PFP_PIPE1_RESET, 1); 452 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 453 ME_PIPE1_RESET, 1); 454 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 455 PFP_PIPE1_RESET, 0); 456 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 457 ME_PIPE1_RESET, 0); 458 break; 459 default: 460 break; 461 } 462 463 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 464 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 465 466 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 467 RS64_FW_UC_START_ADDR_LO; 468 soc24_grbm_select(adev, 0, 0, 0, 0); 469 mutex_unlock(&adev->srbm_mutex); 470 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 471 472 dev_info(adev->dev, "The gfx pipe reset: %s\n", 473 r == 0 ? "successfully" : "failed"); 474 /* Sometimes the ME start pc counter can't cache correctly, so the 475 * PC check only as a reference and pipe reset result rely on the 476 * later ring test. 477 */ 478 return 0; 479 } 480 481 /* 482 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 483 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 484 * asserted; only then clear the pipe reset bit. 485 * Caller must hold adev->srbm_mutex. 486 */ 487 static void mes_v12_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 488 u32 pipe) 489 { 490 unsigned int q; 491 492 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 493 soc24_grbm_select(adev, me, pipe, q, 0); 494 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 495 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 496 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 497 } 498 } 499 500 static int mes_v12_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 501 u32 me, u32 pipe, u32 queue) 502 { 503 uint32_t reset_val, clean_val; 504 int r = 0; 505 506 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 507 mutex_lock(&adev->srbm_mutex); 508 soc24_grbm_select(adev, me, pipe, queue, 0); 509 if (adev->gfx.rs64_enable) { 510 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 511 clean_val = reset_val; 512 513 switch (pipe) { 514 case 0: 515 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 516 MEC_PIPE0_RESET, 1); 517 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 518 MEC_PIPE0_RESET, 0); 519 break; 520 case 1: 521 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 522 MEC_PIPE1_RESET, 1); 523 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 524 MEC_PIPE1_RESET, 0); 525 break; 526 case 2: 527 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 528 MEC_PIPE2_RESET, 1); 529 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 530 MEC_PIPE2_RESET, 0); 531 break; 532 case 3: 533 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 534 MEC_PIPE3_RESET, 1); 535 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 536 MEC_PIPE3_RESET, 0); 537 break; 538 default: 539 break; 540 } 541 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 542 mes_v12_0_clear_hqds_on_mec_pipe(adev, me, pipe); 543 soc24_grbm_select(adev, me, pipe, queue, 0); 544 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 545 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 546 RS64_FW_UC_START_ADDR_LO; 547 } else { 548 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 549 clean_val = reset_val; 550 551 switch (pipe) { 552 case 0: 553 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 554 MEC_ME1_PIPE0_RESET, 1); 555 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 556 MEC_ME1_PIPE0_RESET, 0); 557 break; 558 case 1: 559 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 560 MEC_ME1_PIPE1_RESET, 1); 561 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 562 MEC_ME1_PIPE1_RESET, 0); 563 break; 564 default: 565 break; 566 } 567 568 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 569 mes_v12_0_clear_hqds_on_mec_pipe(adev, me, pipe); 570 soc24_grbm_select(adev, me, pipe, queue, 0); 571 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 572 } 573 574 soc24_grbm_select(adev, 0, 0, 0, 0); 575 mutex_unlock(&adev->srbm_mutex); 576 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 577 578 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 579 me, pipe, queue, r == 0 ? "successfully" : "failed"); 580 return 0; 581 } 582 583 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 584 uint32_t me_id, uint32_t pipe_id, 585 uint32_t queue_id, uint32_t vmid) 586 { 587 struct amdgpu_device *adev = mes->adev; 588 uint32_t value, reg; 589 int i, r = 0; 590 591 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 592 593 if (queue_type == AMDGPU_RING_TYPE_GFX) { 594 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 595 me_id, pipe_id, queue_id, vmid); 596 597 mutex_lock(&adev->gfx.reset_sem_mutex); 598 gfx_v12_0_request_gfx_index_mutex(adev, true); 599 /* all se allow writes */ 600 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 601 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 602 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 603 if (pipe_id == 0) 604 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 605 else 606 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 607 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 608 gfx_v12_0_request_gfx_index_mutex(adev, false); 609 mutex_unlock(&adev->gfx.reset_sem_mutex); 610 611 mutex_lock(&adev->srbm_mutex); 612 soc24_grbm_select(adev, me_id, pipe_id, queue_id, 0); 613 /* wait till dequeue take effects */ 614 for (i = 0; i < adev->usec_timeout; i++) { 615 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 616 break; 617 udelay(1); 618 } 619 if (i >= adev->usec_timeout) { 620 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 621 r = -ETIMEDOUT; 622 } 623 624 soc24_grbm_select(adev, 0, 0, 0, 0); 625 mutex_unlock(&adev->srbm_mutex); 626 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 627 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 628 me_id, pipe_id, queue_id); 629 mutex_lock(&adev->srbm_mutex); 630 soc24_grbm_select(adev, me_id, pipe_id, queue_id, 0); 631 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 632 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 633 634 /* wait till dequeue take effects */ 635 for (i = 0; i < adev->usec_timeout; i++) { 636 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 637 break; 638 udelay(1); 639 } 640 if (i >= adev->usec_timeout) { 641 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 642 r = -ETIMEDOUT; 643 } 644 soc24_grbm_select(adev, 0, 0, 0, 0); 645 mutex_unlock(&adev->srbm_mutex); 646 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 647 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 648 me_id, pipe_id, queue_id); 649 switch (me_id) { 650 case 1: 651 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 652 break; 653 case 0: 654 default: 655 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 656 break; 657 } 658 659 value = 1 << queue_id; 660 WREG32(reg, value); 661 /* wait for queue reset done */ 662 for (i = 0; i < adev->usec_timeout; i++) { 663 if (!(RREG32(reg) & value)) 664 break; 665 udelay(1); 666 } 667 if (i >= adev->usec_timeout) { 668 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 669 r = -ETIMEDOUT; 670 } 671 } 672 673 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 674 return r; 675 } 676 677 static int mes_v12_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 678 uint32_t me_id, uint32_t pipe_id, 679 uint32_t queue_id, uint32_t vmid) 680 { 681 struct amdgpu_device *adev = mes->adev; 682 683 if (queue_type == AMDGPU_RING_TYPE_GFX) 684 return mes_v12_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 685 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 686 return mes_v12_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 687 else 688 return -EOPNOTSUPP; 689 } 690 691 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 692 struct mes_map_legacy_queue_input *input) 693 { 694 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 695 int pipe; 696 697 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 698 699 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 700 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 701 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 702 703 mes_add_queue_pkt.pipe_id = input->pipe_id; 704 mes_add_queue_pkt.queue_id = input->queue_id; 705 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 706 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 707 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 708 mes_add_queue_pkt.queue_type = 709 convert_to_mes_queue_type(input->queue_type); 710 mes_add_queue_pkt.map_legacy_kq = 1; 711 712 if (mes->adev->enable_uni_mes) { 713 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */ 714 if (input->queue_type == AMDGPU_RING_TYPE_MES) 715 pipe = AMDGPU_MES_KIQ_PIPE; 716 else 717 pipe = AMDGPU_MES_SCHED_PIPE; 718 } else { 719 pipe = AMDGPU_MES_SCHED_PIPE; 720 } 721 722 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 723 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 724 offsetof(union MESAPI__ADD_QUEUE, api_status)); 725 } 726 727 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 728 struct mes_unmap_legacy_queue_input *input) 729 { 730 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 731 int pipe; 732 733 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 734 735 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 736 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 737 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 738 739 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 740 mes_remove_queue_pkt.gang_context_addr = 0; 741 742 mes_remove_queue_pkt.pipe_id = input->pipe_id; 743 mes_remove_queue_pkt.queue_id = input->queue_id; 744 745 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 746 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 747 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 748 mes_remove_queue_pkt.tf_data = 749 lower_32_bits(input->trail_fence_data); 750 } else { 751 mes_remove_queue_pkt.unmap_legacy_queue = 1; 752 mes_remove_queue_pkt.queue_type = 753 convert_to_mes_queue_type(input->queue_type); 754 /* 755 * A reset-time unmap: the queue was already reset via MMIO while 756 * gangs are suspended and it is on the MES hung/fail list. Tell 757 * MES to just drop its internal state for it. Without this flag 758 * MES asks CP to unmap the already-reset (still wedged) queue 759 * again, which times out and forces a GPU reset. 760 */ 761 if (input->action == RESET_QUEUES && 762 (mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x5a) 763 mes_remove_queue_pkt.remove_queue_after_reset = 1; 764 765 } 766 767 if (mes->adev->enable_uni_mes) { 768 /* Keep scheduler queue on KIQ pipe; unmap all other kernel queues on sched pipe. */ 769 if (input->queue_type == AMDGPU_RING_TYPE_MES) 770 pipe = AMDGPU_MES_KIQ_PIPE; 771 else 772 pipe = AMDGPU_MES_SCHED_PIPE; 773 } else { 774 pipe = AMDGPU_MES_SCHED_PIPE; 775 } 776 777 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 778 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 779 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 780 } 781 782 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 783 struct mes_suspend_gang_input *input) 784 { 785 union MESAPI__SUSPEND mes_suspend_gang_pkt; 786 787 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 788 789 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 790 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 791 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 792 793 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 794 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 795 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 796 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 797 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 798 799 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 800 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 801 offsetof(union MESAPI__SUSPEND, api_status)); 802 } 803 804 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 805 struct mes_resume_gang_input *input) 806 { 807 union MESAPI__RESUME mes_resume_gang_pkt; 808 809 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 810 811 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 812 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 813 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 814 815 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 816 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 817 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 818 819 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 820 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 821 offsetof(union MESAPI__RESUME, api_status)); 822 } 823 824 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 825 { 826 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 827 828 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 829 830 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 831 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 832 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 833 834 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 835 &mes_status_pkt, sizeof(mes_status_pkt), 836 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 837 } 838 839 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 840 struct mes_misc_op_input *input) 841 { 842 union MESAPI__MISC misc_pkt; 843 int pipe; 844 845 if (mes->adev->enable_uni_mes) 846 pipe = AMDGPU_MES_KIQ_PIPE; 847 else 848 pipe = AMDGPU_MES_SCHED_PIPE; 849 850 memset(&misc_pkt, 0, sizeof(misc_pkt)); 851 852 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 853 misc_pkt.header.opcode = MES_SCH_API_MISC; 854 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 855 856 switch (input->op) { 857 case MES_MISC_OP_READ_REG: 858 misc_pkt.opcode = MESAPI_MISC__READ_REG; 859 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 860 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 861 break; 862 case MES_MISC_OP_WRITE_REG: 863 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 864 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 865 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 866 break; 867 case MES_MISC_OP_WRM_REG_WAIT: 868 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 869 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 870 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 871 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 872 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 873 misc_pkt.wait_reg_mem.reg_offset2 = 0; 874 break; 875 case MES_MISC_OP_WRM_REG_WR_WAIT: 876 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 877 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 878 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 879 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 880 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 881 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 882 break; 883 case MES_MISC_OP_SET_SHADER_DEBUGGER: 884 pipe = AMDGPU_MES_SCHED_PIPE; 885 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 886 misc_pkt.set_shader_debugger.process_context_addr = 887 input->set_shader_debugger.process_context_addr; 888 misc_pkt.set_shader_debugger.flags.u32all = 889 input->set_shader_debugger.flags.u32all; 890 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 891 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 892 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 893 input->set_shader_debugger.tcp_watch_cntl, 894 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 895 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 896 break; 897 case MES_MISC_OP_CHANGE_CONFIG: 898 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 899 misc_pkt.change_config.opcode = 900 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 901 misc_pkt.change_config.option.bits.limit_single_process = 902 input->change_config.option.limit_single_process; 903 break; 904 905 default: 906 DRM_ERROR("unsupported misc op (%d)\n", input->op); 907 return -EINVAL; 908 } 909 910 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 911 &misc_pkt, sizeof(misc_pkt), 912 offsetof(union MESAPI__MISC, api_status)); 913 } 914 915 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 916 { 917 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 918 919 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 920 921 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 922 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 923 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 924 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa; 925 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr = 926 mes->resource_1_gpu_addr[pipe]; 927 928 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 929 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 930 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 931 } 932 933 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 934 { 935 int i; 936 struct amdgpu_device *adev = mes->adev; 937 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 938 uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ? 939 (mes->sched_version & AMDGPU_MES_VERSION_MASK) : 940 (mes->kiq_version & AMDGPU_MES_VERSION_MASK); 941 942 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 943 944 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 945 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 946 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 947 948 if (pipe == AMDGPU_MES_SCHED_PIPE) { 949 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 950 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 951 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 952 mes_set_hw_res_pkt.paging_vmid = 0; 953 954 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 955 mes_set_hw_res_pkt.compute_hqd_mask[i] = 956 mes->compute_hqd_mask[i]; 957 958 for (i = 0; i < MAX_GFX_PIPES; i++) 959 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 960 mes->gfx_hqd_mask[i]; 961 962 for (i = 0; i < MAX_SDMA_PIPES; i++) 963 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 964 mes->sdma_hqd_mask[i]; 965 966 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 967 mes_set_hw_res_pkt.aggregated_doorbells[i] = 968 mes->aggregated_doorbells[i]; 969 } 970 971 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 972 mes->sch_ctx_gpu_addr[pipe]; 973 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 974 mes->query_status_fence_gpu_addr[pipe]; 975 976 for (i = 0; i < 5; i++) { 977 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 978 mes_set_hw_res_pkt.mmhub_base[i] = 979 adev->reg_offset[MMHUB_HWIP][0][i]; 980 mes_set_hw_res_pkt.osssys_base[i] = 981 adev->reg_offset[OSSSYS_HWIP][0][i]; 982 } 983 984 mes_set_hw_res_pkt.disable_reset = 1; 985 mes_set_hw_res_pkt.disable_mes_log = 1; 986 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 987 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 988 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 989 990 /* 991 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 992 * handling support, other queue will not use the oversubscribe timer. 993 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 994 */ 995 mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50; 996 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 997 998 if (amdgpu_mes_log_enable) { 999 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 1000 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + 1001 pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 1002 } 1003 1004 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 1005 mes_set_hw_res_pkt.limit_single_process = 1; 1006 1007 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 1008 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1009 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 1010 } 1011 1012 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 1013 { 1014 struct amdgpu_device *adev = mes->adev; 1015 uint32_t data; 1016 1017 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 1018 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 1019 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 1020 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 1021 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 1022 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 1023 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 1024 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 1025 1026 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 1027 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 1028 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 1029 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 1030 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 1031 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 1032 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 1033 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 1034 1035 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 1036 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 1037 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 1038 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 1039 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 1040 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 1041 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 1042 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 1043 1044 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 1045 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 1046 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 1047 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 1048 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 1049 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 1050 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 1051 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 1052 1053 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 1054 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 1055 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 1056 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 1057 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 1058 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 1059 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 1060 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 1061 1062 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 1063 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 1064 } 1065 1066 1067 static void mes_v12_0_enable_unmapped_doorbell_handling( 1068 struct amdgpu_mes *mes, bool enable) 1069 { 1070 struct amdgpu_device *adev = mes->adev; 1071 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 1072 1073 /* 1074 * The default PROC_LSB settng is 0xc which means doorbell 1075 * addr[16:12] gives the doorbell page number. For kfd, each 1076 * process will use 2 pages of doorbell, we need to change the 1077 * setting to 0xd 1078 */ 1079 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 1080 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 1081 1082 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 1083 1084 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 1085 } 1086 1087 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 1088 struct mes_reset_queue_input *input) 1089 { 1090 union MESAPI__RESET mes_reset_queue_pkt; 1091 int pipe; 1092 1093 if (input->use_mmio) { 1094 int r = mes_v12_0_reset_queue_mmio(mes, input->queue_type, 1095 input->me_id, input->pipe_id, 1096 input->queue_id, input->vmid); 1097 if (r) 1098 return mes_v12_0_reset_pipe_mmio(mes, input->queue_type, 1099 input->me_id, input->pipe_id, 1100 input->queue_id, input->vmid); 1101 return 0; 1102 } 1103 1104 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1105 1106 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1107 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1108 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1109 1110 mes_reset_queue_pkt.queue_type = 1111 convert_to_mes_queue_type(input->queue_type); 1112 1113 if (input->legacy_gfx) { 1114 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1115 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1116 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1117 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1118 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1119 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1120 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1121 } else { 1122 mes_reset_queue_pkt.reset_queue_only = 1; 1123 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1124 } 1125 1126 pipe = AMDGPU_MES_SCHED_PIPE; 1127 1128 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 1129 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1130 offsetof(union MESAPI__RESET, api_status)); 1131 } 1132 1133 static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1134 struct mes_detect_and_reset_queue_input *input) 1135 { 1136 union MESAPI__RESET mes_reset_queue_pkt; 1137 1138 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1139 1140 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1141 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1142 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1143 1144 mes_reset_queue_pkt.queue_type = 1145 convert_to_mes_queue_type(input->queue_type); 1146 mes_reset_queue_pkt.doorbell_offset_addr = 1147 mes->hung_queue_db_array_gpu_addr[0]; 1148 1149 if (input->detect_only) 1150 mes_reset_queue_pkt.hang_detect_only = 1; 1151 else 1152 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1153 1154 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 1155 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1156 offsetof(union MESAPI__RESET, api_status)); 1157 } 1158 1159 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 1160 { 1161 /* 1162 * MES doesn't support invalidate gc_hub on slave xcc individually 1163 * master xcc will invalidate all gc_hub for the partition 1164 */ 1165 if (AMDGPU_IS_GFXHUB(id)) 1166 return 0; 1167 else if (AMDGPU_IS_MMHUB0(id)) 1168 return 1; 1169 else 1170 return -EINVAL; 1171 1172 } 1173 1174 static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, 1175 struct mes_inv_tlbs_pasid_input *input) 1176 { 1177 union MESAPI__INV_TLBS mes_inv_tlbs; 1178 int ret; 1179 1180 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 1181 1182 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 1183 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 1184 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1185 1186 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 1187 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 1188 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 1189 1190 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 1191 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 1192 if (ret < 0) 1193 return -EINVAL; 1194 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 1195 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, 1196 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 1197 offsetof(union MESAPI__INV_TLBS, api_status)); 1198 1199 } 1200 1201 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 1202 .add_hw_queue = mes_v12_0_add_hw_queue, 1203 .remove_hw_queue = mes_v12_0_remove_hw_queue, 1204 .map_legacy_queue = mes_v12_0_map_legacy_queue, 1205 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 1206 .suspend_gang = mes_v12_0_suspend_gang, 1207 .resume_gang = mes_v12_0_resume_gang, 1208 .misc_op = mes_v12_0_misc_op, 1209 .reset_hw_queue = mes_v12_0_reset_hw_queue, 1210 .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, 1211 .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, 1212 }; 1213 1214 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1215 enum amdgpu_mes_pipe pipe) 1216 { 1217 int r; 1218 const struct mes_firmware_header_v1_0 *mes_hdr; 1219 const __le32 *fw_data; 1220 unsigned fw_size; 1221 1222 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1223 adev->mes.fw[pipe]->data; 1224 1225 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1226 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1227 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1228 1229 r = amdgpu_bo_create_reserved(adev, fw_size, 1230 PAGE_SIZE, 1231 AMDGPU_GEM_DOMAIN_VRAM, 1232 &adev->mes.ucode_fw_obj[pipe], 1233 &adev->mes.ucode_fw_gpu_addr[pipe], 1234 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1235 if (r) { 1236 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1237 return r; 1238 } 1239 1240 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1241 1242 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1243 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1244 1245 return 0; 1246 } 1247 1248 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1249 enum amdgpu_mes_pipe pipe) 1250 { 1251 int r; 1252 const struct mes_firmware_header_v1_0 *mes_hdr; 1253 const __le32 *fw_data; 1254 unsigned fw_size; 1255 1256 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1257 adev->mes.fw[pipe]->data; 1258 1259 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1260 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1261 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1262 1263 r = amdgpu_bo_create_reserved(adev, fw_size, 1264 64 * 1024, 1265 AMDGPU_GEM_DOMAIN_VRAM, 1266 &adev->mes.data_fw_obj[pipe], 1267 &adev->mes.data_fw_gpu_addr[pipe], 1268 (void **)&adev->mes.data_fw_ptr[pipe]); 1269 if (r) { 1270 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1271 return r; 1272 } 1273 1274 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1275 1276 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1277 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1278 1279 return 0; 1280 } 1281 1282 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 1283 enum amdgpu_mes_pipe pipe) 1284 { 1285 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1286 &adev->mes.data_fw_gpu_addr[pipe], 1287 (void **)&adev->mes.data_fw_ptr[pipe]); 1288 1289 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1290 &adev->mes.ucode_fw_gpu_addr[pipe], 1291 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1292 } 1293 1294 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 1295 { 1296 uint64_t ucode_addr; 1297 uint32_t pipe, data = 0; 1298 1299 if (enable) { 1300 mutex_lock(&adev->srbm_mutex); 1301 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1302 soc24_grbm_select(adev, 3, pipe, 0, 0); 1303 if (amdgpu_mes_log_enable) { 1304 u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1305 /* In case uni mes is not enabled, only program for pipe 0 */ 1306 if (adev->mes.event_log_size >= (pipe + 1) * log_size) { 1307 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1308 lower_32_bits(adev->mes.event_log_gpu_addr + 1309 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1310 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1311 upper_32_bits(adev->mes.event_log_gpu_addr + 1312 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1313 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1314 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1315 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1316 } 1317 } 1318 1319 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1320 if (pipe == 0) 1321 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1322 else 1323 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1324 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1325 1326 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1327 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1328 lower_32_bits(ucode_addr)); 1329 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1330 upper_32_bits(ucode_addr)); 1331 1332 /* unhalt MES and activate one pipe each loop */ 1333 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1334 if (pipe) 1335 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1336 dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data); 1337 1338 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1339 1340 } 1341 soc24_grbm_select(adev, 0, 0, 0, 0); 1342 mutex_unlock(&adev->srbm_mutex); 1343 1344 if (amdgpu_emu_mode) 1345 msleep(100); 1346 else if (adev->enable_uni_mes) 1347 udelay(500); 1348 else 1349 udelay(50); 1350 } else { 1351 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1352 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1353 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1354 data = REG_SET_FIELD(data, CP_MES_CNTL, 1355 MES_INVALIDATE_ICACHE, 1); 1356 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1357 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1358 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1359 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1360 } 1361 } 1362 1363 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 1364 { 1365 uint64_t ucode_addr; 1366 int pipe; 1367 1368 mes_v12_0_enable(adev, false); 1369 1370 mutex_lock(&adev->srbm_mutex); 1371 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1372 /* me=3, queue=0 */ 1373 soc24_grbm_select(adev, 3, pipe, 0, 0); 1374 1375 /* set ucode start address */ 1376 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1377 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1378 lower_32_bits(ucode_addr)); 1379 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1380 upper_32_bits(ucode_addr)); 1381 1382 soc24_grbm_select(adev, 0, 0, 0, 0); 1383 } 1384 mutex_unlock(&adev->srbm_mutex); 1385 } 1386 1387 /* This function is for backdoor MES firmware */ 1388 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 1389 enum amdgpu_mes_pipe pipe, bool prime_icache) 1390 { 1391 int r; 1392 uint32_t data; 1393 1394 mes_v12_0_enable(adev, false); 1395 1396 if (!adev->mes.fw[pipe]) 1397 return -EINVAL; 1398 1399 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 1400 if (r) 1401 return r; 1402 1403 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 1404 if (r) { 1405 mes_v12_0_free_ucode_buffers(adev, pipe); 1406 return r; 1407 } 1408 1409 mutex_lock(&adev->srbm_mutex); 1410 /* me=3, pipe=0, queue=0 */ 1411 soc24_grbm_select(adev, 3, pipe, 0, 0); 1412 1413 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1414 1415 /* set ucode fimrware address */ 1416 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1417 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1418 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1419 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1420 1421 /* set ucode instruction cache boundary to 2M-1 */ 1422 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1423 1424 /* set ucode data firmware address */ 1425 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1426 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1427 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1428 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1429 1430 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1431 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1432 1433 if (prime_icache) { 1434 /* invalidate ICACHE */ 1435 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1436 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1437 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1438 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1439 1440 /* prime the ICACHE. */ 1441 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1442 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1443 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1444 } 1445 1446 soc24_grbm_select(adev, 0, 0, 0, 0); 1447 mutex_unlock(&adev->srbm_mutex); 1448 1449 return 0; 1450 } 1451 1452 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 1453 enum amdgpu_mes_pipe pipe) 1454 { 1455 int r; 1456 u32 *eop; 1457 1458 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1459 AMDGPU_GEM_DOMAIN_GTT, 1460 &adev->mes.eop_gpu_obj[pipe], 1461 &adev->mes.eop_gpu_addr[pipe], 1462 (void **)&eop); 1463 if (r) { 1464 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1465 return r; 1466 } 1467 1468 memset(eop, 0, 1469 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1470 1471 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1472 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1473 1474 return 0; 1475 } 1476 1477 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 1478 { 1479 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1480 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1481 uint32_t tmp; 1482 1483 mqd->header = 0xC0310800; 1484 mqd->compute_pipelinestat_enable = 0x00000001; 1485 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1486 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1487 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1488 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1489 mqd->compute_misc_reserved = 0x00000007; 1490 1491 eop_base_addr = ring->eop_gpu_addr >> 8; 1492 1493 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1494 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1495 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1496 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1497 1498 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1499 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1500 mqd->cp_hqd_eop_control = tmp; 1501 1502 /* disable the queue if it's active */ 1503 ring->wptr = 0; 1504 mqd->cp_hqd_pq_rptr = 0; 1505 mqd->cp_hqd_pq_wptr_lo = 0; 1506 mqd->cp_hqd_pq_wptr_hi = 0; 1507 1508 /* set the pointer to the MQD */ 1509 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1510 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1511 1512 /* set MQD vmid to 0 */ 1513 tmp = regCP_MQD_CONTROL_DEFAULT; 1514 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1515 mqd->cp_mqd_control = tmp; 1516 1517 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1518 hqd_gpu_addr = ring->gpu_addr >> 8; 1519 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1520 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1521 1522 /* set the wb address whether it's enabled or not */ 1523 wb_gpu_addr = ring->rptr_gpu_addr; 1524 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1525 mqd->cp_hqd_pq_rptr_report_addr_hi = 1526 upper_32_bits(wb_gpu_addr) & 0xffff; 1527 1528 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1529 wb_gpu_addr = ring->wptr_gpu_addr; 1530 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1531 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1532 1533 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1534 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1536 (order_base_2(ring->ring_size / 4) - 1)); 1537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1538 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1544 mqd->cp_hqd_pq_control = tmp; 1545 1546 /* enable doorbell */ 1547 tmp = 0; 1548 if (ring->use_doorbell) { 1549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1550 DOORBELL_OFFSET, ring->doorbell_index); 1551 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1552 DOORBELL_EN, 1); 1553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1554 DOORBELL_SOURCE, 0); 1555 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1556 DOORBELL_HIT, 0); 1557 } else { 1558 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1559 DOORBELL_EN, 0); 1560 } 1561 mqd->cp_hqd_pq_doorbell_control = tmp; 1562 1563 mqd->cp_hqd_vmid = 0; 1564 /* activate the queue */ 1565 mqd->cp_hqd_active = 1; 1566 1567 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1568 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1569 PRELOAD_SIZE, 0x55); 1570 mqd->cp_hqd_persistent_state = tmp; 1571 1572 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1573 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1574 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1575 1576 /* 1577 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1578 * doorbell handling. This is a reserved CP internal register can 1579 * not be accesss by others 1580 */ 1581 mqd->reserved_184 = BIT(15); 1582 1583 return 0; 1584 } 1585 1586 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1587 { 1588 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1589 struct amdgpu_device *adev = ring->adev; 1590 uint32_t data = 0; 1591 1592 mutex_lock(&adev->srbm_mutex); 1593 soc24_grbm_select(adev, 3, ring->pipe, 0, 0); 1594 1595 /* set CP_HQD_VMID.VMID = 0. */ 1596 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1597 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1598 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1599 1600 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1601 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1602 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1603 DOORBELL_EN, 0); 1604 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1605 1606 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1607 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1608 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1609 1610 /* set CP_MQD_CONTROL.VMID=0 */ 1611 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1612 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1613 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1614 1615 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1616 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1617 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1618 1619 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1620 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1621 mqd->cp_hqd_pq_rptr_report_addr_lo); 1622 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1623 mqd->cp_hqd_pq_rptr_report_addr_hi); 1624 1625 /* set CP_HQD_PQ_CONTROL */ 1626 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1627 1628 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1629 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1630 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1631 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1632 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1633 1634 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1635 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1636 mqd->cp_hqd_pq_doorbell_control); 1637 1638 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1639 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1640 1641 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1642 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1643 1644 soc24_grbm_select(adev, 0, 0, 0, 0); 1645 mutex_unlock(&adev->srbm_mutex); 1646 } 1647 1648 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1649 { 1650 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1651 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1652 int r; 1653 1654 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1655 return -EINVAL; 1656 1657 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1658 if (r) { 1659 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1660 return r; 1661 } 1662 1663 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1664 1665 r = amdgpu_ring_test_ring(kiq_ring); 1666 if (r) { 1667 DRM_ERROR("kfq enable failed\n"); 1668 kiq_ring->sched.ready = false; 1669 } 1670 return r; 1671 } 1672 1673 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1674 enum amdgpu_mes_pipe pipe) 1675 { 1676 struct amdgpu_ring *ring; 1677 int r; 1678 1679 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1680 ring = &adev->gfx.kiq[0].ring; 1681 else 1682 ring = &adev->mes.ring[pipe]; 1683 1684 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1685 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1686 *(ring->wptr_cpu_addr) = 0; 1687 *(ring->rptr_cpu_addr) = 0; 1688 amdgpu_ring_clear_ring(ring); 1689 } 1690 1691 r = mes_v12_0_mqd_init(ring); 1692 if (r) 1693 return r; 1694 1695 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1696 if (adev->enable_uni_mes) 1697 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 1698 else 1699 r = mes_v12_0_kiq_enable_queue(adev); 1700 if (r) 1701 return r; 1702 } else { 1703 mes_v12_0_queue_init_register(ring); 1704 } 1705 1706 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) || 1707 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) { 1708 /* get MES scheduler/KIQ versions */ 1709 mutex_lock(&adev->srbm_mutex); 1710 soc24_grbm_select(adev, 3, pipe, 0, 0); 1711 1712 if (pipe == AMDGPU_MES_SCHED_PIPE) 1713 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1714 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1715 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1716 1717 soc24_grbm_select(adev, 0, 0, 0, 0); 1718 mutex_unlock(&adev->srbm_mutex); 1719 } 1720 1721 return 0; 1722 } 1723 1724 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1725 { 1726 struct amdgpu_ring *ring; 1727 1728 ring = &adev->mes.ring[pipe]; 1729 1730 ring->funcs = &mes_v12_0_ring_funcs; 1731 1732 ring->me = 3; 1733 ring->pipe = pipe; 1734 ring->queue = 0; 1735 1736 ring->ring_obj = NULL; 1737 ring->use_doorbell = true; 1738 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1739 ring->no_scheduler = true; 1740 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1741 1742 if (pipe == AMDGPU_MES_SCHED_PIPE) 1743 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1744 else 1745 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1746 1747 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1748 AMDGPU_RING_PRIO_DEFAULT, NULL); 1749 } 1750 1751 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1752 { 1753 struct amdgpu_ring *ring; 1754 1755 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1756 1757 ring = &adev->gfx.kiq[0].ring; 1758 1759 ring->me = 3; 1760 ring->pipe = 1; 1761 ring->queue = 0; 1762 1763 ring->adev = NULL; 1764 ring->ring_obj = NULL; 1765 ring->use_doorbell = true; 1766 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1767 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1768 ring->no_scheduler = true; 1769 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1770 ring->me, ring->pipe, ring->queue); 1771 1772 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1773 AMDGPU_RING_PRIO_DEFAULT, NULL); 1774 } 1775 1776 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1777 enum amdgpu_mes_pipe pipe) 1778 { 1779 int r, mqd_size = sizeof(struct v12_compute_mqd); 1780 struct amdgpu_ring *ring; 1781 1782 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1783 ring = &adev->gfx.kiq[0].ring; 1784 else 1785 ring = &adev->mes.ring[pipe]; 1786 1787 if (ring->mqd_obj) 1788 return 0; 1789 1790 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1791 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1792 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1793 if (r) { 1794 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1795 return r; 1796 } 1797 1798 memset(ring->mqd_ptr, 0, mqd_size); 1799 1800 /* prepare MQD backup */ 1801 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1802 if (!adev->mes.mqd_backup[pipe]) 1803 dev_warn(adev->dev, 1804 "no memory to create MQD backup for ring %s\n", 1805 ring->name); 1806 1807 return 0; 1808 } 1809 1810 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1811 { 1812 struct amdgpu_device *adev = ip_block->adev; 1813 int pipe, r; 1814 1815 adev->mes.funcs = &mes_v12_0_funcs; 1816 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1817 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1818 adev->mes.enable_legacy_queue_map = true; 1819 1820 adev->mes.event_log_size = adev->enable_uni_mes ? 1821 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : 1822 (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 1823 r = amdgpu_mes_init(adev); 1824 if (r) 1825 return r; 1826 1827 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1828 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1829 if (r) 1830 return r; 1831 1832 r = mes_v12_0_mqd_sw_init(adev, pipe); 1833 if (r) 1834 return r; 1835 1836 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) { 1837 r = mes_v12_0_kiq_ring_init(adev); 1838 } 1839 else { 1840 r = mes_v12_0_ring_init(adev, pipe); 1841 if (r) 1842 return r; 1843 r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1844 AMDGPU_GEM_DOMAIN_VRAM, 1845 &adev->mes.resource_1[pipe], 1846 &adev->mes.resource_1_gpu_addr[pipe], 1847 &adev->mes.resource_1_addr[pipe]); 1848 if (r) { 1849 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe); 1850 return r; 1851 } 1852 } 1853 } 1854 1855 return 0; 1856 } 1857 1858 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1859 { 1860 struct amdgpu_device *adev = ip_block->adev; 1861 int pipe; 1862 1863 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1864 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], 1865 &adev->mes.resource_1_gpu_addr[pipe], 1866 &adev->mes.resource_1_addr[pipe]); 1867 1868 kfree(adev->mes.mqd_backup[pipe]); 1869 1870 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1871 &adev->mes.eop_gpu_addr[pipe], 1872 NULL); 1873 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1874 1875 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1876 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1877 &adev->mes.ring[pipe].mqd_gpu_addr, 1878 &adev->mes.ring[pipe].mqd_ptr); 1879 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1880 } 1881 } 1882 1883 if (!adev->enable_uni_mes) { 1884 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1885 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1886 &adev->gfx.kiq[0].ring.mqd_ptr); 1887 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1888 } 1889 1890 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1891 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1892 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1893 } 1894 1895 amdgpu_mes_fini(adev); 1896 return 0; 1897 } 1898 1899 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1900 { 1901 uint32_t data; 1902 int i; 1903 1904 mutex_lock(&adev->srbm_mutex); 1905 soc24_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1906 1907 /* disable the queue if it's active */ 1908 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1909 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1910 for (i = 0; i < adev->usec_timeout; i++) { 1911 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1912 break; 1913 udelay(1); 1914 } 1915 } 1916 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1917 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1918 DOORBELL_EN, 0); 1919 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1920 DOORBELL_HIT, 1); 1921 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1922 1923 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1924 1925 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1926 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1927 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1928 1929 soc24_grbm_select(adev, 0, 0, 0, 0); 1930 mutex_unlock(&adev->srbm_mutex); 1931 1932 adev->mes.ring[0].sched.ready = false; 1933 } 1934 1935 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1936 { 1937 uint32_t tmp; 1938 struct amdgpu_device *adev = ring->adev; 1939 1940 /* tell RLC which is KIQ queue */ 1941 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1942 tmp &= 0xffffff00; 1943 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1944 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1945 } 1946 1947 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1948 { 1949 int r = 0; 1950 struct amdgpu_ip_block *ip_block; 1951 1952 if (adev->enable_uni_mes) 1953 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1954 else 1955 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1956 1957 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1958 1959 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1960 if (r) { 1961 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1962 return r; 1963 } 1964 1965 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1966 if (r) { 1967 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1968 return r; 1969 } 1970 1971 mes_v12_0_set_ucode_start_addr(adev); 1972 1973 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1974 mes_v12_0_set_ucode_start_addr(adev); 1975 1976 mes_v12_0_enable(adev, true); 1977 1978 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1979 if (unlikely(!ip_block)) { 1980 dev_err(adev->dev, "Failed to get MES handle\n"); 1981 return -EINVAL; 1982 } 1983 1984 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1985 if (r) 1986 goto failure; 1987 1988 if (adev->enable_uni_mes) { 1989 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1990 if (r) 1991 goto failure; 1992 1993 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1994 } 1995 1996 if (adev->mes.enable_legacy_queue_map) { 1997 r = mes_v12_0_hw_init(ip_block); 1998 if (r) 1999 goto failure; 2000 } 2001 2002 return r; 2003 2004 failure: 2005 mes_v12_0_hw_fini(ip_block); 2006 return r; 2007 } 2008 2009 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 2010 { 2011 if (adev->mes.ring[0].sched.ready) { 2012 if (adev->enable_uni_mes) 2013 amdgpu_mes_unmap_legacy_queue(adev, 2014 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 2015 RESET_QUEUES, 0, 0, 0); 2016 else 2017 mes_v12_0_kiq_dequeue_sched(adev); 2018 2019 adev->mes.ring[0].sched.ready = false; 2020 } 2021 2022 mes_v12_0_enable(adev, false); 2023 2024 return 0; 2025 } 2026 2027 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 2028 { 2029 int r; 2030 struct amdgpu_device *adev = ip_block->adev; 2031 2032 if (adev->mes.ring[0].sched.ready) 2033 goto out; 2034 2035 if (!adev->enable_mes_kiq) { 2036 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2037 r = mes_v12_0_load_microcode(adev, 2038 AMDGPU_MES_SCHED_PIPE, true); 2039 if (r) { 2040 DRM_ERROR("failed to MES fw, r=%d\n", r); 2041 return r; 2042 } 2043 2044 mes_v12_0_set_ucode_start_addr(adev); 2045 2046 } else if (adev->firmware.load_type == 2047 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2048 2049 mes_v12_0_set_ucode_start_addr(adev); 2050 } 2051 2052 mes_v12_0_enable(adev, true); 2053 } 2054 2055 /* Enable the MES to handle doorbell ring on unmapped queue */ 2056 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 2057 2058 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 2059 if (r) 2060 goto failure; 2061 2062 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 2063 if (r) 2064 goto failure; 2065 2066 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b) 2067 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 2068 2069 mes_v12_0_init_aggregated_doorbell(&adev->mes); 2070 2071 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 2072 if (r) { 2073 DRM_ERROR("MES is busy\n"); 2074 goto failure; 2075 } 2076 2077 r = amdgpu_mes_update_enforce_isolation(adev); 2078 if (r) 2079 goto failure; 2080 2081 amdgpu_mes_validate_fw_version(adev); 2082 out: 2083 /* 2084 * Disable KIQ ring usage from the driver once MES is enabled. 2085 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 2086 * with MES enabled. 2087 */ 2088 adev->gfx.kiq[0].ring.sched.ready = false; 2089 adev->mes.ring[0].sched.ready = true; 2090 2091 return 0; 2092 2093 failure: 2094 mes_v12_0_hw_fini(ip_block); 2095 return r; 2096 } 2097 2098 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 2099 { 2100 return 0; 2101 } 2102 2103 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) 2104 { 2105 return mes_v12_0_hw_fini(ip_block); 2106 } 2107 2108 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) 2109 { 2110 return mes_v12_0_hw_init(ip_block); 2111 } 2112 2113 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) 2114 { 2115 struct amdgpu_device *adev = ip_block->adev; 2116 int pipe, r; 2117 2118 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 2119 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 2120 2121 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 2122 r = amdgpu_mes_init_microcode(adev, pipe); 2123 if (r) 2124 return r; 2125 } 2126 2127 return 0; 2128 } 2129 2130 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 2131 .name = "mes_v12_0", 2132 .early_init = mes_v12_0_early_init, 2133 .late_init = NULL, 2134 .sw_init = mes_v12_0_sw_init, 2135 .sw_fini = mes_v12_0_sw_fini, 2136 .hw_init = mes_v12_0_hw_init, 2137 .hw_fini = mes_v12_0_hw_fini, 2138 .suspend = mes_v12_0_suspend, 2139 .resume = mes_v12_0_resume, 2140 }; 2141 2142 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 2143 .type = AMD_IP_BLOCK_TYPE_MES, 2144 .major = 12, 2145 .minor = 0, 2146 .rev = 0, 2147 .funcs = &mes_v12_0_ip_funcs, 2148 }; 2149