1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_12_0_0_offset.h" 30 #include "gc/gc_12_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 41 42 static int mes_v12_0_hw_init(void *handle); 43 static int mes_v12_0_hw_fini(void *handle); 44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v12_0_ring_get_rptr, 84 .get_wptr = mes_v12_0_ring_get_wptr, 85 .set_wptr = mes_v12_0_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static const char *mes_v12_0_opcodes[] = { 90 "SET_HW_RSRC", 91 "SET_SCHEDULING_CONFIG", 92 "ADD_QUEUE", 93 "REMOVE_QUEUE", 94 "PERFORM_YIELD", 95 "SET_GANG_PRIORITY_LEVEL", 96 "SUSPEND", 97 "RESUME", 98 "RESET", 99 "SET_LOG_BUFFER", 100 "CHANGE_GANG_PRORITY", 101 "QUERY_SCHEDULER_STATUS", 102 "SET_DEBUG_VMID", 103 "MISC", 104 "UPDATE_ROOT_PAGE_TABLE", 105 "AMD_LOG", 106 "SET_SE_MODE", 107 "SET_GANG_SUBMIT", 108 "SET_HW_RSRC_1", 109 }; 110 111 static const char *mes_v12_0_misc_opcodes[] = { 112 "WRITE_REG", 113 "INV_GART", 114 "QUERY_STATUS", 115 "READ_REG", 116 "WAIT_REG_MEM", 117 "SET_SHADER_DEBUGGER", 118 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 119 "NOTIFY_TO_UNMAP_PROCESSES", 120 }; 121 122 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 123 { 124 const char *op_str = NULL; 125 126 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 127 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 128 129 return op_str; 130 } 131 132 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 133 { 134 const char *op_str = NULL; 135 136 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 137 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 138 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 139 140 return op_str; 141 } 142 143 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 144 void *pkt, int size, 145 int api_status_off) 146 { 147 int ndw = size / 4; 148 signed long r; 149 union MESAPI__MISC *x_pkt = pkt; 150 struct MES_API_STATUS *api_status; 151 struct amdgpu_device *adev = mes->adev; 152 struct amdgpu_ring *ring = &mes->ring; 153 unsigned long flags; 154 const char *op_str, *misc_op_str; 155 signed long timeout = 3000000; /* 3000 ms */ 156 u32 fence_offset; 157 u64 fence_gpu_addr; 158 u64 *fence_ptr; 159 int ret; 160 161 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 162 return -EINVAL; 163 164 if (amdgpu_emu_mode) { 165 timeout *= 100; 166 } else if (amdgpu_sriov_vf(adev)) { 167 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 168 timeout = 15 * 600 * 1000; 169 } 170 BUG_ON(size % 4 != 0); 171 172 ret = amdgpu_device_wb_get(adev, &fence_offset); 173 if (ret) 174 return ret; 175 fence_gpu_addr = 176 adev->wb.gpu_addr + (fence_offset * 4); 177 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 178 *fence_ptr = 0; 179 180 spin_lock_irqsave(&mes->ring_lock, flags); 181 if (amdgpu_ring_alloc(ring, ndw)) { 182 spin_unlock_irqrestore(&mes->ring_lock, flags); 183 amdgpu_device_wb_free(adev, fence_offset); 184 return -ENOMEM; 185 } 186 187 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 188 api_status->api_completion_fence_addr = fence_gpu_addr; 189 api_status->api_completion_fence_value = 1; 190 191 amdgpu_ring_write_multiple(ring, pkt, ndw); 192 amdgpu_ring_commit(ring); 193 spin_unlock_irqrestore(&mes->ring_lock, flags); 194 195 op_str = mes_v12_0_get_op_string(x_pkt); 196 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 197 198 if (misc_op_str) 199 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, misc_op_str); 200 else if (op_str) 201 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 202 else 203 dev_dbg(adev->dev, "MES msg=%d was emitted\n", x_pkt->header.opcode); 204 205 r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout); 206 amdgpu_device_wb_free(adev, fence_offset); 207 208 if (r < 1) { 209 if (misc_op_str) 210 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 211 op_str, misc_op_str); 212 else if (op_str) 213 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 214 op_str); 215 else 216 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 217 x_pkt->header.opcode); 218 219 while (halt_if_hws_hang) 220 schedule(); 221 222 return -ETIMEDOUT; 223 } 224 225 return 0; 226 } 227 228 static int convert_to_mes_queue_type(int queue_type) 229 { 230 if (queue_type == AMDGPU_RING_TYPE_GFX) 231 return MES_QUEUE_TYPE_GFX; 232 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 233 return MES_QUEUE_TYPE_COMPUTE; 234 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 235 return MES_QUEUE_TYPE_SDMA; 236 else 237 BUG(); 238 return -1; 239 } 240 241 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 242 struct mes_add_queue_input *input) 243 { 244 struct amdgpu_device *adev = mes->adev; 245 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 246 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 247 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 248 249 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 250 251 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 252 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 253 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 254 255 mes_add_queue_pkt.process_id = input->process_id; 256 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 257 mes_add_queue_pkt.process_va_start = input->process_va_start; 258 mes_add_queue_pkt.process_va_end = input->process_va_end; 259 mes_add_queue_pkt.process_quantum = input->process_quantum; 260 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 261 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 262 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 263 mes_add_queue_pkt.inprocess_gang_priority = 264 input->inprocess_gang_priority; 265 mes_add_queue_pkt.gang_global_priority_level = 266 input->gang_global_priority_level; 267 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 268 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 269 270 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 271 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 272 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 273 else 274 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 275 276 mes_add_queue_pkt.queue_type = 277 convert_to_mes_queue_type(input->queue_type); 278 mes_add_queue_pkt.paging = input->paging; 279 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 280 mes_add_queue_pkt.gws_base = input->gws_base; 281 mes_add_queue_pkt.gws_size = input->gws_size; 282 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 283 mes_add_queue_pkt.tma_addr = input->tma_addr; 284 mes_add_queue_pkt.trap_en = input->trap_en; 285 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 286 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 287 288 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 289 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 290 mes_add_queue_pkt.gds_size = input->queue_size; 291 292 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 293 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 294 mes_add_queue_pkt.gds_size = input->queue_size; 295 296 return mes_v12_0_submit_pkt_and_poll_completion(mes, 297 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 298 offsetof(union MESAPI__ADD_QUEUE, api_status)); 299 } 300 301 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 302 struct mes_remove_queue_input *input) 303 { 304 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 305 306 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 307 308 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 309 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 310 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 311 312 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 313 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 314 315 return mes_v12_0_submit_pkt_and_poll_completion(mes, 316 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 317 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 318 } 319 320 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 321 struct mes_map_legacy_queue_input *input) 322 { 323 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 324 325 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 326 327 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 328 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 329 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 330 331 mes_add_queue_pkt.pipe_id = input->pipe_id; 332 mes_add_queue_pkt.queue_id = input->queue_id; 333 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 334 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 335 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 336 mes_add_queue_pkt.queue_type = 337 convert_to_mes_queue_type(input->queue_type); 338 mes_add_queue_pkt.map_legacy_kq = 1; 339 340 return mes_v12_0_submit_pkt_and_poll_completion(mes, 341 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 342 offsetof(union MESAPI__ADD_QUEUE, api_status)); 343 } 344 345 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 346 struct mes_unmap_legacy_queue_input *input) 347 { 348 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 349 350 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 351 352 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 353 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 354 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 355 356 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 357 mes_remove_queue_pkt.gang_context_addr = 0; 358 359 mes_remove_queue_pkt.pipe_id = input->pipe_id; 360 mes_remove_queue_pkt.queue_id = input->queue_id; 361 362 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 363 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 364 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 365 mes_remove_queue_pkt.tf_data = 366 lower_32_bits(input->trail_fence_data); 367 } else { 368 mes_remove_queue_pkt.unmap_legacy_queue = 1; 369 mes_remove_queue_pkt.queue_type = 370 convert_to_mes_queue_type(input->queue_type); 371 } 372 373 return mes_v12_0_submit_pkt_and_poll_completion(mes, 374 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 375 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 376 } 377 378 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 379 struct mes_suspend_gang_input *input) 380 { 381 return 0; 382 } 383 384 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 385 struct mes_resume_gang_input *input) 386 { 387 return 0; 388 } 389 390 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes) 391 { 392 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 393 394 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 395 396 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 397 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 398 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 399 400 return mes_v12_0_submit_pkt_and_poll_completion(mes, 401 &mes_status_pkt, sizeof(mes_status_pkt), 402 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 403 } 404 405 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 406 struct mes_misc_op_input *input) 407 { 408 union MESAPI__MISC misc_pkt; 409 410 memset(&misc_pkt, 0, sizeof(misc_pkt)); 411 412 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 413 misc_pkt.header.opcode = MES_SCH_API_MISC; 414 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 415 416 switch (input->op) { 417 case MES_MISC_OP_READ_REG: 418 misc_pkt.opcode = MESAPI_MISC__READ_REG; 419 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 420 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 421 break; 422 case MES_MISC_OP_WRITE_REG: 423 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 424 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 425 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 426 break; 427 case MES_MISC_OP_WRM_REG_WAIT: 428 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 429 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 430 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 431 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 432 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 433 misc_pkt.wait_reg_mem.reg_offset2 = 0; 434 break; 435 case MES_MISC_OP_WRM_REG_WR_WAIT: 436 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 437 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 438 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 439 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 440 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 441 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 442 break; 443 case MES_MISC_OP_SET_SHADER_DEBUGGER: 444 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 445 misc_pkt.set_shader_debugger.process_context_addr = 446 input->set_shader_debugger.process_context_addr; 447 misc_pkt.set_shader_debugger.flags.u32all = 448 input->set_shader_debugger.flags.u32all; 449 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 450 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 451 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 452 input->set_shader_debugger.tcp_watch_cntl, 453 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 454 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 455 break; 456 default: 457 DRM_ERROR("unsupported misc op (%d) \n", input->op); 458 return -EINVAL; 459 } 460 461 return mes_v12_0_submit_pkt_and_poll_completion(mes, 462 &misc_pkt, sizeof(misc_pkt), 463 offsetof(union MESAPI__MISC, api_status)); 464 } 465 466 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes) 467 { 468 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 469 470 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 471 472 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 473 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 474 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 475 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 476 477 return mes_v12_0_submit_pkt_and_poll_completion(mes, 478 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 479 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 480 } 481 482 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) 483 { 484 int i; 485 struct amdgpu_device *adev = mes->adev; 486 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 487 488 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 489 490 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 491 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 492 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 493 494 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 495 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 496 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 497 mes_set_hw_res_pkt.paging_vmid = 0; 498 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 499 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 500 mes->query_status_fence_gpu_addr; 501 502 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 503 mes_set_hw_res_pkt.compute_hqd_mask[i] = 504 mes->compute_hqd_mask[i]; 505 506 for (i = 0; i < MAX_GFX_PIPES; i++) 507 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 508 509 for (i = 0; i < MAX_SDMA_PIPES; i++) 510 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 511 512 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 513 mes_set_hw_res_pkt.aggregated_doorbells[i] = 514 mes->aggregated_doorbells[i]; 515 516 for (i = 0; i < 5; i++) { 517 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 518 mes_set_hw_res_pkt.mmhub_base[i] = 519 adev->reg_offset[MMHUB_HWIP][0][i]; 520 mes_set_hw_res_pkt.osssys_base[i] = 521 adev->reg_offset[OSSSYS_HWIP][0][i]; 522 } 523 524 mes_set_hw_res_pkt.disable_reset = 1; 525 mes_set_hw_res_pkt.disable_mes_log = 1; 526 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 527 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 528 mes_set_hw_res_pkt.oversubscription_timer = 50; 529 530 mes_set_hw_res_pkt.enable_mes_event_int_logging = 0; 531 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 532 533 return mes_v12_0_submit_pkt_and_poll_completion(mes, 534 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 535 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 536 } 537 538 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 539 { 540 struct amdgpu_device *adev = mes->adev; 541 uint32_t data; 542 543 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 544 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 545 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 546 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 547 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 548 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 549 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 550 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 551 552 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 553 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 554 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 555 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 556 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 557 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 558 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 559 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 560 561 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 562 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 563 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 564 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 565 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 566 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 567 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 568 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 569 570 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 571 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 572 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 573 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 574 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 575 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 576 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 577 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 578 579 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 580 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 581 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 582 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 583 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 584 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 585 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 586 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 587 588 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 589 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 590 } 591 592 593 static void mes_v12_0_enable_unmapped_doorbell_handling( 594 struct amdgpu_mes *mes, bool enable) 595 { 596 struct amdgpu_device *adev = mes->adev; 597 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 598 599 /* 600 * The default PROC_LSB settng is 0xc which means doorbell 601 * addr[16:12] gives the doorbell page number. For kfd, each 602 * process will use 2 pages of doorbell, we need to change the 603 * setting to 0xd 604 */ 605 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 606 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 607 608 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 609 610 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 611 } 612 613 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 614 .add_hw_queue = mes_v12_0_add_hw_queue, 615 .remove_hw_queue = mes_v12_0_remove_hw_queue, 616 .map_legacy_queue = mes_v12_0_map_legacy_queue, 617 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 618 .suspend_gang = mes_v12_0_suspend_gang, 619 .resume_gang = mes_v12_0_resume_gang, 620 .misc_op = mes_v12_0_misc_op, 621 }; 622 623 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 624 enum admgpu_mes_pipe pipe) 625 { 626 int r; 627 const struct mes_firmware_header_v1_0 *mes_hdr; 628 const __le32 *fw_data; 629 unsigned fw_size; 630 631 mes_hdr = (const struct mes_firmware_header_v1_0 *) 632 adev->mes.fw[pipe]->data; 633 634 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 635 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 636 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 637 638 r = amdgpu_bo_create_reserved(adev, fw_size, 639 PAGE_SIZE, 640 AMDGPU_GEM_DOMAIN_VRAM, 641 &adev->mes.ucode_fw_obj[pipe], 642 &adev->mes.ucode_fw_gpu_addr[pipe], 643 (void **)&adev->mes.ucode_fw_ptr[pipe]); 644 if (r) { 645 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 646 return r; 647 } 648 649 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 650 651 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 652 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 653 654 return 0; 655 } 656 657 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 658 enum admgpu_mes_pipe pipe) 659 { 660 int r; 661 const struct mes_firmware_header_v1_0 *mes_hdr; 662 const __le32 *fw_data; 663 unsigned fw_size; 664 665 mes_hdr = (const struct mes_firmware_header_v1_0 *) 666 adev->mes.fw[pipe]->data; 667 668 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 669 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 670 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 671 672 r = amdgpu_bo_create_reserved(adev, fw_size, 673 64 * 1024, 674 AMDGPU_GEM_DOMAIN_VRAM, 675 &adev->mes.data_fw_obj[pipe], 676 &adev->mes.data_fw_gpu_addr[pipe], 677 (void **)&adev->mes.data_fw_ptr[pipe]); 678 if (r) { 679 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 680 return r; 681 } 682 683 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 684 685 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 686 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 687 688 return 0; 689 } 690 691 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 692 enum admgpu_mes_pipe pipe) 693 { 694 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 695 &adev->mes.data_fw_gpu_addr[pipe], 696 (void **)&adev->mes.data_fw_ptr[pipe]); 697 698 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 699 &adev->mes.ucode_fw_gpu_addr[pipe], 700 (void **)&adev->mes.ucode_fw_ptr[pipe]); 701 } 702 703 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 704 { 705 uint64_t ucode_addr; 706 uint32_t pipe, data = 0; 707 708 if (enable) { 709 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 710 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 711 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 712 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 713 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 714 715 mutex_lock(&adev->srbm_mutex); 716 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 717 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 718 pipe == AMDGPU_MES_KIQ_PIPE) 719 continue; 720 721 soc21_grbm_select(adev, 3, pipe, 0, 0); 722 723 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 724 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 725 lower_32_bits(ucode_addr)); 726 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 727 upper_32_bits(ucode_addr)); 728 } 729 soc21_grbm_select(adev, 0, 0, 0, 0); 730 mutex_unlock(&adev->srbm_mutex); 731 732 /* unhalt MES and activate pipe0 */ 733 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 734 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 735 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 736 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 737 738 if (amdgpu_emu_mode) 739 msleep(100); 740 else if (adev->enable_uni_mes) 741 udelay(500); 742 else 743 udelay(50); 744 } else { 745 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 746 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 747 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 748 data = REG_SET_FIELD(data, CP_MES_CNTL, 749 MES_INVALIDATE_ICACHE, 1); 750 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 751 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 752 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 753 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 754 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 755 } 756 } 757 758 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 759 { 760 uint64_t ucode_addr; 761 int pipe; 762 763 mes_v12_0_enable(adev, false); 764 765 mutex_lock(&adev->srbm_mutex); 766 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 767 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 768 pipe == AMDGPU_MES_KIQ_PIPE) 769 continue; 770 771 /* me=3, queue=0 */ 772 soc21_grbm_select(adev, 3, pipe, 0, 0); 773 774 /* set ucode start address */ 775 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 776 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 777 lower_32_bits(ucode_addr)); 778 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 779 upper_32_bits(ucode_addr)); 780 781 soc21_grbm_select(adev, 0, 0, 0, 0); 782 } 783 mutex_unlock(&adev->srbm_mutex); 784 } 785 786 /* This function is for backdoor MES firmware */ 787 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 788 enum admgpu_mes_pipe pipe, bool prime_icache) 789 { 790 int r; 791 uint32_t data; 792 793 mes_v12_0_enable(adev, false); 794 795 if (!adev->mes.fw[pipe]) 796 return -EINVAL; 797 798 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 799 if (r) 800 return r; 801 802 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 803 if (r) { 804 mes_v12_0_free_ucode_buffers(adev, pipe); 805 return r; 806 } 807 808 mutex_lock(&adev->srbm_mutex); 809 /* me=3, pipe=0, queue=0 */ 810 soc21_grbm_select(adev, 3, pipe, 0, 0); 811 812 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 813 814 /* set ucode fimrware address */ 815 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 816 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 817 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 818 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 819 820 /* set ucode instruction cache boundary to 2M-1 */ 821 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 822 823 /* set ucode data firmware address */ 824 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 825 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 826 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 827 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 828 829 /* Set data cache boundary CP_MES_MDBOUND_LO */ 830 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 831 832 if (prime_icache) { 833 /* invalidate ICACHE */ 834 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 835 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 836 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 837 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 838 839 /* prime the ICACHE. */ 840 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 841 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 842 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 843 } 844 845 soc21_grbm_select(adev, 0, 0, 0, 0); 846 mutex_unlock(&adev->srbm_mutex); 847 848 return 0; 849 } 850 851 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 852 enum admgpu_mes_pipe pipe) 853 { 854 int r; 855 u32 *eop; 856 857 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 858 AMDGPU_GEM_DOMAIN_GTT, 859 &adev->mes.eop_gpu_obj[pipe], 860 &adev->mes.eop_gpu_addr[pipe], 861 (void **)&eop); 862 if (r) { 863 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 864 return r; 865 } 866 867 memset(eop, 0, 868 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 869 870 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 871 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 872 873 return 0; 874 } 875 876 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 877 { 878 struct v12_compute_mqd *mqd = ring->mqd_ptr; 879 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 880 uint32_t tmp; 881 882 mqd->header = 0xC0310800; 883 mqd->compute_pipelinestat_enable = 0x00000001; 884 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 885 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 886 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 887 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 888 mqd->compute_misc_reserved = 0x00000007; 889 890 eop_base_addr = ring->eop_gpu_addr >> 8; 891 892 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 893 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 894 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 895 (order_base_2(MES_EOP_SIZE / 4) - 1)); 896 897 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 898 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 899 mqd->cp_hqd_eop_control = tmp; 900 901 /* disable the queue if it's active */ 902 ring->wptr = 0; 903 mqd->cp_hqd_pq_rptr = 0; 904 mqd->cp_hqd_pq_wptr_lo = 0; 905 mqd->cp_hqd_pq_wptr_hi = 0; 906 907 /* set the pointer to the MQD */ 908 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 909 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 910 911 /* set MQD vmid to 0 */ 912 tmp = regCP_MQD_CONTROL_DEFAULT; 913 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 914 mqd->cp_mqd_control = tmp; 915 916 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 917 hqd_gpu_addr = ring->gpu_addr >> 8; 918 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 919 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 920 921 /* set the wb address whether it's enabled or not */ 922 wb_gpu_addr = ring->rptr_gpu_addr; 923 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 924 mqd->cp_hqd_pq_rptr_report_addr_hi = 925 upper_32_bits(wb_gpu_addr) & 0xffff; 926 927 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 928 wb_gpu_addr = ring->wptr_gpu_addr; 929 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 930 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 931 932 /* set up the HQD, this is similar to CP_RB0_CNTL */ 933 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 934 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 935 (order_base_2(ring->ring_size / 4) - 1)); 936 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 937 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 938 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 939 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 940 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 941 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 942 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 943 mqd->cp_hqd_pq_control = tmp; 944 945 /* enable doorbell */ 946 tmp = 0; 947 if (ring->use_doorbell) { 948 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 949 DOORBELL_OFFSET, ring->doorbell_index); 950 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 951 DOORBELL_EN, 1); 952 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 953 DOORBELL_SOURCE, 0); 954 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 955 DOORBELL_HIT, 0); 956 } else { 957 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 958 DOORBELL_EN, 0); 959 } 960 mqd->cp_hqd_pq_doorbell_control = tmp; 961 962 mqd->cp_hqd_vmid = 0; 963 /* activate the queue */ 964 mqd->cp_hqd_active = 1; 965 966 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 967 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 968 PRELOAD_SIZE, 0x55); 969 mqd->cp_hqd_persistent_state = tmp; 970 971 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 972 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 973 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 974 975 return 0; 976 } 977 978 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 979 { 980 struct v12_compute_mqd *mqd = ring->mqd_ptr; 981 struct amdgpu_device *adev = ring->adev; 982 uint32_t data = 0; 983 984 mutex_lock(&adev->srbm_mutex); 985 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 986 987 /* set CP_HQD_VMID.VMID = 0. */ 988 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 989 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 990 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 991 992 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 993 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 994 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 995 DOORBELL_EN, 0); 996 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 997 998 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 999 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1000 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1001 1002 /* set CP_MQD_CONTROL.VMID=0 */ 1003 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1004 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1005 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1006 1007 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1008 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1009 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1010 1011 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1012 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1013 mqd->cp_hqd_pq_rptr_report_addr_lo); 1014 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1015 mqd->cp_hqd_pq_rptr_report_addr_hi); 1016 1017 /* set CP_HQD_PQ_CONTROL */ 1018 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1019 1020 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1021 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1022 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1023 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1024 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1025 1026 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1027 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1028 mqd->cp_hqd_pq_doorbell_control); 1029 1030 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1031 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1032 1033 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1034 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1035 1036 soc21_grbm_select(adev, 0, 0, 0, 0); 1037 mutex_unlock(&adev->srbm_mutex); 1038 } 1039 1040 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1041 { 1042 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1043 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1044 int r; 1045 1046 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1047 return -EINVAL; 1048 1049 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1050 if (r) { 1051 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1052 return r; 1053 } 1054 1055 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 1056 1057 r = amdgpu_ring_test_ring(kiq_ring); 1058 if (r) { 1059 DRM_ERROR("kfq enable failed\n"); 1060 kiq_ring->sched.ready = false; 1061 } 1062 return r; 1063 } 1064 1065 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1066 enum admgpu_mes_pipe pipe) 1067 { 1068 struct amdgpu_ring *ring; 1069 int r; 1070 1071 if (pipe == AMDGPU_MES_KIQ_PIPE) 1072 ring = &adev->gfx.kiq[0].ring; 1073 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1074 ring = &adev->mes.ring; 1075 else 1076 BUG(); 1077 1078 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1079 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1080 *(ring->wptr_cpu_addr) = 0; 1081 *(ring->rptr_cpu_addr) = 0; 1082 amdgpu_ring_clear_ring(ring); 1083 } 1084 1085 r = mes_v12_0_mqd_init(ring); 1086 if (r) 1087 return r; 1088 1089 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1090 if (adev->enable_uni_mes) { 1091 mes_v12_0_queue_init_register(ring); 1092 } else { 1093 r = mes_v12_0_kiq_enable_queue(adev); 1094 if (r) 1095 return r; 1096 } 1097 } else { 1098 mes_v12_0_queue_init_register(ring); 1099 } 1100 1101 /* get MES scheduler/KIQ versions */ 1102 mutex_lock(&adev->srbm_mutex); 1103 soc21_grbm_select(adev, 3, pipe, 0, 0); 1104 1105 if (pipe == AMDGPU_MES_SCHED_PIPE) 1106 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1107 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1108 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1109 1110 soc21_grbm_select(adev, 0, 0, 0, 0); 1111 mutex_unlock(&adev->srbm_mutex); 1112 1113 return 0; 1114 } 1115 1116 static int mes_v12_0_ring_init(struct amdgpu_device *adev) 1117 { 1118 struct amdgpu_ring *ring; 1119 1120 ring = &adev->mes.ring; 1121 1122 ring->funcs = &mes_v12_0_ring_funcs; 1123 1124 ring->me = 3; 1125 ring->pipe = 0; 1126 ring->queue = 0; 1127 1128 ring->ring_obj = NULL; 1129 ring->use_doorbell = true; 1130 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1131 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1132 ring->no_scheduler = true; 1133 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1134 1135 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1136 AMDGPU_RING_PRIO_DEFAULT, NULL); 1137 } 1138 1139 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1140 { 1141 struct amdgpu_ring *ring; 1142 1143 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1144 1145 ring = &adev->gfx.kiq[0].ring; 1146 1147 ring->me = 3; 1148 ring->pipe = adev->enable_uni_mes ? 0 : 1; 1149 ring->queue = 0; 1150 1151 ring->adev = NULL; 1152 ring->ring_obj = NULL; 1153 ring->use_doorbell = true; 1154 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1155 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1156 ring->no_scheduler = true; 1157 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1158 ring->me, ring->pipe, ring->queue); 1159 1160 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1161 AMDGPU_RING_PRIO_DEFAULT, NULL); 1162 } 1163 1164 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1165 enum admgpu_mes_pipe pipe) 1166 { 1167 int r, mqd_size = sizeof(struct v12_compute_mqd); 1168 struct amdgpu_ring *ring; 1169 1170 if (pipe == AMDGPU_MES_KIQ_PIPE) 1171 ring = &adev->gfx.kiq[0].ring; 1172 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1173 ring = &adev->mes.ring; 1174 else 1175 BUG(); 1176 1177 if (ring->mqd_obj) 1178 return 0; 1179 1180 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1181 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1182 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1183 if (r) { 1184 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1185 return r; 1186 } 1187 1188 memset(ring->mqd_ptr, 0, mqd_size); 1189 1190 /* prepare MQD backup */ 1191 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1192 if (!adev->mes.mqd_backup[pipe]) 1193 dev_warn(adev->dev, 1194 "no memory to create MQD backup for ring %s\n", 1195 ring->name); 1196 1197 return 0; 1198 } 1199 1200 static int mes_v12_0_sw_init(void *handle) 1201 { 1202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1203 int pipe, r; 1204 1205 adev->mes.funcs = &mes_v12_0_funcs; 1206 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1207 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1208 1209 r = amdgpu_mes_init(adev); 1210 if (r) 1211 return r; 1212 1213 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1214 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1215 continue; 1216 1217 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1218 if (r) 1219 return r; 1220 1221 r = mes_v12_0_mqd_sw_init(adev, pipe); 1222 if (r) 1223 return r; 1224 } 1225 1226 if (adev->enable_mes_kiq) { 1227 r = mes_v12_0_kiq_ring_init(adev); 1228 if (r) 1229 return r; 1230 } 1231 1232 r = mes_v12_0_ring_init(adev); 1233 if (r) 1234 return r; 1235 1236 return 0; 1237 } 1238 1239 static int mes_v12_0_sw_fini(void *handle) 1240 { 1241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1242 int pipe; 1243 1244 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1245 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1246 1247 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1248 kfree(adev->mes.mqd_backup[pipe]); 1249 1250 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1251 &adev->mes.eop_gpu_addr[pipe], 1252 NULL); 1253 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1254 } 1255 1256 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1257 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1258 &adev->gfx.kiq[0].ring.mqd_ptr); 1259 1260 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1261 &adev->mes.ring.mqd_gpu_addr, 1262 &adev->mes.ring.mqd_ptr); 1263 1264 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1265 amdgpu_ring_fini(&adev->mes.ring); 1266 1267 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1268 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1269 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1270 } 1271 1272 amdgpu_mes_fini(adev); 1273 return 0; 1274 } 1275 1276 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1277 { 1278 uint32_t data; 1279 int i; 1280 1281 mutex_lock(&adev->srbm_mutex); 1282 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1283 1284 /* disable the queue if it's active */ 1285 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1286 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1287 for (i = 0; i < adev->usec_timeout; i++) { 1288 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1289 break; 1290 udelay(1); 1291 } 1292 } 1293 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1294 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1295 DOORBELL_EN, 0); 1296 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1297 DOORBELL_HIT, 1); 1298 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1299 1300 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1301 1302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1303 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1304 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1305 1306 soc21_grbm_select(adev, 0, 0, 0, 0); 1307 mutex_unlock(&adev->srbm_mutex); 1308 1309 adev->mes.ring.sched.ready = false; 1310 } 1311 1312 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1313 { 1314 uint32_t tmp; 1315 struct amdgpu_device *adev = ring->adev; 1316 1317 /* tell RLC which is KIQ queue */ 1318 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1319 tmp &= 0xffffff00; 1320 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1321 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1322 tmp |= 0x80; 1323 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1324 } 1325 1326 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1327 { 1328 int r = 0; 1329 1330 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1331 1332 if (adev->enable_uni_mes) 1333 return mes_v12_0_hw_init(adev); 1334 1335 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1336 1337 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1338 if (r) { 1339 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1340 return r; 1341 } 1342 1343 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1344 if (r) { 1345 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1346 return r; 1347 } 1348 1349 mes_v12_0_set_ucode_start_addr(adev); 1350 1351 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1352 mes_v12_0_set_ucode_start_addr(adev); 1353 1354 mes_v12_0_enable(adev, true); 1355 1356 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1357 if (r) 1358 goto failure; 1359 1360 r = mes_v12_0_hw_init(adev); 1361 if (r) 1362 goto failure; 1363 1364 return r; 1365 1366 failure: 1367 mes_v12_0_hw_fini(adev); 1368 return r; 1369 } 1370 1371 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1372 { 1373 if (!adev->enable_uni_mes && adev->mes.ring.sched.ready) 1374 mes_v12_0_kiq_dequeue_sched(adev); 1375 1376 if (!amdgpu_sriov_vf(adev)) 1377 mes_v12_0_enable(adev, false); 1378 1379 return 0; 1380 } 1381 1382 static int mes_v12_0_hw_init(void *handle) 1383 { 1384 int r; 1385 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1386 1387 if (adev->mes.ring.sched.ready) 1388 goto out; 1389 1390 if (!adev->enable_mes_kiq || adev->enable_uni_mes) { 1391 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1392 r = mes_v12_0_load_microcode(adev, 1393 AMDGPU_MES_SCHED_PIPE, true); 1394 if (r) { 1395 DRM_ERROR("failed to MES fw, r=%d\n", r); 1396 return r; 1397 } 1398 1399 mes_v12_0_set_ucode_start_addr(adev); 1400 1401 } else if (adev->firmware.load_type == 1402 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1403 1404 mes_v12_0_set_ucode_start_addr(adev); 1405 } 1406 1407 mes_v12_0_enable(adev, true); 1408 } 1409 1410 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1411 if (r) 1412 goto failure; 1413 1414 r = mes_v12_0_set_hw_resources(&adev->mes); 1415 if (r) 1416 goto failure; 1417 1418 if (adev->enable_uni_mes) 1419 mes_v12_0_set_hw_resources_1(&adev->mes); 1420 1421 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1422 1423 /* Enable the MES to handle doorbell ring on unmapped queue */ 1424 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1425 1426 r = mes_v12_0_query_sched_status(&adev->mes); 1427 if (r) { 1428 DRM_ERROR("MES is busy\n"); 1429 goto failure; 1430 } 1431 1432 out: 1433 /* 1434 * Disable KIQ ring usage from the driver once MES is enabled. 1435 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1436 * with MES enabled. 1437 */ 1438 adev->gfx.kiq[0].ring.sched.ready = false; 1439 adev->mes.ring.sched.ready = true; 1440 1441 return 0; 1442 1443 failure: 1444 mes_v12_0_hw_fini(adev); 1445 return r; 1446 } 1447 1448 static int mes_v12_0_hw_fini(void *handle) 1449 { 1450 return 0; 1451 } 1452 1453 static int mes_v12_0_suspend(void *handle) 1454 { 1455 int r; 1456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1457 1458 r = amdgpu_mes_suspend(adev); 1459 if (r) 1460 return r; 1461 1462 return mes_v12_0_hw_fini(adev); 1463 } 1464 1465 static int mes_v12_0_resume(void *handle) 1466 { 1467 int r; 1468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 1470 r = mes_v12_0_hw_init(adev); 1471 if (r) 1472 return r; 1473 1474 return amdgpu_mes_resume(adev); 1475 } 1476 1477 static int mes_v12_0_early_init(void *handle) 1478 { 1479 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1480 int pipe, r; 1481 1482 if (adev->enable_uni_mes) { 1483 r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1484 if (!r) 1485 return 0; 1486 1487 adev->enable_uni_mes = false; 1488 } 1489 1490 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1491 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1492 continue; 1493 r = amdgpu_mes_init_microcode(adev, pipe); 1494 if (r) 1495 return r; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static int mes_v12_0_late_init(void *handle) 1502 { 1503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1504 1505 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1506 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) 1507 amdgpu_mes_self_test(adev); 1508 1509 return 0; 1510 } 1511 1512 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1513 .name = "mes_v12_0", 1514 .early_init = mes_v12_0_early_init, 1515 .late_init = mes_v12_0_late_init, 1516 .sw_init = mes_v12_0_sw_init, 1517 .sw_fini = mes_v12_0_sw_fini, 1518 .hw_init = mes_v12_0_hw_init, 1519 .hw_fini = mes_v12_0_hw_fini, 1520 .suspend = mes_v12_0_suspend, 1521 .resume = mes_v12_0_resume, 1522 }; 1523 1524 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1525 .type = AMD_IP_BLOCK_TYPE_MES, 1526 .major = 12, 1527 .minor = 0, 1528 .rev = 0, 1529 .funcs = &mes_v12_0_ip_funcs, 1530 }; 1531