1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_12_0_0_offset.h" 30 #include "gc/gc_12_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 41 42 static int mes_v12_0_hw_init(void *handle); 43 static int mes_v12_0_hw_fini(void *handle); 44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v12_0_ring_get_rptr, 84 .get_wptr = mes_v12_0_ring_get_wptr, 85 .set_wptr = mes_v12_0_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static const char *mes_v12_0_opcodes[] = { 90 "SET_HW_RSRC", 91 "SET_SCHEDULING_CONFIG", 92 "ADD_QUEUE", 93 "REMOVE_QUEUE", 94 "PERFORM_YIELD", 95 "SET_GANG_PRIORITY_LEVEL", 96 "SUSPEND", 97 "RESUME", 98 "RESET", 99 "SET_LOG_BUFFER", 100 "CHANGE_GANG_PRORITY", 101 "QUERY_SCHEDULER_STATUS", 102 "SET_DEBUG_VMID", 103 "MISC", 104 "UPDATE_ROOT_PAGE_TABLE", 105 "AMD_LOG", 106 "SET_SE_MODE", 107 "SET_GANG_SUBMIT", 108 "SET_HW_RSRC_1", 109 }; 110 111 static const char *mes_v12_0_misc_opcodes[] = { 112 "WRITE_REG", 113 "INV_GART", 114 "QUERY_STATUS", 115 "READ_REG", 116 "WAIT_REG_MEM", 117 "SET_SHADER_DEBUGGER", 118 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 119 "NOTIFY_TO_UNMAP_PROCESSES", 120 }; 121 122 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 123 { 124 const char *op_str = NULL; 125 126 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 127 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 128 129 return op_str; 130 } 131 132 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 133 { 134 const char *op_str = NULL; 135 136 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 137 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 138 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 139 140 return op_str; 141 } 142 143 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 144 void *pkt, int size, 145 int api_status_off) 146 { 147 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 148 signed long timeout = 3000000; /* 3000 ms */ 149 struct amdgpu_device *adev = mes->adev; 150 struct amdgpu_ring *ring = &mes->ring; 151 struct MES_API_STATUS *api_status; 152 union MESAPI__MISC *x_pkt = pkt; 153 const char *op_str, *misc_op_str; 154 unsigned long flags; 155 u64 status_gpu_addr; 156 u32 status_offset; 157 u64 *status_ptr; 158 signed long r; 159 int ret; 160 161 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 162 return -EINVAL; 163 164 if (amdgpu_emu_mode) { 165 timeout *= 100; 166 } else if (amdgpu_sriov_vf(adev)) { 167 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 168 timeout = 15 * 600 * 1000; 169 } 170 171 ret = amdgpu_device_wb_get(adev, &status_offset); 172 if (ret) 173 return ret; 174 175 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 176 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 177 *status_ptr = 0; 178 179 spin_lock_irqsave(&mes->ring_lock, flags); 180 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 181 if (r) 182 goto error_unlock_free; 183 184 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 185 api_status->api_completion_fence_addr = status_gpu_addr; 186 api_status->api_completion_fence_value = 1; 187 188 amdgpu_ring_write_multiple(ring, pkt, size / 4); 189 190 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 191 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 192 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 193 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 194 mes_status_pkt.api_status.api_completion_fence_addr = 195 ring->fence_drv.gpu_addr; 196 mes_status_pkt.api_status.api_completion_fence_value = 197 ++ring->fence_drv.sync_seq; 198 199 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 200 sizeof(mes_status_pkt) / 4); 201 202 amdgpu_ring_commit(ring); 203 spin_unlock_irqrestore(&mes->ring_lock, flags); 204 205 op_str = mes_v12_0_get_op_string(x_pkt); 206 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 207 208 if (misc_op_str) 209 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 210 misc_op_str); 211 else if (op_str) 212 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 213 else 214 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 215 x_pkt->header.opcode); 216 217 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, timeout); 218 if (r < 1 || !*status_ptr) { 219 220 if (misc_op_str) 221 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 222 op_str, misc_op_str); 223 else if (op_str) 224 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 225 op_str); 226 else 227 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 228 x_pkt->header.opcode); 229 230 while (halt_if_hws_hang) 231 schedule(); 232 233 r = -ETIMEDOUT; 234 goto error_wb_free; 235 } 236 237 amdgpu_device_wb_free(adev, status_offset); 238 return 0; 239 240 error_unlock_free: 241 spin_unlock_irqrestore(&mes->ring_lock, flags); 242 243 error_wb_free: 244 amdgpu_device_wb_free(adev, status_offset); 245 return r; 246 } 247 248 static int convert_to_mes_queue_type(int queue_type) 249 { 250 if (queue_type == AMDGPU_RING_TYPE_GFX) 251 return MES_QUEUE_TYPE_GFX; 252 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 253 return MES_QUEUE_TYPE_COMPUTE; 254 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 255 return MES_QUEUE_TYPE_SDMA; 256 else 257 BUG(); 258 return -1; 259 } 260 261 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 262 struct mes_add_queue_input *input) 263 { 264 struct amdgpu_device *adev = mes->adev; 265 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 266 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 267 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 268 269 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 270 271 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 272 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 273 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 274 275 mes_add_queue_pkt.process_id = input->process_id; 276 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 277 mes_add_queue_pkt.process_va_start = input->process_va_start; 278 mes_add_queue_pkt.process_va_end = input->process_va_end; 279 mes_add_queue_pkt.process_quantum = input->process_quantum; 280 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 281 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 282 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 283 mes_add_queue_pkt.inprocess_gang_priority = 284 input->inprocess_gang_priority; 285 mes_add_queue_pkt.gang_global_priority_level = 286 input->gang_global_priority_level; 287 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 288 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 289 290 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 291 292 mes_add_queue_pkt.queue_type = 293 convert_to_mes_queue_type(input->queue_type); 294 mes_add_queue_pkt.paging = input->paging; 295 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 296 mes_add_queue_pkt.gws_base = input->gws_base; 297 mes_add_queue_pkt.gws_size = input->gws_size; 298 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 299 mes_add_queue_pkt.tma_addr = input->tma_addr; 300 mes_add_queue_pkt.trap_en = input->trap_en; 301 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 302 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 303 304 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 305 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 306 mes_add_queue_pkt.gds_size = input->queue_size; 307 308 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 309 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 310 mes_add_queue_pkt.gds_size = input->queue_size; 311 312 return mes_v12_0_submit_pkt_and_poll_completion(mes, 313 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 314 offsetof(union MESAPI__ADD_QUEUE, api_status)); 315 } 316 317 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 318 struct mes_remove_queue_input *input) 319 { 320 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 321 322 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 323 324 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 325 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 326 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 327 328 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 329 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 330 331 return mes_v12_0_submit_pkt_and_poll_completion(mes, 332 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 333 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 334 } 335 336 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 337 struct mes_map_legacy_queue_input *input) 338 { 339 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 340 341 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 342 343 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 344 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 345 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 346 347 mes_add_queue_pkt.pipe_id = input->pipe_id; 348 mes_add_queue_pkt.queue_id = input->queue_id; 349 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 350 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 351 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 352 mes_add_queue_pkt.queue_type = 353 convert_to_mes_queue_type(input->queue_type); 354 mes_add_queue_pkt.map_legacy_kq = 1; 355 356 return mes_v12_0_submit_pkt_and_poll_completion(mes, 357 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 358 offsetof(union MESAPI__ADD_QUEUE, api_status)); 359 } 360 361 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 362 struct mes_unmap_legacy_queue_input *input) 363 { 364 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 365 366 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 367 368 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 369 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 370 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 371 372 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 373 mes_remove_queue_pkt.gang_context_addr = 0; 374 375 mes_remove_queue_pkt.pipe_id = input->pipe_id; 376 mes_remove_queue_pkt.queue_id = input->queue_id; 377 378 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 379 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 380 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 381 mes_remove_queue_pkt.tf_data = 382 lower_32_bits(input->trail_fence_data); 383 } else { 384 mes_remove_queue_pkt.unmap_legacy_queue = 1; 385 mes_remove_queue_pkt.queue_type = 386 convert_to_mes_queue_type(input->queue_type); 387 } 388 389 return mes_v12_0_submit_pkt_and_poll_completion(mes, 390 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 391 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 392 } 393 394 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 395 struct mes_suspend_gang_input *input) 396 { 397 return 0; 398 } 399 400 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 401 struct mes_resume_gang_input *input) 402 { 403 return 0; 404 } 405 406 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes) 407 { 408 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 409 410 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 411 412 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 413 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 414 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 415 416 return mes_v12_0_submit_pkt_and_poll_completion(mes, 417 &mes_status_pkt, sizeof(mes_status_pkt), 418 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 419 } 420 421 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 422 struct mes_misc_op_input *input) 423 { 424 union MESAPI__MISC misc_pkt; 425 426 memset(&misc_pkt, 0, sizeof(misc_pkt)); 427 428 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 429 misc_pkt.header.opcode = MES_SCH_API_MISC; 430 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 431 432 switch (input->op) { 433 case MES_MISC_OP_READ_REG: 434 misc_pkt.opcode = MESAPI_MISC__READ_REG; 435 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 436 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 437 break; 438 case MES_MISC_OP_WRITE_REG: 439 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 440 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 441 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 442 break; 443 case MES_MISC_OP_WRM_REG_WAIT: 444 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 445 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 446 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 447 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 448 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 449 misc_pkt.wait_reg_mem.reg_offset2 = 0; 450 break; 451 case MES_MISC_OP_WRM_REG_WR_WAIT: 452 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 453 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 454 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 455 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 456 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 457 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 458 break; 459 case MES_MISC_OP_SET_SHADER_DEBUGGER: 460 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 461 misc_pkt.set_shader_debugger.process_context_addr = 462 input->set_shader_debugger.process_context_addr; 463 misc_pkt.set_shader_debugger.flags.u32all = 464 input->set_shader_debugger.flags.u32all; 465 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 466 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 467 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 468 input->set_shader_debugger.tcp_watch_cntl, 469 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 470 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 471 break; 472 default: 473 DRM_ERROR("unsupported misc op (%d) \n", input->op); 474 return -EINVAL; 475 } 476 477 return mes_v12_0_submit_pkt_and_poll_completion(mes, 478 &misc_pkt, sizeof(misc_pkt), 479 offsetof(union MESAPI__MISC, api_status)); 480 } 481 482 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes) 483 { 484 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 485 486 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 487 488 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 489 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 490 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 491 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 492 493 return mes_v12_0_submit_pkt_and_poll_completion(mes, 494 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 495 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 496 } 497 498 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) 499 { 500 int i; 501 struct amdgpu_device *adev = mes->adev; 502 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 503 504 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 505 506 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 507 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 508 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 509 510 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 511 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 512 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 513 mes_set_hw_res_pkt.paging_vmid = 0; 514 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 515 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 516 mes->query_status_fence_gpu_addr; 517 518 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 519 mes_set_hw_res_pkt.compute_hqd_mask[i] = 520 mes->compute_hqd_mask[i]; 521 522 for (i = 0; i < MAX_GFX_PIPES; i++) 523 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 524 525 for (i = 0; i < MAX_SDMA_PIPES; i++) 526 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 527 528 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 529 mes_set_hw_res_pkt.aggregated_doorbells[i] = 530 mes->aggregated_doorbells[i]; 531 532 for (i = 0; i < 5; i++) { 533 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 534 mes_set_hw_res_pkt.mmhub_base[i] = 535 adev->reg_offset[MMHUB_HWIP][0][i]; 536 mes_set_hw_res_pkt.osssys_base[i] = 537 adev->reg_offset[OSSSYS_HWIP][0][i]; 538 } 539 540 mes_set_hw_res_pkt.disable_reset = 1; 541 mes_set_hw_res_pkt.disable_mes_log = 1; 542 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 543 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 544 545 /* 546 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 547 * handling support, other queue will not use the oversubscribe timer. 548 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 549 */ 550 mes_set_hw_res_pkt.oversubscription_timer = 50; 551 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 552 553 mes_set_hw_res_pkt.enable_mes_event_int_logging = 0; 554 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 555 556 return mes_v12_0_submit_pkt_and_poll_completion(mes, 557 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 558 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 559 } 560 561 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 562 { 563 struct amdgpu_device *adev = mes->adev; 564 uint32_t data; 565 566 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 567 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 568 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 569 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 570 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 571 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 572 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 573 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 574 575 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 576 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 577 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 578 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 579 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 580 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 581 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 582 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 583 584 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 585 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 586 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 587 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 588 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 589 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 590 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 591 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 592 593 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 594 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 595 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 596 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 597 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 598 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 599 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 600 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 601 602 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 603 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 604 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 605 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 606 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 607 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 608 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 609 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 610 611 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 612 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 613 } 614 615 616 static void mes_v12_0_enable_unmapped_doorbell_handling( 617 struct amdgpu_mes *mes, bool enable) 618 { 619 struct amdgpu_device *adev = mes->adev; 620 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 621 622 /* 623 * The default PROC_LSB settng is 0xc which means doorbell 624 * addr[16:12] gives the doorbell page number. For kfd, each 625 * process will use 2 pages of doorbell, we need to change the 626 * setting to 0xd 627 */ 628 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 629 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 630 631 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 632 633 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 634 } 635 636 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 637 .add_hw_queue = mes_v12_0_add_hw_queue, 638 .remove_hw_queue = mes_v12_0_remove_hw_queue, 639 .map_legacy_queue = mes_v12_0_map_legacy_queue, 640 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 641 .suspend_gang = mes_v12_0_suspend_gang, 642 .resume_gang = mes_v12_0_resume_gang, 643 .misc_op = mes_v12_0_misc_op, 644 }; 645 646 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 647 enum admgpu_mes_pipe pipe) 648 { 649 int r; 650 const struct mes_firmware_header_v1_0 *mes_hdr; 651 const __le32 *fw_data; 652 unsigned fw_size; 653 654 mes_hdr = (const struct mes_firmware_header_v1_0 *) 655 adev->mes.fw[pipe]->data; 656 657 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 658 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 659 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 660 661 r = amdgpu_bo_create_reserved(adev, fw_size, 662 PAGE_SIZE, 663 AMDGPU_GEM_DOMAIN_VRAM, 664 &adev->mes.ucode_fw_obj[pipe], 665 &adev->mes.ucode_fw_gpu_addr[pipe], 666 (void **)&adev->mes.ucode_fw_ptr[pipe]); 667 if (r) { 668 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 669 return r; 670 } 671 672 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 673 674 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 675 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 676 677 return 0; 678 } 679 680 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 681 enum admgpu_mes_pipe pipe) 682 { 683 int r; 684 const struct mes_firmware_header_v1_0 *mes_hdr; 685 const __le32 *fw_data; 686 unsigned fw_size; 687 688 mes_hdr = (const struct mes_firmware_header_v1_0 *) 689 adev->mes.fw[pipe]->data; 690 691 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 692 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 693 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 694 695 r = amdgpu_bo_create_reserved(adev, fw_size, 696 64 * 1024, 697 AMDGPU_GEM_DOMAIN_VRAM, 698 &adev->mes.data_fw_obj[pipe], 699 &adev->mes.data_fw_gpu_addr[pipe], 700 (void **)&adev->mes.data_fw_ptr[pipe]); 701 if (r) { 702 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 703 return r; 704 } 705 706 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 707 708 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 709 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 710 711 return 0; 712 } 713 714 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 715 enum admgpu_mes_pipe pipe) 716 { 717 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 718 &adev->mes.data_fw_gpu_addr[pipe], 719 (void **)&adev->mes.data_fw_ptr[pipe]); 720 721 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 722 &adev->mes.ucode_fw_gpu_addr[pipe], 723 (void **)&adev->mes.ucode_fw_ptr[pipe]); 724 } 725 726 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 727 { 728 uint64_t ucode_addr; 729 uint32_t pipe, data = 0; 730 731 if (enable) { 732 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 733 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 734 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 735 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 736 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 737 738 mutex_lock(&adev->srbm_mutex); 739 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 740 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 741 pipe == AMDGPU_MES_KIQ_PIPE) 742 continue; 743 744 soc21_grbm_select(adev, 3, pipe, 0, 0); 745 746 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 747 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 748 lower_32_bits(ucode_addr)); 749 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 750 upper_32_bits(ucode_addr)); 751 } 752 soc21_grbm_select(adev, 0, 0, 0, 0); 753 mutex_unlock(&adev->srbm_mutex); 754 755 /* unhalt MES and activate pipe0 */ 756 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 757 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 758 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 759 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 760 761 if (amdgpu_emu_mode) 762 msleep(100); 763 else if (adev->enable_uni_mes) 764 udelay(500); 765 else 766 udelay(50); 767 } else { 768 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 769 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 770 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 771 data = REG_SET_FIELD(data, CP_MES_CNTL, 772 MES_INVALIDATE_ICACHE, 1); 773 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 774 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 775 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 776 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 777 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 778 } 779 } 780 781 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 782 { 783 uint64_t ucode_addr; 784 int pipe; 785 786 mes_v12_0_enable(adev, false); 787 788 mutex_lock(&adev->srbm_mutex); 789 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 790 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 791 pipe == AMDGPU_MES_KIQ_PIPE) 792 continue; 793 794 /* me=3, queue=0 */ 795 soc21_grbm_select(adev, 3, pipe, 0, 0); 796 797 /* set ucode start address */ 798 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 799 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 800 lower_32_bits(ucode_addr)); 801 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 802 upper_32_bits(ucode_addr)); 803 804 soc21_grbm_select(adev, 0, 0, 0, 0); 805 } 806 mutex_unlock(&adev->srbm_mutex); 807 } 808 809 /* This function is for backdoor MES firmware */ 810 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 811 enum admgpu_mes_pipe pipe, bool prime_icache) 812 { 813 int r; 814 uint32_t data; 815 816 mes_v12_0_enable(adev, false); 817 818 if (!adev->mes.fw[pipe]) 819 return -EINVAL; 820 821 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 822 if (r) 823 return r; 824 825 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 826 if (r) { 827 mes_v12_0_free_ucode_buffers(adev, pipe); 828 return r; 829 } 830 831 mutex_lock(&adev->srbm_mutex); 832 /* me=3, pipe=0, queue=0 */ 833 soc21_grbm_select(adev, 3, pipe, 0, 0); 834 835 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 836 837 /* set ucode fimrware address */ 838 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 839 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 840 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 841 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 842 843 /* set ucode instruction cache boundary to 2M-1 */ 844 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 845 846 /* set ucode data firmware address */ 847 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 848 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 849 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 850 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 851 852 /* Set data cache boundary CP_MES_MDBOUND_LO */ 853 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 854 855 if (prime_icache) { 856 /* invalidate ICACHE */ 857 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 858 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 859 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 860 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 861 862 /* prime the ICACHE. */ 863 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 864 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 865 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 866 } 867 868 soc21_grbm_select(adev, 0, 0, 0, 0); 869 mutex_unlock(&adev->srbm_mutex); 870 871 return 0; 872 } 873 874 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 875 enum admgpu_mes_pipe pipe) 876 { 877 int r; 878 u32 *eop; 879 880 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 881 AMDGPU_GEM_DOMAIN_GTT, 882 &adev->mes.eop_gpu_obj[pipe], 883 &adev->mes.eop_gpu_addr[pipe], 884 (void **)&eop); 885 if (r) { 886 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 887 return r; 888 } 889 890 memset(eop, 0, 891 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 892 893 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 894 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 895 896 return 0; 897 } 898 899 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 900 { 901 struct v12_compute_mqd *mqd = ring->mqd_ptr; 902 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 903 uint32_t tmp; 904 905 mqd->header = 0xC0310800; 906 mqd->compute_pipelinestat_enable = 0x00000001; 907 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 908 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 909 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 910 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 911 mqd->compute_misc_reserved = 0x00000007; 912 913 eop_base_addr = ring->eop_gpu_addr >> 8; 914 915 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 916 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 917 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 918 (order_base_2(MES_EOP_SIZE / 4) - 1)); 919 920 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 921 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 922 mqd->cp_hqd_eop_control = tmp; 923 924 /* disable the queue if it's active */ 925 ring->wptr = 0; 926 mqd->cp_hqd_pq_rptr = 0; 927 mqd->cp_hqd_pq_wptr_lo = 0; 928 mqd->cp_hqd_pq_wptr_hi = 0; 929 930 /* set the pointer to the MQD */ 931 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 932 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 933 934 /* set MQD vmid to 0 */ 935 tmp = regCP_MQD_CONTROL_DEFAULT; 936 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 937 mqd->cp_mqd_control = tmp; 938 939 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 940 hqd_gpu_addr = ring->gpu_addr >> 8; 941 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 942 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 943 944 /* set the wb address whether it's enabled or not */ 945 wb_gpu_addr = ring->rptr_gpu_addr; 946 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 947 mqd->cp_hqd_pq_rptr_report_addr_hi = 948 upper_32_bits(wb_gpu_addr) & 0xffff; 949 950 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 951 wb_gpu_addr = ring->wptr_gpu_addr; 952 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 953 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 954 955 /* set up the HQD, this is similar to CP_RB0_CNTL */ 956 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 957 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 958 (order_base_2(ring->ring_size / 4) - 1)); 959 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 960 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 961 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 962 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 963 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 964 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 965 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 966 mqd->cp_hqd_pq_control = tmp; 967 968 /* enable doorbell */ 969 tmp = 0; 970 if (ring->use_doorbell) { 971 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 972 DOORBELL_OFFSET, ring->doorbell_index); 973 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 974 DOORBELL_EN, 1); 975 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 976 DOORBELL_SOURCE, 0); 977 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 978 DOORBELL_HIT, 0); 979 } else { 980 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 981 DOORBELL_EN, 0); 982 } 983 mqd->cp_hqd_pq_doorbell_control = tmp; 984 985 mqd->cp_hqd_vmid = 0; 986 /* activate the queue */ 987 mqd->cp_hqd_active = 1; 988 989 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 990 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 991 PRELOAD_SIZE, 0x55); 992 mqd->cp_hqd_persistent_state = tmp; 993 994 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 995 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 996 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 997 998 /* 999 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1000 * doorbell handling. This is a reserved CP internal register can 1001 * not be accesss by others 1002 */ 1003 mqd->reserved_184 = BIT(15); 1004 1005 return 0; 1006 } 1007 1008 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1009 { 1010 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1011 struct amdgpu_device *adev = ring->adev; 1012 uint32_t data = 0; 1013 1014 mutex_lock(&adev->srbm_mutex); 1015 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1016 1017 /* set CP_HQD_VMID.VMID = 0. */ 1018 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1019 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1020 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1021 1022 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1023 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1024 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1025 DOORBELL_EN, 0); 1026 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1027 1028 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1029 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1030 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1031 1032 /* set CP_MQD_CONTROL.VMID=0 */ 1033 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1034 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1035 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1036 1037 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1038 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1039 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1040 1041 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1042 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1043 mqd->cp_hqd_pq_rptr_report_addr_lo); 1044 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1045 mqd->cp_hqd_pq_rptr_report_addr_hi); 1046 1047 /* set CP_HQD_PQ_CONTROL */ 1048 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1049 1050 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1051 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1052 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1053 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1054 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1055 1056 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1057 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1058 mqd->cp_hqd_pq_doorbell_control); 1059 1060 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1061 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1062 1063 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1064 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1065 1066 soc21_grbm_select(adev, 0, 0, 0, 0); 1067 mutex_unlock(&adev->srbm_mutex); 1068 } 1069 1070 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1071 { 1072 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1073 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1074 int r; 1075 1076 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1077 return -EINVAL; 1078 1079 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1080 if (r) { 1081 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1082 return r; 1083 } 1084 1085 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 1086 1087 r = amdgpu_ring_test_ring(kiq_ring); 1088 if (r) { 1089 DRM_ERROR("kfq enable failed\n"); 1090 kiq_ring->sched.ready = false; 1091 } 1092 return r; 1093 } 1094 1095 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1096 enum admgpu_mes_pipe pipe) 1097 { 1098 struct amdgpu_ring *ring; 1099 int r; 1100 1101 if (pipe == AMDGPU_MES_KIQ_PIPE) 1102 ring = &adev->gfx.kiq[0].ring; 1103 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1104 ring = &adev->mes.ring; 1105 else 1106 BUG(); 1107 1108 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1109 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1110 *(ring->wptr_cpu_addr) = 0; 1111 *(ring->rptr_cpu_addr) = 0; 1112 amdgpu_ring_clear_ring(ring); 1113 } 1114 1115 r = mes_v12_0_mqd_init(ring); 1116 if (r) 1117 return r; 1118 1119 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1120 if (adev->enable_uni_mes) { 1121 mes_v12_0_queue_init_register(ring); 1122 } else { 1123 r = mes_v12_0_kiq_enable_queue(adev); 1124 if (r) 1125 return r; 1126 } 1127 } else { 1128 mes_v12_0_queue_init_register(ring); 1129 } 1130 1131 /* get MES scheduler/KIQ versions */ 1132 mutex_lock(&adev->srbm_mutex); 1133 soc21_grbm_select(adev, 3, pipe, 0, 0); 1134 1135 if (pipe == AMDGPU_MES_SCHED_PIPE) 1136 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1137 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1138 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1139 1140 soc21_grbm_select(adev, 0, 0, 0, 0); 1141 mutex_unlock(&adev->srbm_mutex); 1142 1143 return 0; 1144 } 1145 1146 static int mes_v12_0_ring_init(struct amdgpu_device *adev) 1147 { 1148 struct amdgpu_ring *ring; 1149 1150 ring = &adev->mes.ring; 1151 1152 ring->funcs = &mes_v12_0_ring_funcs; 1153 1154 ring->me = 3; 1155 ring->pipe = 0; 1156 ring->queue = 0; 1157 1158 ring->ring_obj = NULL; 1159 ring->use_doorbell = true; 1160 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1161 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1162 ring->no_scheduler = true; 1163 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1164 1165 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1166 AMDGPU_RING_PRIO_DEFAULT, NULL); 1167 } 1168 1169 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1170 { 1171 struct amdgpu_ring *ring; 1172 1173 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1174 1175 ring = &adev->gfx.kiq[0].ring; 1176 1177 ring->me = 3; 1178 ring->pipe = adev->enable_uni_mes ? 0 : 1; 1179 ring->queue = 0; 1180 1181 ring->adev = NULL; 1182 ring->ring_obj = NULL; 1183 ring->use_doorbell = true; 1184 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1185 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1186 ring->no_scheduler = true; 1187 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1188 ring->me, ring->pipe, ring->queue); 1189 1190 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1191 AMDGPU_RING_PRIO_DEFAULT, NULL); 1192 } 1193 1194 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1195 enum admgpu_mes_pipe pipe) 1196 { 1197 int r, mqd_size = sizeof(struct v12_compute_mqd); 1198 struct amdgpu_ring *ring; 1199 1200 if (pipe == AMDGPU_MES_KIQ_PIPE) 1201 ring = &adev->gfx.kiq[0].ring; 1202 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1203 ring = &adev->mes.ring; 1204 else 1205 BUG(); 1206 1207 if (ring->mqd_obj) 1208 return 0; 1209 1210 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1211 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1212 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1213 if (r) { 1214 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1215 return r; 1216 } 1217 1218 memset(ring->mqd_ptr, 0, mqd_size); 1219 1220 /* prepare MQD backup */ 1221 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1222 if (!adev->mes.mqd_backup[pipe]) 1223 dev_warn(adev->dev, 1224 "no memory to create MQD backup for ring %s\n", 1225 ring->name); 1226 1227 return 0; 1228 } 1229 1230 static int mes_v12_0_sw_init(void *handle) 1231 { 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 int pipe, r; 1234 1235 adev->mes.funcs = &mes_v12_0_funcs; 1236 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1237 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1238 1239 r = amdgpu_mes_init(adev); 1240 if (r) 1241 return r; 1242 1243 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1244 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1245 continue; 1246 1247 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1248 if (r) 1249 return r; 1250 1251 r = mes_v12_0_mqd_sw_init(adev, pipe); 1252 if (r) 1253 return r; 1254 } 1255 1256 if (adev->enable_mes_kiq) { 1257 r = mes_v12_0_kiq_ring_init(adev); 1258 if (r) 1259 return r; 1260 } 1261 1262 r = mes_v12_0_ring_init(adev); 1263 if (r) 1264 return r; 1265 1266 return 0; 1267 } 1268 1269 static int mes_v12_0_sw_fini(void *handle) 1270 { 1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1272 int pipe; 1273 1274 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1275 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1276 1277 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1278 kfree(adev->mes.mqd_backup[pipe]); 1279 1280 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1281 &adev->mes.eop_gpu_addr[pipe], 1282 NULL); 1283 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1284 } 1285 1286 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1287 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1288 &adev->gfx.kiq[0].ring.mqd_ptr); 1289 1290 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1291 &adev->mes.ring.mqd_gpu_addr, 1292 &adev->mes.ring.mqd_ptr); 1293 1294 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1295 amdgpu_ring_fini(&adev->mes.ring); 1296 1297 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1298 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1299 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1300 } 1301 1302 amdgpu_mes_fini(adev); 1303 return 0; 1304 } 1305 1306 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1307 { 1308 uint32_t data; 1309 int i; 1310 1311 mutex_lock(&adev->srbm_mutex); 1312 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1313 1314 /* disable the queue if it's active */ 1315 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1316 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1317 for (i = 0; i < adev->usec_timeout; i++) { 1318 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1319 break; 1320 udelay(1); 1321 } 1322 } 1323 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1324 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1325 DOORBELL_EN, 0); 1326 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1327 DOORBELL_HIT, 1); 1328 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1329 1330 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1331 1332 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1333 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1334 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1335 1336 soc21_grbm_select(adev, 0, 0, 0, 0); 1337 mutex_unlock(&adev->srbm_mutex); 1338 1339 adev->mes.ring.sched.ready = false; 1340 } 1341 1342 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1343 { 1344 uint32_t tmp; 1345 struct amdgpu_device *adev = ring->adev; 1346 1347 /* tell RLC which is KIQ queue */ 1348 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1349 tmp &= 0xffffff00; 1350 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1351 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1352 tmp |= 0x80; 1353 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1354 } 1355 1356 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1357 { 1358 int r = 0; 1359 1360 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1361 1362 if (adev->enable_uni_mes) 1363 return mes_v12_0_hw_init(adev); 1364 1365 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1366 1367 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1368 if (r) { 1369 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1370 return r; 1371 } 1372 1373 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1374 if (r) { 1375 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1376 return r; 1377 } 1378 1379 mes_v12_0_set_ucode_start_addr(adev); 1380 1381 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1382 mes_v12_0_set_ucode_start_addr(adev); 1383 1384 mes_v12_0_enable(adev, true); 1385 1386 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1387 if (r) 1388 goto failure; 1389 1390 r = mes_v12_0_hw_init(adev); 1391 if (r) 1392 goto failure; 1393 1394 return r; 1395 1396 failure: 1397 mes_v12_0_hw_fini(adev); 1398 return r; 1399 } 1400 1401 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1402 { 1403 if (adev->mes.ring.sched.ready) { 1404 mes_v12_0_kiq_dequeue_sched(adev); 1405 adev->mes.ring.sched.ready = false; 1406 } 1407 1408 mes_v12_0_enable(adev, false); 1409 1410 return 0; 1411 } 1412 1413 static int mes_v12_0_hw_init(void *handle) 1414 { 1415 int r; 1416 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1417 1418 if (adev->mes.ring.sched.ready) 1419 goto out; 1420 1421 if (!adev->enable_mes_kiq || adev->enable_uni_mes) { 1422 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1423 r = mes_v12_0_load_microcode(adev, 1424 AMDGPU_MES_SCHED_PIPE, true); 1425 if (r) { 1426 DRM_ERROR("failed to MES fw, r=%d\n", r); 1427 return r; 1428 } 1429 1430 mes_v12_0_set_ucode_start_addr(adev); 1431 1432 } else if (adev->firmware.load_type == 1433 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1434 1435 mes_v12_0_set_ucode_start_addr(adev); 1436 } 1437 1438 mes_v12_0_enable(adev, true); 1439 } 1440 1441 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1442 if (r) 1443 goto failure; 1444 1445 r = mes_v12_0_set_hw_resources(&adev->mes); 1446 if (r) 1447 goto failure; 1448 1449 if (adev->enable_uni_mes) 1450 mes_v12_0_set_hw_resources_1(&adev->mes); 1451 1452 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1453 1454 /* Enable the MES to handle doorbell ring on unmapped queue */ 1455 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1456 1457 r = mes_v12_0_query_sched_status(&adev->mes); 1458 if (r) { 1459 DRM_ERROR("MES is busy\n"); 1460 goto failure; 1461 } 1462 1463 out: 1464 /* 1465 * Disable KIQ ring usage from the driver once MES is enabled. 1466 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1467 * with MES enabled. 1468 */ 1469 adev->gfx.kiq[0].ring.sched.ready = false; 1470 adev->mes.ring.sched.ready = true; 1471 1472 return 0; 1473 1474 failure: 1475 mes_v12_0_hw_fini(adev); 1476 return r; 1477 } 1478 1479 static int mes_v12_0_hw_fini(void *handle) 1480 { 1481 return 0; 1482 } 1483 1484 static int mes_v12_0_suspend(void *handle) 1485 { 1486 int r; 1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1488 1489 r = amdgpu_mes_suspend(adev); 1490 if (r) 1491 return r; 1492 1493 return mes_v12_0_hw_fini(adev); 1494 } 1495 1496 static int mes_v12_0_resume(void *handle) 1497 { 1498 int r; 1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1500 1501 r = mes_v12_0_hw_init(adev); 1502 if (r) 1503 return r; 1504 1505 return amdgpu_mes_resume(adev); 1506 } 1507 1508 static int mes_v12_0_early_init(void *handle) 1509 { 1510 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1511 int pipe, r; 1512 1513 if (adev->enable_uni_mes) { 1514 r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1515 if (!r) 1516 return 0; 1517 1518 adev->enable_uni_mes = false; 1519 } 1520 1521 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1522 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1523 continue; 1524 r = amdgpu_mes_init_microcode(adev, pipe); 1525 if (r) 1526 return r; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int mes_v12_0_late_init(void *handle) 1533 { 1534 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1535 1536 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1537 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) 1538 amdgpu_mes_self_test(adev); 1539 1540 return 0; 1541 } 1542 1543 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1544 .name = "mes_v12_0", 1545 .early_init = mes_v12_0_early_init, 1546 .late_init = mes_v12_0_late_init, 1547 .sw_init = mes_v12_0_sw_init, 1548 .sw_fini = mes_v12_0_sw_fini, 1549 .hw_init = mes_v12_0_hw_init, 1550 .hw_fini = mes_v12_0_hw_fini, 1551 .suspend = mes_v12_0_suspend, 1552 .resume = mes_v12_0_resume, 1553 }; 1554 1555 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1556 .type = AMD_IP_BLOCK_TYPE_MES, 1557 .major = 12, 1558 .minor = 0, 1559 .rev = 0, 1560 .funcs = &mes_v12_0_ip_funcs, 1561 }; 1562