1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_12_0_0_offset.h" 30 #include "gc/gc_12_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v12_structs.h" 33 #include "mes_v12_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 41 42 static int mes_v12_0_hw_init(void *handle); 43 static int mes_v12_0_hw_fini(void *handle); 44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v12_0_ring_get_rptr, 84 .get_wptr = mes_v12_0_ring_get_wptr, 85 .set_wptr = mes_v12_0_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static const char *mes_v12_0_opcodes[] = { 90 "SET_HW_RSRC", 91 "SET_SCHEDULING_CONFIG", 92 "ADD_QUEUE", 93 "REMOVE_QUEUE", 94 "PERFORM_YIELD", 95 "SET_GANG_PRIORITY_LEVEL", 96 "SUSPEND", 97 "RESUME", 98 "RESET", 99 "SET_LOG_BUFFER", 100 "CHANGE_GANG_PRORITY", 101 "QUERY_SCHEDULER_STATUS", 102 "unused", 103 "SET_DEBUG_VMID", 104 "MISC", 105 "UPDATE_ROOT_PAGE_TABLE", 106 "AMD_LOG", 107 "SET_SE_MODE", 108 "SET_GANG_SUBMIT", 109 "SET_HW_RSRC_1", 110 }; 111 112 static const char *mes_v12_0_misc_opcodes[] = { 113 "WRITE_REG", 114 "INV_GART", 115 "QUERY_STATUS", 116 "READ_REG", 117 "WAIT_REG_MEM", 118 "SET_SHADER_DEBUGGER", 119 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 120 "NOTIFY_TO_UNMAP_PROCESSES", 121 }; 122 123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 124 { 125 const char *op_str = NULL; 126 127 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 128 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 129 130 return op_str; 131 } 132 133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 134 { 135 const char *op_str = NULL; 136 137 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 138 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 139 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 140 141 return op_str; 142 } 143 144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 145 void *pkt, int size, 146 int api_status_off) 147 { 148 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 149 signed long timeout = 3000000; /* 3000 ms */ 150 struct amdgpu_device *adev = mes->adev; 151 struct amdgpu_ring *ring = &mes->ring[0]; 152 struct MES_API_STATUS *api_status; 153 union MESAPI__MISC *x_pkt = pkt; 154 const char *op_str, *misc_op_str; 155 unsigned long flags; 156 u64 status_gpu_addr; 157 u32 seq, status_offset; 158 u64 *status_ptr; 159 signed long r; 160 int ret; 161 162 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 163 return -EINVAL; 164 165 if (amdgpu_emu_mode) { 166 timeout *= 100; 167 } else if (amdgpu_sriov_vf(adev)) { 168 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 169 timeout = 15 * 600 * 1000; 170 } 171 172 ret = amdgpu_device_wb_get(adev, &status_offset); 173 if (ret) 174 return ret; 175 176 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 177 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 178 *status_ptr = 0; 179 180 spin_lock_irqsave(&mes->ring_lock[0], flags); 181 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 182 if (r) 183 goto error_unlock_free; 184 185 seq = ++ring->fence_drv.sync_seq; 186 r = amdgpu_fence_wait_polling(ring, 187 seq - ring->fence_drv.num_fences_mask, 188 timeout); 189 if (r < 1) 190 goto error_undo; 191 192 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 193 api_status->api_completion_fence_addr = status_gpu_addr; 194 api_status->api_completion_fence_value = 1; 195 196 amdgpu_ring_write_multiple(ring, pkt, size / 4); 197 198 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 199 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 200 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 201 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 202 mes_status_pkt.api_status.api_completion_fence_addr = 203 ring->fence_drv.gpu_addr; 204 mes_status_pkt.api_status.api_completion_fence_value = seq; 205 206 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 207 sizeof(mes_status_pkt) / 4); 208 209 amdgpu_ring_commit(ring); 210 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 211 212 op_str = mes_v12_0_get_op_string(x_pkt); 213 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 214 215 if (misc_op_str) 216 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 217 misc_op_str); 218 else if (op_str) 219 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 220 else 221 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 222 x_pkt->header.opcode); 223 224 r = amdgpu_fence_wait_polling(ring, seq, timeout); 225 if (r < 1 || !*status_ptr) { 226 227 if (misc_op_str) 228 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 229 op_str, misc_op_str); 230 else if (op_str) 231 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 232 op_str); 233 else 234 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 235 x_pkt->header.opcode); 236 237 while (halt_if_hws_hang) 238 schedule(); 239 240 r = -ETIMEDOUT; 241 goto error_wb_free; 242 } 243 244 amdgpu_device_wb_free(adev, status_offset); 245 return 0; 246 247 error_undo: 248 dev_err(adev->dev, "MES ring buffer is full.\n"); 249 amdgpu_ring_undo(ring); 250 251 error_unlock_free: 252 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 253 254 error_wb_free: 255 amdgpu_device_wb_free(adev, status_offset); 256 return r; 257 } 258 259 static int convert_to_mes_queue_type(int queue_type) 260 { 261 if (queue_type == AMDGPU_RING_TYPE_GFX) 262 return MES_QUEUE_TYPE_GFX; 263 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 264 return MES_QUEUE_TYPE_COMPUTE; 265 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 266 return MES_QUEUE_TYPE_SDMA; 267 else 268 BUG(); 269 return -1; 270 } 271 272 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 273 struct mes_add_queue_input *input) 274 { 275 struct amdgpu_device *adev = mes->adev; 276 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 277 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 278 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 279 280 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 281 282 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 283 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 284 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 285 286 mes_add_queue_pkt.process_id = input->process_id; 287 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 288 mes_add_queue_pkt.process_va_start = input->process_va_start; 289 mes_add_queue_pkt.process_va_end = input->process_va_end; 290 mes_add_queue_pkt.process_quantum = input->process_quantum; 291 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 292 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 293 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 294 mes_add_queue_pkt.inprocess_gang_priority = 295 input->inprocess_gang_priority; 296 mes_add_queue_pkt.gang_global_priority_level = 297 input->gang_global_priority_level; 298 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 299 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 300 301 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 302 303 mes_add_queue_pkt.queue_type = 304 convert_to_mes_queue_type(input->queue_type); 305 mes_add_queue_pkt.paging = input->paging; 306 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 307 mes_add_queue_pkt.gws_base = input->gws_base; 308 mes_add_queue_pkt.gws_size = input->gws_size; 309 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 310 mes_add_queue_pkt.tma_addr = input->tma_addr; 311 mes_add_queue_pkt.trap_en = input->trap_en; 312 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 313 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 314 315 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 316 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 317 mes_add_queue_pkt.gds_size = input->queue_size; 318 319 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 320 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 321 mes_add_queue_pkt.gds_size = input->queue_size; 322 323 return mes_v12_0_submit_pkt_and_poll_completion(mes, 324 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 325 offsetof(union MESAPI__ADD_QUEUE, api_status)); 326 } 327 328 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 329 struct mes_remove_queue_input *input) 330 { 331 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 332 333 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 334 335 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 336 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 337 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 338 339 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 340 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 341 342 return mes_v12_0_submit_pkt_and_poll_completion(mes, 343 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 344 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 345 } 346 347 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 348 struct mes_map_legacy_queue_input *input) 349 { 350 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 351 352 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 353 354 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 355 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 356 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 357 358 mes_add_queue_pkt.pipe_id = input->pipe_id; 359 mes_add_queue_pkt.queue_id = input->queue_id; 360 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 361 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 362 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 363 mes_add_queue_pkt.queue_type = 364 convert_to_mes_queue_type(input->queue_type); 365 mes_add_queue_pkt.map_legacy_kq = 1; 366 367 return mes_v12_0_submit_pkt_and_poll_completion(mes, 368 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 369 offsetof(union MESAPI__ADD_QUEUE, api_status)); 370 } 371 372 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 373 struct mes_unmap_legacy_queue_input *input) 374 { 375 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 376 377 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 378 379 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 380 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 381 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 382 383 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 384 mes_remove_queue_pkt.gang_context_addr = 0; 385 386 mes_remove_queue_pkt.pipe_id = input->pipe_id; 387 mes_remove_queue_pkt.queue_id = input->queue_id; 388 389 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 390 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 391 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 392 mes_remove_queue_pkt.tf_data = 393 lower_32_bits(input->trail_fence_data); 394 } else { 395 mes_remove_queue_pkt.unmap_legacy_queue = 1; 396 mes_remove_queue_pkt.queue_type = 397 convert_to_mes_queue_type(input->queue_type); 398 } 399 400 return mes_v12_0_submit_pkt_and_poll_completion(mes, 401 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 402 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 403 } 404 405 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 406 struct mes_suspend_gang_input *input) 407 { 408 return 0; 409 } 410 411 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 412 struct mes_resume_gang_input *input) 413 { 414 return 0; 415 } 416 417 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes) 418 { 419 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 420 421 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 422 423 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 424 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 425 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 426 427 return mes_v12_0_submit_pkt_and_poll_completion(mes, 428 &mes_status_pkt, sizeof(mes_status_pkt), 429 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 430 } 431 432 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 433 struct mes_misc_op_input *input) 434 { 435 union MESAPI__MISC misc_pkt; 436 437 memset(&misc_pkt, 0, sizeof(misc_pkt)); 438 439 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 440 misc_pkt.header.opcode = MES_SCH_API_MISC; 441 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 442 443 switch (input->op) { 444 case MES_MISC_OP_READ_REG: 445 misc_pkt.opcode = MESAPI_MISC__READ_REG; 446 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 447 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 448 break; 449 case MES_MISC_OP_WRITE_REG: 450 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 451 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 452 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 453 break; 454 case MES_MISC_OP_WRM_REG_WAIT: 455 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 456 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 457 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 458 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 459 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 460 misc_pkt.wait_reg_mem.reg_offset2 = 0; 461 break; 462 case MES_MISC_OP_WRM_REG_WR_WAIT: 463 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 464 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 465 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 466 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 467 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 468 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 469 break; 470 case MES_MISC_OP_SET_SHADER_DEBUGGER: 471 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 472 misc_pkt.set_shader_debugger.process_context_addr = 473 input->set_shader_debugger.process_context_addr; 474 misc_pkt.set_shader_debugger.flags.u32all = 475 input->set_shader_debugger.flags.u32all; 476 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 477 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 478 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 479 input->set_shader_debugger.tcp_watch_cntl, 480 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 481 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 482 break; 483 default: 484 DRM_ERROR("unsupported misc op (%d) \n", input->op); 485 return -EINVAL; 486 } 487 488 return mes_v12_0_submit_pkt_and_poll_completion(mes, 489 &misc_pkt, sizeof(misc_pkt), 490 offsetof(union MESAPI__MISC, api_status)); 491 } 492 493 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes) 494 { 495 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 496 497 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 498 499 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 500 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 501 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 502 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; 503 504 return mes_v12_0_submit_pkt_and_poll_completion(mes, 505 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 506 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 507 } 508 509 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) 510 { 511 int i; 512 struct amdgpu_device *adev = mes->adev; 513 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 514 515 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 516 517 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 518 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 519 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 520 521 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 522 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 523 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 524 mes_set_hw_res_pkt.paging_vmid = 0; 525 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 526 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 527 mes->query_status_fence_gpu_addr; 528 529 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 530 mes_set_hw_res_pkt.compute_hqd_mask[i] = 531 mes->compute_hqd_mask[i]; 532 533 for (i = 0; i < MAX_GFX_PIPES; i++) 534 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 535 536 for (i = 0; i < MAX_SDMA_PIPES; i++) 537 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 538 539 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 540 mes_set_hw_res_pkt.aggregated_doorbells[i] = 541 mes->aggregated_doorbells[i]; 542 543 for (i = 0; i < 5; i++) { 544 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 545 mes_set_hw_res_pkt.mmhub_base[i] = 546 adev->reg_offset[MMHUB_HWIP][0][i]; 547 mes_set_hw_res_pkt.osssys_base[i] = 548 adev->reg_offset[OSSSYS_HWIP][0][i]; 549 } 550 551 mes_set_hw_res_pkt.disable_reset = 1; 552 mes_set_hw_res_pkt.disable_mes_log = 1; 553 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 554 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 555 556 /* 557 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 558 * handling support, other queue will not use the oversubscribe timer. 559 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 560 */ 561 mes_set_hw_res_pkt.oversubscription_timer = 50; 562 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 563 564 if (amdgpu_mes_log_enable) { 565 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 566 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 567 } 568 569 return mes_v12_0_submit_pkt_and_poll_completion(mes, 570 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 571 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 572 } 573 574 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 575 { 576 struct amdgpu_device *adev = mes->adev; 577 uint32_t data; 578 579 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 580 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 581 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 582 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 583 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 584 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 585 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 586 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 587 588 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 589 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 590 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 591 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 592 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 593 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 594 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 595 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 596 597 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 598 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 599 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 600 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 601 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 602 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 603 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 604 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 605 606 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 607 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 608 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 609 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 610 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 611 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 612 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 613 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 614 615 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 616 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 617 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 618 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 619 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 620 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 621 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 622 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 623 624 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 625 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 626 } 627 628 629 static void mes_v12_0_enable_unmapped_doorbell_handling( 630 struct amdgpu_mes *mes, bool enable) 631 { 632 struct amdgpu_device *adev = mes->adev; 633 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 634 635 /* 636 * The default PROC_LSB settng is 0xc which means doorbell 637 * addr[16:12] gives the doorbell page number. For kfd, each 638 * process will use 2 pages of doorbell, we need to change the 639 * setting to 0xd 640 */ 641 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 642 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 643 644 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 645 646 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 647 } 648 649 static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes, 650 struct mes_reset_legacy_queue_input *input) 651 { 652 union MESAPI__RESET mes_reset_queue_pkt; 653 654 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 655 656 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 657 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 658 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 659 660 mes_reset_queue_pkt.queue_type = 661 convert_to_mes_queue_type(input->queue_type); 662 663 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 664 mes_reset_queue_pkt.reset_legacy_gfx = 1; 665 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 666 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 667 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 668 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 669 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 670 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 671 } else { 672 mes_reset_queue_pkt.reset_queue_only = 1; 673 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 674 } 675 676 return mes_v12_0_submit_pkt_and_poll_completion(mes, 677 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 678 offsetof(union MESAPI__RESET, api_status)); 679 } 680 681 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 682 .add_hw_queue = mes_v12_0_add_hw_queue, 683 .remove_hw_queue = mes_v12_0_remove_hw_queue, 684 .map_legacy_queue = mes_v12_0_map_legacy_queue, 685 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 686 .suspend_gang = mes_v12_0_suspend_gang, 687 .resume_gang = mes_v12_0_resume_gang, 688 .misc_op = mes_v12_0_misc_op, 689 .reset_legacy_queue = mes_v12_0_reset_legacy_queue, 690 }; 691 692 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 693 enum admgpu_mes_pipe pipe) 694 { 695 int r; 696 const struct mes_firmware_header_v1_0 *mes_hdr; 697 const __le32 *fw_data; 698 unsigned fw_size; 699 700 mes_hdr = (const struct mes_firmware_header_v1_0 *) 701 adev->mes.fw[pipe]->data; 702 703 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 704 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 705 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 706 707 r = amdgpu_bo_create_reserved(adev, fw_size, 708 PAGE_SIZE, 709 AMDGPU_GEM_DOMAIN_VRAM, 710 &adev->mes.ucode_fw_obj[pipe], 711 &adev->mes.ucode_fw_gpu_addr[pipe], 712 (void **)&adev->mes.ucode_fw_ptr[pipe]); 713 if (r) { 714 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 715 return r; 716 } 717 718 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 719 720 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 721 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 722 723 return 0; 724 } 725 726 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 727 enum admgpu_mes_pipe pipe) 728 { 729 int r; 730 const struct mes_firmware_header_v1_0 *mes_hdr; 731 const __le32 *fw_data; 732 unsigned fw_size; 733 734 mes_hdr = (const struct mes_firmware_header_v1_0 *) 735 adev->mes.fw[pipe]->data; 736 737 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 738 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 739 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 740 741 r = amdgpu_bo_create_reserved(adev, fw_size, 742 64 * 1024, 743 AMDGPU_GEM_DOMAIN_VRAM, 744 &adev->mes.data_fw_obj[pipe], 745 &adev->mes.data_fw_gpu_addr[pipe], 746 (void **)&adev->mes.data_fw_ptr[pipe]); 747 if (r) { 748 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 749 return r; 750 } 751 752 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 753 754 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 755 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 756 757 return 0; 758 } 759 760 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 761 enum admgpu_mes_pipe pipe) 762 { 763 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 764 &adev->mes.data_fw_gpu_addr[pipe], 765 (void **)&adev->mes.data_fw_ptr[pipe]); 766 767 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 768 &adev->mes.ucode_fw_gpu_addr[pipe], 769 (void **)&adev->mes.ucode_fw_ptr[pipe]); 770 } 771 772 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 773 { 774 uint64_t ucode_addr; 775 uint32_t pipe, data = 0; 776 777 if (enable) { 778 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 779 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 780 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 781 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 782 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 783 784 mutex_lock(&adev->srbm_mutex); 785 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 786 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 787 pipe == AMDGPU_MES_KIQ_PIPE) 788 continue; 789 790 soc21_grbm_select(adev, 3, pipe, 0, 0); 791 792 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 793 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 794 lower_32_bits(ucode_addr)); 795 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 796 upper_32_bits(ucode_addr)); 797 } 798 soc21_grbm_select(adev, 0, 0, 0, 0); 799 mutex_unlock(&adev->srbm_mutex); 800 801 /* unhalt MES and activate pipe0 */ 802 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 803 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 804 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 805 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 806 807 if (amdgpu_emu_mode) 808 msleep(100); 809 else if (adev->enable_uni_mes) 810 udelay(500); 811 else 812 udelay(50); 813 } else { 814 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 815 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 816 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 817 data = REG_SET_FIELD(data, CP_MES_CNTL, 818 MES_INVALIDATE_ICACHE, 1); 819 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 820 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 821 (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0); 822 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 823 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 824 } 825 } 826 827 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 828 { 829 uint64_t ucode_addr; 830 int pipe; 831 832 mes_v12_0_enable(adev, false); 833 834 mutex_lock(&adev->srbm_mutex); 835 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 836 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) && 837 pipe == AMDGPU_MES_KIQ_PIPE) 838 continue; 839 840 /* me=3, queue=0 */ 841 soc21_grbm_select(adev, 3, pipe, 0, 0); 842 843 /* set ucode start address */ 844 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 845 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 846 lower_32_bits(ucode_addr)); 847 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 848 upper_32_bits(ucode_addr)); 849 850 soc21_grbm_select(adev, 0, 0, 0, 0); 851 } 852 mutex_unlock(&adev->srbm_mutex); 853 } 854 855 /* This function is for backdoor MES firmware */ 856 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 857 enum admgpu_mes_pipe pipe, bool prime_icache) 858 { 859 int r; 860 uint32_t data; 861 862 mes_v12_0_enable(adev, false); 863 864 if (!adev->mes.fw[pipe]) 865 return -EINVAL; 866 867 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 868 if (r) 869 return r; 870 871 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 872 if (r) { 873 mes_v12_0_free_ucode_buffers(adev, pipe); 874 return r; 875 } 876 877 mutex_lock(&adev->srbm_mutex); 878 /* me=3, pipe=0, queue=0 */ 879 soc21_grbm_select(adev, 3, pipe, 0, 0); 880 881 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 882 883 /* set ucode fimrware address */ 884 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 885 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 886 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 887 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 888 889 /* set ucode instruction cache boundary to 2M-1 */ 890 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 891 892 /* set ucode data firmware address */ 893 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 894 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 895 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 896 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 897 898 /* Set data cache boundary CP_MES_MDBOUND_LO */ 899 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 900 901 if (prime_icache) { 902 /* invalidate ICACHE */ 903 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 904 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 905 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 906 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 907 908 /* prime the ICACHE. */ 909 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 910 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 911 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 912 } 913 914 soc21_grbm_select(adev, 0, 0, 0, 0); 915 mutex_unlock(&adev->srbm_mutex); 916 917 return 0; 918 } 919 920 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 921 enum admgpu_mes_pipe pipe) 922 { 923 int r; 924 u32 *eop; 925 926 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 927 AMDGPU_GEM_DOMAIN_GTT, 928 &adev->mes.eop_gpu_obj[pipe], 929 &adev->mes.eop_gpu_addr[pipe], 930 (void **)&eop); 931 if (r) { 932 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 933 return r; 934 } 935 936 memset(eop, 0, 937 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 938 939 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 940 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 941 942 return 0; 943 } 944 945 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 946 { 947 struct v12_compute_mqd *mqd = ring->mqd_ptr; 948 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 949 uint32_t tmp; 950 951 mqd->header = 0xC0310800; 952 mqd->compute_pipelinestat_enable = 0x00000001; 953 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 954 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 955 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 956 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 957 mqd->compute_misc_reserved = 0x00000007; 958 959 eop_base_addr = ring->eop_gpu_addr >> 8; 960 961 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 962 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 963 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 964 (order_base_2(MES_EOP_SIZE / 4) - 1)); 965 966 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 967 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 968 mqd->cp_hqd_eop_control = tmp; 969 970 /* disable the queue if it's active */ 971 ring->wptr = 0; 972 mqd->cp_hqd_pq_rptr = 0; 973 mqd->cp_hqd_pq_wptr_lo = 0; 974 mqd->cp_hqd_pq_wptr_hi = 0; 975 976 /* set the pointer to the MQD */ 977 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 978 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 979 980 /* set MQD vmid to 0 */ 981 tmp = regCP_MQD_CONTROL_DEFAULT; 982 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 983 mqd->cp_mqd_control = tmp; 984 985 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 986 hqd_gpu_addr = ring->gpu_addr >> 8; 987 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 988 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 989 990 /* set the wb address whether it's enabled or not */ 991 wb_gpu_addr = ring->rptr_gpu_addr; 992 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 993 mqd->cp_hqd_pq_rptr_report_addr_hi = 994 upper_32_bits(wb_gpu_addr) & 0xffff; 995 996 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 997 wb_gpu_addr = ring->wptr_gpu_addr; 998 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 999 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1000 1001 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1002 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1003 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1004 (order_base_2(ring->ring_size / 4) - 1)); 1005 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1006 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1007 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1008 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1009 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1010 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1011 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1012 mqd->cp_hqd_pq_control = tmp; 1013 1014 /* enable doorbell */ 1015 tmp = 0; 1016 if (ring->use_doorbell) { 1017 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1018 DOORBELL_OFFSET, ring->doorbell_index); 1019 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1020 DOORBELL_EN, 1); 1021 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1022 DOORBELL_SOURCE, 0); 1023 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1024 DOORBELL_HIT, 0); 1025 } else { 1026 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1027 DOORBELL_EN, 0); 1028 } 1029 mqd->cp_hqd_pq_doorbell_control = tmp; 1030 1031 mqd->cp_hqd_vmid = 0; 1032 /* activate the queue */ 1033 mqd->cp_hqd_active = 1; 1034 1035 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1036 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1037 PRELOAD_SIZE, 0x55); 1038 mqd->cp_hqd_persistent_state = tmp; 1039 1040 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1041 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1042 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1043 1044 /* 1045 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1046 * doorbell handling. This is a reserved CP internal register can 1047 * not be accesss by others 1048 */ 1049 mqd->reserved_184 = BIT(15); 1050 1051 return 0; 1052 } 1053 1054 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1055 { 1056 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1057 struct amdgpu_device *adev = ring->adev; 1058 uint32_t data = 0; 1059 1060 mutex_lock(&adev->srbm_mutex); 1061 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1062 1063 /* set CP_HQD_VMID.VMID = 0. */ 1064 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1065 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1066 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1067 1068 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1069 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1070 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1071 DOORBELL_EN, 0); 1072 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1073 1074 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1075 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1076 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1077 1078 /* set CP_MQD_CONTROL.VMID=0 */ 1079 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1080 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1081 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1082 1083 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1084 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1085 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1086 1087 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1088 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1089 mqd->cp_hqd_pq_rptr_report_addr_lo); 1090 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1091 mqd->cp_hqd_pq_rptr_report_addr_hi); 1092 1093 /* set CP_HQD_PQ_CONTROL */ 1094 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1095 1096 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1097 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1098 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1099 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1100 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1101 1102 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1103 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1104 mqd->cp_hqd_pq_doorbell_control); 1105 1106 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1107 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1108 1109 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1110 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1111 1112 soc21_grbm_select(adev, 0, 0, 0, 0); 1113 mutex_unlock(&adev->srbm_mutex); 1114 } 1115 1116 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1117 { 1118 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1119 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1120 int r; 1121 1122 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1123 return -EINVAL; 1124 1125 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1126 if (r) { 1127 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1128 return r; 1129 } 1130 1131 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1132 1133 r = amdgpu_ring_test_ring(kiq_ring); 1134 if (r) { 1135 DRM_ERROR("kfq enable failed\n"); 1136 kiq_ring->sched.ready = false; 1137 } 1138 return r; 1139 } 1140 1141 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1142 enum admgpu_mes_pipe pipe) 1143 { 1144 struct amdgpu_ring *ring; 1145 int r; 1146 1147 if (pipe == AMDGPU_MES_KIQ_PIPE) 1148 ring = &adev->gfx.kiq[0].ring; 1149 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1150 ring = &adev->mes.ring[0]; 1151 else 1152 BUG(); 1153 1154 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1155 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1156 *(ring->wptr_cpu_addr) = 0; 1157 *(ring->rptr_cpu_addr) = 0; 1158 amdgpu_ring_clear_ring(ring); 1159 } 1160 1161 r = mes_v12_0_mqd_init(ring); 1162 if (r) 1163 return r; 1164 1165 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1166 if (adev->enable_uni_mes) { 1167 mes_v12_0_queue_init_register(ring); 1168 } else { 1169 r = mes_v12_0_kiq_enable_queue(adev); 1170 if (r) 1171 return r; 1172 } 1173 } else { 1174 mes_v12_0_queue_init_register(ring); 1175 } 1176 1177 /* get MES scheduler/KIQ versions */ 1178 mutex_lock(&adev->srbm_mutex); 1179 soc21_grbm_select(adev, 3, pipe, 0, 0); 1180 1181 if (pipe == AMDGPU_MES_SCHED_PIPE) 1182 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1183 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1184 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1185 1186 soc21_grbm_select(adev, 0, 0, 0, 0); 1187 mutex_unlock(&adev->srbm_mutex); 1188 1189 return 0; 1190 } 1191 1192 static int mes_v12_0_ring_init(struct amdgpu_device *adev) 1193 { 1194 struct amdgpu_ring *ring; 1195 1196 ring = &adev->mes.ring[0]; 1197 1198 ring->funcs = &mes_v12_0_ring_funcs; 1199 1200 ring->me = 3; 1201 ring->pipe = 0; 1202 ring->queue = 0; 1203 1204 ring->ring_obj = NULL; 1205 ring->use_doorbell = true; 1206 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1207 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1208 ring->no_scheduler = true; 1209 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1210 1211 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1212 AMDGPU_RING_PRIO_DEFAULT, NULL); 1213 } 1214 1215 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1216 { 1217 struct amdgpu_ring *ring; 1218 1219 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1220 1221 ring = &adev->gfx.kiq[0].ring; 1222 1223 ring->me = 3; 1224 ring->pipe = adev->enable_uni_mes ? 0 : 1; 1225 ring->queue = 0; 1226 1227 ring->adev = NULL; 1228 ring->ring_obj = NULL; 1229 ring->use_doorbell = true; 1230 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1231 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1232 ring->no_scheduler = true; 1233 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1234 ring->me, ring->pipe, ring->queue); 1235 1236 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1237 AMDGPU_RING_PRIO_DEFAULT, NULL); 1238 } 1239 1240 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1241 enum admgpu_mes_pipe pipe) 1242 { 1243 int r, mqd_size = sizeof(struct v12_compute_mqd); 1244 struct amdgpu_ring *ring; 1245 1246 if (pipe == AMDGPU_MES_KIQ_PIPE) 1247 ring = &adev->gfx.kiq[0].ring; 1248 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1249 ring = &adev->mes.ring[0]; 1250 else 1251 BUG(); 1252 1253 if (ring->mqd_obj) 1254 return 0; 1255 1256 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1257 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1258 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1259 if (r) { 1260 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1261 return r; 1262 } 1263 1264 memset(ring->mqd_ptr, 0, mqd_size); 1265 1266 /* prepare MQD backup */ 1267 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1268 if (!adev->mes.mqd_backup[pipe]) 1269 dev_warn(adev->dev, 1270 "no memory to create MQD backup for ring %s\n", 1271 ring->name); 1272 1273 return 0; 1274 } 1275 1276 static int mes_v12_0_sw_init(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 int pipe, r; 1280 1281 adev->mes.funcs = &mes_v12_0_funcs; 1282 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1283 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1284 1285 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; 1286 1287 r = amdgpu_mes_init(adev); 1288 if (r) 1289 return r; 1290 1291 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1292 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1293 continue; 1294 1295 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1296 if (r) 1297 return r; 1298 1299 r = mes_v12_0_mqd_sw_init(adev, pipe); 1300 if (r) 1301 return r; 1302 } 1303 1304 if (adev->enable_mes_kiq) { 1305 r = mes_v12_0_kiq_ring_init(adev); 1306 if (r) 1307 return r; 1308 } 1309 1310 r = mes_v12_0_ring_init(adev); 1311 if (r) 1312 return r; 1313 1314 return 0; 1315 } 1316 1317 static int mes_v12_0_sw_fini(void *handle) 1318 { 1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1320 int pipe; 1321 1322 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1323 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1324 1325 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1326 kfree(adev->mes.mqd_backup[pipe]); 1327 1328 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1329 &adev->mes.eop_gpu_addr[pipe], 1330 NULL); 1331 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1332 } 1333 1334 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1335 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1336 &adev->gfx.kiq[0].ring.mqd_ptr); 1337 1338 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1339 &adev->mes.ring[0].mqd_gpu_addr, 1340 &adev->mes.ring[0].mqd_ptr); 1341 1342 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1343 amdgpu_ring_fini(&adev->mes.ring[0]); 1344 1345 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1346 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1347 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1348 } 1349 1350 amdgpu_mes_fini(adev); 1351 return 0; 1352 } 1353 1354 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1355 { 1356 uint32_t data; 1357 int i; 1358 1359 mutex_lock(&adev->srbm_mutex); 1360 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1361 1362 /* disable the queue if it's active */ 1363 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1364 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1365 for (i = 0; i < adev->usec_timeout; i++) { 1366 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1367 break; 1368 udelay(1); 1369 } 1370 } 1371 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1372 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1373 DOORBELL_EN, 0); 1374 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1375 DOORBELL_HIT, 1); 1376 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1377 1378 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1379 1380 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1381 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1382 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1383 1384 soc21_grbm_select(adev, 0, 0, 0, 0); 1385 mutex_unlock(&adev->srbm_mutex); 1386 1387 adev->mes.ring[0].sched.ready = false; 1388 } 1389 1390 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1391 { 1392 uint32_t tmp; 1393 struct amdgpu_device *adev = ring->adev; 1394 1395 /* tell RLC which is KIQ queue */ 1396 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1397 tmp &= 0xffffff00; 1398 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1399 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1400 tmp |= 0x80; 1401 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1402 } 1403 1404 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1405 { 1406 int r = 0; 1407 1408 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1409 1410 if (adev->enable_uni_mes) 1411 return mes_v12_0_hw_init(adev); 1412 1413 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1414 1415 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1416 if (r) { 1417 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1418 return r; 1419 } 1420 1421 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1422 if (r) { 1423 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1424 return r; 1425 } 1426 1427 mes_v12_0_set_ucode_start_addr(adev); 1428 1429 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1430 mes_v12_0_set_ucode_start_addr(adev); 1431 1432 mes_v12_0_enable(adev, true); 1433 1434 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1435 if (r) 1436 goto failure; 1437 1438 r = mes_v12_0_hw_init(adev); 1439 if (r) 1440 goto failure; 1441 1442 return r; 1443 1444 failure: 1445 mes_v12_0_hw_fini(adev); 1446 return r; 1447 } 1448 1449 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1450 { 1451 if (adev->mes.ring[0].sched.ready) { 1452 mes_v12_0_kiq_dequeue_sched(adev); 1453 adev->mes.ring[0].sched.ready = false; 1454 } 1455 1456 mes_v12_0_enable(adev, false); 1457 1458 return 0; 1459 } 1460 1461 static int mes_v12_0_hw_init(void *handle) 1462 { 1463 int r; 1464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1465 1466 if (adev->mes.ring[0].sched.ready) 1467 goto out; 1468 1469 if (!adev->enable_mes_kiq || adev->enable_uni_mes) { 1470 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1471 r = mes_v12_0_load_microcode(adev, 1472 AMDGPU_MES_SCHED_PIPE, true); 1473 if (r) { 1474 DRM_ERROR("failed to MES fw, r=%d\n", r); 1475 return r; 1476 } 1477 1478 mes_v12_0_set_ucode_start_addr(adev); 1479 1480 } else if (adev->firmware.load_type == 1481 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1482 1483 mes_v12_0_set_ucode_start_addr(adev); 1484 } 1485 1486 mes_v12_0_enable(adev, true); 1487 } 1488 1489 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1490 if (r) 1491 goto failure; 1492 1493 r = mes_v12_0_set_hw_resources(&adev->mes); 1494 if (r) 1495 goto failure; 1496 1497 if (adev->enable_uni_mes) 1498 mes_v12_0_set_hw_resources_1(&adev->mes); 1499 1500 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1501 1502 /* Enable the MES to handle doorbell ring on unmapped queue */ 1503 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1504 1505 r = mes_v12_0_query_sched_status(&adev->mes); 1506 if (r) { 1507 DRM_ERROR("MES is busy\n"); 1508 goto failure; 1509 } 1510 1511 out: 1512 /* 1513 * Disable KIQ ring usage from the driver once MES is enabled. 1514 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1515 * with MES enabled. 1516 */ 1517 adev->gfx.kiq[0].ring.sched.ready = false; 1518 adev->mes.ring[0].sched.ready = true; 1519 1520 return 0; 1521 1522 failure: 1523 mes_v12_0_hw_fini(adev); 1524 return r; 1525 } 1526 1527 static int mes_v12_0_hw_fini(void *handle) 1528 { 1529 return 0; 1530 } 1531 1532 static int mes_v12_0_suspend(void *handle) 1533 { 1534 int r; 1535 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1536 1537 r = amdgpu_mes_suspend(adev); 1538 if (r) 1539 return r; 1540 1541 return mes_v12_0_hw_fini(adev); 1542 } 1543 1544 static int mes_v12_0_resume(void *handle) 1545 { 1546 int r; 1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1548 1549 r = mes_v12_0_hw_init(adev); 1550 if (r) 1551 return r; 1552 1553 return amdgpu_mes_resume(adev); 1554 } 1555 1556 static int mes_v12_0_early_init(void *handle) 1557 { 1558 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1559 int pipe, r; 1560 1561 if (adev->enable_uni_mes) { 1562 r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1563 if (!r) 1564 return 0; 1565 1566 adev->enable_uni_mes = false; 1567 } 1568 1569 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1570 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1571 continue; 1572 r = amdgpu_mes_init_microcode(adev, pipe); 1573 if (r) 1574 return r; 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int mes_v12_0_late_init(void *handle) 1581 { 1582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1583 1584 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1585 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) 1586 amdgpu_mes_self_test(adev); 1587 1588 return 0; 1589 } 1590 1591 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1592 .name = "mes_v12_0", 1593 .early_init = mes_v12_0_early_init, 1594 .late_init = mes_v12_0_late_init, 1595 .sw_init = mes_v12_0_sw_init, 1596 .sw_fini = mes_v12_0_sw_fini, 1597 .hw_init = mes_v12_0_hw_init, 1598 .hw_fini = mes_v12_0_hw_fini, 1599 .suspend = mes_v12_0_suspend, 1600 .resume = mes_v12_0_resume, 1601 }; 1602 1603 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1604 .type = AMD_IP_BLOCK_TYPE_MES, 1605 .major = 12, 1606 .minor = 0, 1607 .rev = 0, 1608 .funcs = &mes_v12_0_ip_funcs, 1609 }; 1610