1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "gfx_v12_0.h" 28 #include "soc15_common.h" 29 #include "soc21.h" 30 #include "gc/gc_12_0_0_offset.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v12_structs.h" 34 #include "mes_v12_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 42 43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); 45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 47 48 #define MES_EOP_SIZE 2048 49 50 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ 51 #define MES12_HUNG_HQD_INFO_OFFSET 4 52 53 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 54 { 55 struct amdgpu_device *adev = ring->adev; 56 57 if (ring->use_doorbell) { 58 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 59 ring->wptr); 60 WDOORBELL64(ring->doorbell_index, ring->wptr); 61 } else { 62 BUG(); 63 } 64 } 65 66 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 67 { 68 return *ring->rptr_cpu_addr; 69 } 70 71 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 72 { 73 u64 wptr; 74 75 if (ring->use_doorbell) 76 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 77 else 78 BUG(); 79 return wptr; 80 } 81 82 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 83 .type = AMDGPU_RING_TYPE_MES, 84 .align_mask = 1, 85 .nop = 0, 86 .support_64bit_ptrs = true, 87 .get_rptr = mes_v12_0_ring_get_rptr, 88 .get_wptr = mes_v12_0_ring_get_wptr, 89 .set_wptr = mes_v12_0_ring_set_wptr, 90 .insert_nop = amdgpu_ring_insert_nop, 91 }; 92 93 static const char *mes_v12_0_opcodes[] = { 94 "SET_HW_RSRC", 95 "SET_SCHEDULING_CONFIG", 96 "ADD_QUEUE", 97 "REMOVE_QUEUE", 98 "PERFORM_YIELD", 99 "SET_GANG_PRIORITY_LEVEL", 100 "SUSPEND", 101 "RESUME", 102 "RESET", 103 "SET_LOG_BUFFER", 104 "CHANGE_GANG_PRORITY", 105 "QUERY_SCHEDULER_STATUS", 106 "unused", 107 "SET_DEBUG_VMID", 108 "MISC", 109 "UPDATE_ROOT_PAGE_TABLE", 110 "AMD_LOG", 111 "SET_SE_MODE", 112 "SET_GANG_SUBMIT", 113 "SET_HW_RSRC_1", 114 "INVALIDATE_TLBS", 115 }; 116 117 static const char *mes_v12_0_misc_opcodes[] = { 118 "WRITE_REG", 119 "INV_GART", 120 "QUERY_STATUS", 121 "READ_REG", 122 "WAIT_REG_MEM", 123 "SET_SHADER_DEBUGGER", 124 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 125 "NOTIFY_TO_UNMAP_PROCESSES", 126 }; 127 128 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 129 { 130 const char *op_str = NULL; 131 132 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 133 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 134 135 return op_str; 136 } 137 138 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 139 { 140 const char *op_str = NULL; 141 142 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 143 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 144 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 145 146 return op_str; 147 } 148 149 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 150 int pipe, void *pkt, int size, 151 int api_status_off) 152 { 153 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 154 signed long timeout = 2100000; /* 2100 ms */ 155 struct amdgpu_device *adev = mes->adev; 156 struct amdgpu_ring *ring = &mes->ring[pipe]; 157 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 158 struct MES_API_STATUS *api_status; 159 union MESAPI__MISC *x_pkt = pkt; 160 const char *op_str, *misc_op_str; 161 unsigned long flags; 162 u64 status_gpu_addr; 163 u32 seq, status_offset; 164 u64 *status_ptr; 165 signed long r; 166 int ret; 167 168 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 169 return -EINVAL; 170 171 if (amdgpu_emu_mode) { 172 timeout *= 100; 173 } else if (amdgpu_sriov_vf(adev)) { 174 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 175 timeout = 15 * 600 * 1000; 176 } 177 178 ret = amdgpu_device_wb_get(adev, &status_offset); 179 if (ret) 180 return ret; 181 182 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 183 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 184 *status_ptr = 0; 185 186 spin_lock_irqsave(ring_lock, flags); 187 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 188 if (r) 189 goto error_unlock_free; 190 191 seq = ++ring->fence_drv.sync_seq; 192 r = amdgpu_fence_wait_polling(ring, 193 seq - ring->fence_drv.num_fences_mask, 194 timeout); 195 if (r < 1) 196 goto error_undo; 197 198 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 199 api_status->api_completion_fence_addr = status_gpu_addr; 200 api_status->api_completion_fence_value = 1; 201 202 amdgpu_ring_write_multiple(ring, pkt, size / 4); 203 204 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 205 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 206 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 207 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 208 mes_status_pkt.api_status.api_completion_fence_addr = 209 ring->fence_drv.gpu_addr; 210 mes_status_pkt.api_status.api_completion_fence_value = seq; 211 212 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 213 sizeof(mes_status_pkt) / 4); 214 215 amdgpu_ring_commit(ring); 216 spin_unlock_irqrestore(ring_lock, flags); 217 218 op_str = mes_v12_0_get_op_string(x_pkt); 219 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 220 221 if (misc_op_str) 222 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 223 pipe, op_str, misc_op_str); 224 else if (op_str) 225 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 226 pipe, op_str); 227 else 228 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 229 pipe, x_pkt->header.opcode); 230 231 r = amdgpu_fence_wait_polling(ring, seq, timeout); 232 233 /* 234 * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success). 235 * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information. 236 */ 237 if (r < 1 || !(lower_32_bits(*status_ptr))) { 238 239 if (misc_op_str) 240 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 241 pipe, op_str, misc_op_str); 242 else if (op_str) 243 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 244 pipe, op_str); 245 else 246 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 247 pipe, x_pkt->header.opcode); 248 249 while (halt_if_hws_hang) 250 schedule(); 251 252 r = -ETIMEDOUT; 253 goto error_wb_free; 254 } 255 256 amdgpu_device_wb_free(adev, status_offset); 257 return 0; 258 259 error_undo: 260 dev_err(adev->dev, "MES ring buffer is full.\n"); 261 amdgpu_ring_undo(ring); 262 263 error_unlock_free: 264 spin_unlock_irqrestore(ring_lock, flags); 265 266 error_wb_free: 267 amdgpu_device_wb_free(adev, status_offset); 268 return r; 269 } 270 271 static int convert_to_mes_queue_type(int queue_type) 272 { 273 if (queue_type == AMDGPU_RING_TYPE_GFX) 274 return MES_QUEUE_TYPE_GFX; 275 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 276 return MES_QUEUE_TYPE_COMPUTE; 277 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 278 return MES_QUEUE_TYPE_SDMA; 279 else if (queue_type == AMDGPU_RING_TYPE_MES) 280 return MES_QUEUE_TYPE_SCHQ; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int convert_to_mes_priority_level(int priority_level) 287 { 288 switch (priority_level) { 289 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 290 return AMD_PRIORITY_LEVEL_LOW; 291 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 292 default: 293 return AMD_PRIORITY_LEVEL_NORMAL; 294 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 295 return AMD_PRIORITY_LEVEL_MEDIUM; 296 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 297 return AMD_PRIORITY_LEVEL_HIGH; 298 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 299 return AMD_PRIORITY_LEVEL_REALTIME; 300 } 301 } 302 303 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 304 struct mes_add_queue_input *input) 305 { 306 struct amdgpu_device *adev = mes->adev; 307 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 308 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 309 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 310 311 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 312 313 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 314 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 315 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 316 317 mes_add_queue_pkt.process_id = input->process_id; 318 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 319 mes_add_queue_pkt.process_va_start = input->process_va_start; 320 mes_add_queue_pkt.process_va_end = input->process_va_end; 321 mes_add_queue_pkt.process_quantum = input->process_quantum; 322 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 323 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 324 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 325 mes_add_queue_pkt.inprocess_gang_priority = 326 convert_to_mes_priority_level(input->inprocess_gang_priority); 327 mes_add_queue_pkt.gang_global_priority_level = 328 convert_to_mes_priority_level(input->gang_global_priority_level); 329 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 330 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 331 332 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 333 334 mes_add_queue_pkt.queue_type = 335 convert_to_mes_queue_type(input->queue_type); 336 mes_add_queue_pkt.paging = input->paging; 337 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 338 mes_add_queue_pkt.gws_base = input->gws_base; 339 mes_add_queue_pkt.gws_size = input->gws_size; 340 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 341 mes_add_queue_pkt.tma_addr = input->tma_addr; 342 mes_add_queue_pkt.trap_en = input->trap_en; 343 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 344 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 345 346 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 347 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 348 mes_add_queue_pkt.gds_size = input->queue_size; 349 350 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 351 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 352 mes_add_queue_pkt.gds_size = input->queue_size; 353 354 return mes_v12_0_submit_pkt_and_poll_completion(mes, 355 AMDGPU_MES_SCHED_PIPE, 356 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 357 offsetof(union MESAPI__ADD_QUEUE, api_status)); 358 } 359 360 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 361 struct mes_remove_queue_input *input) 362 { 363 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 364 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 365 366 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 367 368 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 369 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 370 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 371 372 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 373 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 374 375 if (mes_rev >= 0x5a) 376 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 377 378 return mes_v12_0_submit_pkt_and_poll_completion(mes, 379 AMDGPU_MES_SCHED_PIPE, 380 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 381 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 382 } 383 384 int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev, 385 bool req) 386 { 387 u32 i, tmp, val; 388 389 for (i = 0; i < adev->usec_timeout; i++) { 390 /* Request with MeId=2, PipeId=0 */ 391 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 392 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 393 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 394 395 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 396 if (req) { 397 if (val == tmp) 398 break; 399 } else { 400 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 401 REQUEST, 1); 402 403 /* unlocked or locked by firmware */ 404 if (val != tmp) 405 break; 406 } 407 udelay(1); 408 } 409 410 if (i >= adev->usec_timeout) 411 return -EINVAL; 412 413 return 0; 414 } 415 416 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 417 uint32_t me_id, uint32_t pipe_id, 418 uint32_t queue_id, uint32_t vmid) 419 { 420 struct amdgpu_device *adev = mes->adev; 421 uint32_t value, reg; 422 int i, r = 0; 423 424 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 425 426 if (queue_type == AMDGPU_RING_TYPE_GFX) { 427 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 428 me_id, pipe_id, queue_id, vmid); 429 430 mutex_lock(&adev->gfx.reset_sem_mutex); 431 gfx_v12_0_request_gfx_index_mutex(adev, true); 432 /* all se allow writes */ 433 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 434 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 435 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 436 if (pipe_id == 0) 437 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 438 else 439 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 440 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 441 gfx_v12_0_request_gfx_index_mutex(adev, false); 442 mutex_unlock(&adev->gfx.reset_sem_mutex); 443 444 mutex_lock(&adev->srbm_mutex); 445 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 446 /* wait till dequeue take effects */ 447 for (i = 0; i < adev->usec_timeout; i++) { 448 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 449 break; 450 udelay(1); 451 } 452 if (i >= adev->usec_timeout) { 453 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 454 r = -ETIMEDOUT; 455 } 456 457 soc21_grbm_select(adev, 0, 0, 0, 0); 458 mutex_unlock(&adev->srbm_mutex); 459 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 460 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 461 me_id, pipe_id, queue_id); 462 mutex_lock(&adev->srbm_mutex); 463 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 464 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 465 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 466 467 /* wait till dequeue take effects */ 468 for (i = 0; i < adev->usec_timeout; i++) { 469 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 470 break; 471 udelay(1); 472 } 473 if (i >= adev->usec_timeout) { 474 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 475 r = -ETIMEDOUT; 476 } 477 soc21_grbm_select(adev, 0, 0, 0, 0); 478 mutex_unlock(&adev->srbm_mutex); 479 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 480 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 481 me_id, pipe_id, queue_id); 482 switch (me_id) { 483 case 1: 484 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 485 break; 486 case 0: 487 default: 488 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 489 break; 490 } 491 492 value = 1 << queue_id; 493 WREG32(reg, value); 494 /* wait for queue reset done */ 495 for (i = 0; i < adev->usec_timeout; i++) { 496 if (!(RREG32(reg) & value)) 497 break; 498 udelay(1); 499 } 500 if (i >= adev->usec_timeout) { 501 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 502 r = -ETIMEDOUT; 503 } 504 } 505 506 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 507 return r; 508 } 509 510 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 511 struct mes_map_legacy_queue_input *input) 512 { 513 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 514 int pipe; 515 516 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 517 518 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 519 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 520 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 521 522 mes_add_queue_pkt.pipe_id = input->pipe_id; 523 mes_add_queue_pkt.queue_id = input->queue_id; 524 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 525 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 526 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 527 mes_add_queue_pkt.queue_type = 528 convert_to_mes_queue_type(input->queue_type); 529 mes_add_queue_pkt.map_legacy_kq = 1; 530 531 if (mes->adev->enable_uni_mes) 532 pipe = AMDGPU_MES_KIQ_PIPE; 533 else 534 pipe = AMDGPU_MES_SCHED_PIPE; 535 536 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 537 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 538 offsetof(union MESAPI__ADD_QUEUE, api_status)); 539 } 540 541 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 542 struct mes_unmap_legacy_queue_input *input) 543 { 544 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 545 int pipe; 546 547 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 548 549 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 550 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 551 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 552 553 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 554 mes_remove_queue_pkt.gang_context_addr = 0; 555 556 mes_remove_queue_pkt.pipe_id = input->pipe_id; 557 mes_remove_queue_pkt.queue_id = input->queue_id; 558 559 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 560 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 561 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 562 mes_remove_queue_pkt.tf_data = 563 lower_32_bits(input->trail_fence_data); 564 } else { 565 mes_remove_queue_pkt.unmap_legacy_queue = 1; 566 mes_remove_queue_pkt.queue_type = 567 convert_to_mes_queue_type(input->queue_type); 568 } 569 570 if (mes->adev->enable_uni_mes) 571 pipe = AMDGPU_MES_KIQ_PIPE; 572 else 573 pipe = AMDGPU_MES_SCHED_PIPE; 574 575 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 576 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 577 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 578 } 579 580 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 581 struct mes_suspend_gang_input *input) 582 { 583 union MESAPI__SUSPEND mes_suspend_gang_pkt; 584 585 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 586 587 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 588 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 589 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 590 591 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 592 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 593 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 594 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 595 596 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 597 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 598 offsetof(union MESAPI__SUSPEND, api_status)); 599 } 600 601 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 602 struct mes_resume_gang_input *input) 603 { 604 union MESAPI__RESUME mes_resume_gang_pkt; 605 606 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 607 608 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 609 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 610 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 611 612 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 613 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 614 615 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 616 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 617 offsetof(union MESAPI__RESUME, api_status)); 618 } 619 620 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 621 { 622 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 623 624 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 625 626 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 627 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 628 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 629 630 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 631 &mes_status_pkt, sizeof(mes_status_pkt), 632 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 633 } 634 635 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 636 struct mes_misc_op_input *input) 637 { 638 union MESAPI__MISC misc_pkt; 639 int pipe; 640 641 if (mes->adev->enable_uni_mes) 642 pipe = AMDGPU_MES_KIQ_PIPE; 643 else 644 pipe = AMDGPU_MES_SCHED_PIPE; 645 646 memset(&misc_pkt, 0, sizeof(misc_pkt)); 647 648 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 649 misc_pkt.header.opcode = MES_SCH_API_MISC; 650 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 651 652 switch (input->op) { 653 case MES_MISC_OP_READ_REG: 654 misc_pkt.opcode = MESAPI_MISC__READ_REG; 655 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 656 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 657 break; 658 case MES_MISC_OP_WRITE_REG: 659 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 660 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 661 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 662 break; 663 case MES_MISC_OP_WRM_REG_WAIT: 664 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 665 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 666 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 667 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 668 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 669 misc_pkt.wait_reg_mem.reg_offset2 = 0; 670 break; 671 case MES_MISC_OP_WRM_REG_WR_WAIT: 672 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 673 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 674 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 675 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 676 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 677 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 678 break; 679 case MES_MISC_OP_SET_SHADER_DEBUGGER: 680 pipe = AMDGPU_MES_SCHED_PIPE; 681 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 682 misc_pkt.set_shader_debugger.process_context_addr = 683 input->set_shader_debugger.process_context_addr; 684 misc_pkt.set_shader_debugger.flags.u32all = 685 input->set_shader_debugger.flags.u32all; 686 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 687 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 688 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 689 input->set_shader_debugger.tcp_watch_cntl, 690 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 691 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 692 break; 693 case MES_MISC_OP_CHANGE_CONFIG: 694 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 695 misc_pkt.change_config.opcode = 696 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 697 misc_pkt.change_config.option.bits.limit_single_process = 698 input->change_config.option.limit_single_process; 699 break; 700 701 default: 702 DRM_ERROR("unsupported misc op (%d)\n", input->op); 703 return -EINVAL; 704 } 705 706 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 707 &misc_pkt, sizeof(misc_pkt), 708 offsetof(union MESAPI__MISC, api_status)); 709 } 710 711 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 712 { 713 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 714 715 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 716 717 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 718 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 719 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 720 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa; 721 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr = 722 mes->resource_1_gpu_addr[pipe]; 723 724 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 725 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 726 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 727 } 728 729 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 730 { 731 int i; 732 struct amdgpu_device *adev = mes->adev; 733 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 734 735 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 736 737 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 738 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 739 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 740 741 if (pipe == AMDGPU_MES_SCHED_PIPE) { 742 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 743 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 744 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 745 mes_set_hw_res_pkt.paging_vmid = 0; 746 747 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 748 mes_set_hw_res_pkt.compute_hqd_mask[i] = 749 mes->compute_hqd_mask[i]; 750 751 for (i = 0; i < MAX_GFX_PIPES; i++) 752 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 753 mes->gfx_hqd_mask[i]; 754 755 for (i = 0; i < MAX_SDMA_PIPES; i++) 756 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 757 mes->sdma_hqd_mask[i]; 758 759 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 760 mes_set_hw_res_pkt.aggregated_doorbells[i] = 761 mes->aggregated_doorbells[i]; 762 } 763 764 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 765 mes->sch_ctx_gpu_addr[pipe]; 766 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 767 mes->query_status_fence_gpu_addr[pipe]; 768 769 for (i = 0; i < 5; i++) { 770 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 771 mes_set_hw_res_pkt.mmhub_base[i] = 772 adev->reg_offset[MMHUB_HWIP][0][i]; 773 mes_set_hw_res_pkt.osssys_base[i] = 774 adev->reg_offset[OSSSYS_HWIP][0][i]; 775 } 776 777 mes_set_hw_res_pkt.disable_reset = 1; 778 mes_set_hw_res_pkt.disable_mes_log = 1; 779 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 780 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 781 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 782 783 /* 784 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 785 * handling support, other queue will not use the oversubscribe timer. 786 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 787 */ 788 mes_set_hw_res_pkt.oversubscription_timer = 50; 789 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 790 791 if (amdgpu_mes_log_enable) { 792 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 793 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + 794 pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 795 } 796 797 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 798 mes_set_hw_res_pkt.limit_single_process = 1; 799 800 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 801 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 802 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 803 } 804 805 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 806 { 807 struct amdgpu_device *adev = mes->adev; 808 uint32_t data; 809 810 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 811 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 812 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 813 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 814 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 815 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 816 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 817 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 818 819 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 820 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 821 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 822 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 823 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 824 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 825 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 826 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 827 828 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 829 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 830 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 831 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 832 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 833 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 834 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 835 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 836 837 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 838 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 839 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 840 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 841 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 842 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 843 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 844 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 845 846 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 847 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 848 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 849 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 850 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 851 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 852 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 853 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 854 855 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 856 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 857 } 858 859 860 static void mes_v12_0_enable_unmapped_doorbell_handling( 861 struct amdgpu_mes *mes, bool enable) 862 { 863 struct amdgpu_device *adev = mes->adev; 864 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 865 866 /* 867 * The default PROC_LSB settng is 0xc which means doorbell 868 * addr[16:12] gives the doorbell page number. For kfd, each 869 * process will use 2 pages of doorbell, we need to change the 870 * setting to 0xd 871 */ 872 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 873 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 874 875 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 876 877 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 878 } 879 880 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 881 struct mes_reset_queue_input *input) 882 { 883 union MESAPI__RESET mes_reset_queue_pkt; 884 int pipe; 885 886 if (input->use_mmio) 887 return mes_v12_0_reset_queue_mmio(mes, input->queue_type, 888 input->me_id, input->pipe_id, 889 input->queue_id, input->vmid); 890 891 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 892 893 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 894 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 895 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 896 897 mes_reset_queue_pkt.queue_type = 898 convert_to_mes_queue_type(input->queue_type); 899 900 if (input->legacy_gfx) { 901 mes_reset_queue_pkt.reset_legacy_gfx = 1; 902 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 903 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 904 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 905 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 906 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 907 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 908 } else { 909 mes_reset_queue_pkt.reset_queue_only = 1; 910 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 911 } 912 913 if (input->is_kq) 914 pipe = AMDGPU_MES_KIQ_PIPE; 915 else 916 pipe = AMDGPU_MES_SCHED_PIPE; 917 918 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 919 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 920 offsetof(union MESAPI__RESET, api_status)); 921 } 922 923 static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 924 struct mes_detect_and_reset_queue_input *input) 925 { 926 union MESAPI__RESET mes_reset_queue_pkt; 927 928 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 929 930 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 931 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 932 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 933 934 mes_reset_queue_pkt.queue_type = 935 convert_to_mes_queue_type(input->queue_type); 936 mes_reset_queue_pkt.doorbell_offset_addr = 937 mes->hung_queue_db_array_gpu_addr[0]; 938 939 if (input->detect_only) 940 mes_reset_queue_pkt.hang_detect_only = 1; 941 else 942 mes_reset_queue_pkt.hang_detect_then_reset = 1; 943 944 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 945 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 946 offsetof(union MESAPI__RESET, api_status)); 947 } 948 949 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 950 { 951 /* 952 * MES doesn't support invalidate gc_hub on slave xcc individually 953 * master xcc will invalidate all gc_hub for the partition 954 */ 955 if (AMDGPU_IS_GFXHUB(id)) 956 return 0; 957 else if (AMDGPU_IS_MMHUB0(id)) 958 return 1; 959 else 960 return -EINVAL; 961 962 } 963 964 static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, 965 struct mes_inv_tlbs_pasid_input *input) 966 { 967 union MESAPI__INV_TLBS mes_inv_tlbs; 968 int ret; 969 970 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 971 972 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 973 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 974 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 975 976 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 977 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 978 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 979 980 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 981 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 982 if (ret < 0) 983 return -EINVAL; 984 mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 985 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, 986 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 987 offsetof(union MESAPI__INV_TLBS, api_status)); 988 989 } 990 991 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 992 .add_hw_queue = mes_v12_0_add_hw_queue, 993 .remove_hw_queue = mes_v12_0_remove_hw_queue, 994 .map_legacy_queue = mes_v12_0_map_legacy_queue, 995 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 996 .suspend_gang = mes_v12_0_suspend_gang, 997 .resume_gang = mes_v12_0_resume_gang, 998 .misc_op = mes_v12_0_misc_op, 999 .reset_hw_queue = mes_v12_0_reset_hw_queue, 1000 .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, 1001 .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, 1002 }; 1003 1004 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1005 enum amdgpu_mes_pipe pipe) 1006 { 1007 int r; 1008 const struct mes_firmware_header_v1_0 *mes_hdr; 1009 const __le32 *fw_data; 1010 unsigned fw_size; 1011 1012 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1013 adev->mes.fw[pipe]->data; 1014 1015 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1016 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1017 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1018 1019 r = amdgpu_bo_create_reserved(adev, fw_size, 1020 PAGE_SIZE, 1021 AMDGPU_GEM_DOMAIN_VRAM, 1022 &adev->mes.ucode_fw_obj[pipe], 1023 &adev->mes.ucode_fw_gpu_addr[pipe], 1024 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1025 if (r) { 1026 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1027 return r; 1028 } 1029 1030 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1031 1032 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1033 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1034 1035 return 0; 1036 } 1037 1038 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1039 enum amdgpu_mes_pipe pipe) 1040 { 1041 int r; 1042 const struct mes_firmware_header_v1_0 *mes_hdr; 1043 const __le32 *fw_data; 1044 unsigned fw_size; 1045 1046 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1047 adev->mes.fw[pipe]->data; 1048 1049 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1050 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1051 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1052 1053 r = amdgpu_bo_create_reserved(adev, fw_size, 1054 64 * 1024, 1055 AMDGPU_GEM_DOMAIN_VRAM, 1056 &adev->mes.data_fw_obj[pipe], 1057 &adev->mes.data_fw_gpu_addr[pipe], 1058 (void **)&adev->mes.data_fw_ptr[pipe]); 1059 if (r) { 1060 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1061 return r; 1062 } 1063 1064 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1065 1066 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1067 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1068 1069 return 0; 1070 } 1071 1072 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 1073 enum amdgpu_mes_pipe pipe) 1074 { 1075 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1076 &adev->mes.data_fw_gpu_addr[pipe], 1077 (void **)&adev->mes.data_fw_ptr[pipe]); 1078 1079 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1080 &adev->mes.ucode_fw_gpu_addr[pipe], 1081 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1082 } 1083 1084 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 1085 { 1086 uint64_t ucode_addr; 1087 uint32_t pipe, data = 0; 1088 1089 if (enable) { 1090 mutex_lock(&adev->srbm_mutex); 1091 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1092 soc21_grbm_select(adev, 3, pipe, 0, 0); 1093 if (amdgpu_mes_log_enable) { 1094 u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1095 /* In case uni mes is not enabled, only program for pipe 0 */ 1096 if (adev->mes.event_log_size >= (pipe + 1) * log_size) { 1097 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1098 lower_32_bits(adev->mes.event_log_gpu_addr + 1099 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1100 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1101 upper_32_bits(adev->mes.event_log_gpu_addr + 1102 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1103 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1104 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1105 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1106 } 1107 } 1108 1109 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1110 if (pipe == 0) 1111 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1112 else 1113 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1114 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1115 1116 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1117 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1118 lower_32_bits(ucode_addr)); 1119 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1120 upper_32_bits(ucode_addr)); 1121 1122 /* unhalt MES and activate one pipe each loop */ 1123 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1124 if (pipe) 1125 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1126 dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data); 1127 1128 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1129 1130 } 1131 soc21_grbm_select(adev, 0, 0, 0, 0); 1132 mutex_unlock(&adev->srbm_mutex); 1133 1134 if (amdgpu_emu_mode) 1135 msleep(100); 1136 else if (adev->enable_uni_mes) 1137 udelay(500); 1138 else 1139 udelay(50); 1140 } else { 1141 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1142 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1143 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1144 data = REG_SET_FIELD(data, CP_MES_CNTL, 1145 MES_INVALIDATE_ICACHE, 1); 1146 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1147 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1148 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1149 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1150 } 1151 } 1152 1153 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 1154 { 1155 uint64_t ucode_addr; 1156 int pipe; 1157 1158 mes_v12_0_enable(adev, false); 1159 1160 mutex_lock(&adev->srbm_mutex); 1161 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1162 /* me=3, queue=0 */ 1163 soc21_grbm_select(adev, 3, pipe, 0, 0); 1164 1165 /* set ucode start address */ 1166 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1167 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1168 lower_32_bits(ucode_addr)); 1169 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1170 upper_32_bits(ucode_addr)); 1171 1172 soc21_grbm_select(adev, 0, 0, 0, 0); 1173 } 1174 mutex_unlock(&adev->srbm_mutex); 1175 } 1176 1177 /* This function is for backdoor MES firmware */ 1178 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 1179 enum amdgpu_mes_pipe pipe, bool prime_icache) 1180 { 1181 int r; 1182 uint32_t data; 1183 1184 mes_v12_0_enable(adev, false); 1185 1186 if (!adev->mes.fw[pipe]) 1187 return -EINVAL; 1188 1189 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 1190 if (r) 1191 return r; 1192 1193 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 1194 if (r) { 1195 mes_v12_0_free_ucode_buffers(adev, pipe); 1196 return r; 1197 } 1198 1199 mutex_lock(&adev->srbm_mutex); 1200 /* me=3, pipe=0, queue=0 */ 1201 soc21_grbm_select(adev, 3, pipe, 0, 0); 1202 1203 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1204 1205 /* set ucode fimrware address */ 1206 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1207 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1208 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1209 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1210 1211 /* set ucode instruction cache boundary to 2M-1 */ 1212 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1213 1214 /* set ucode data firmware address */ 1215 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1216 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1217 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1218 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1219 1220 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1221 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1222 1223 if (prime_icache) { 1224 /* invalidate ICACHE */ 1225 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1226 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1227 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1228 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1229 1230 /* prime the ICACHE. */ 1231 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1232 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1233 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1234 } 1235 1236 soc21_grbm_select(adev, 0, 0, 0, 0); 1237 mutex_unlock(&adev->srbm_mutex); 1238 1239 return 0; 1240 } 1241 1242 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 1243 enum amdgpu_mes_pipe pipe) 1244 { 1245 int r; 1246 u32 *eop; 1247 1248 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1249 AMDGPU_GEM_DOMAIN_GTT, 1250 &adev->mes.eop_gpu_obj[pipe], 1251 &adev->mes.eop_gpu_addr[pipe], 1252 (void **)&eop); 1253 if (r) { 1254 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1255 return r; 1256 } 1257 1258 memset(eop, 0, 1259 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1260 1261 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1262 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1263 1264 return 0; 1265 } 1266 1267 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 1268 { 1269 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1270 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1271 uint32_t tmp; 1272 1273 mqd->header = 0xC0310800; 1274 mqd->compute_pipelinestat_enable = 0x00000001; 1275 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1276 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1277 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1278 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1279 mqd->compute_misc_reserved = 0x00000007; 1280 1281 eop_base_addr = ring->eop_gpu_addr >> 8; 1282 1283 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1284 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1285 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1286 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1287 1288 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1289 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1290 mqd->cp_hqd_eop_control = tmp; 1291 1292 /* disable the queue if it's active */ 1293 ring->wptr = 0; 1294 mqd->cp_hqd_pq_rptr = 0; 1295 mqd->cp_hqd_pq_wptr_lo = 0; 1296 mqd->cp_hqd_pq_wptr_hi = 0; 1297 1298 /* set the pointer to the MQD */ 1299 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1300 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1301 1302 /* set MQD vmid to 0 */ 1303 tmp = regCP_MQD_CONTROL_DEFAULT; 1304 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1305 mqd->cp_mqd_control = tmp; 1306 1307 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1308 hqd_gpu_addr = ring->gpu_addr >> 8; 1309 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1310 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1311 1312 /* set the wb address whether it's enabled or not */ 1313 wb_gpu_addr = ring->rptr_gpu_addr; 1314 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1315 mqd->cp_hqd_pq_rptr_report_addr_hi = 1316 upper_32_bits(wb_gpu_addr) & 0xffff; 1317 1318 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1319 wb_gpu_addr = ring->wptr_gpu_addr; 1320 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1321 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1322 1323 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1324 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1325 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1326 (order_base_2(ring->ring_size / 4) - 1)); 1327 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1328 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1329 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1330 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1331 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1332 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1333 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1334 mqd->cp_hqd_pq_control = tmp; 1335 1336 /* enable doorbell */ 1337 tmp = 0; 1338 if (ring->use_doorbell) { 1339 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1340 DOORBELL_OFFSET, ring->doorbell_index); 1341 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1342 DOORBELL_EN, 1); 1343 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1344 DOORBELL_SOURCE, 0); 1345 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1346 DOORBELL_HIT, 0); 1347 } else { 1348 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1349 DOORBELL_EN, 0); 1350 } 1351 mqd->cp_hqd_pq_doorbell_control = tmp; 1352 1353 mqd->cp_hqd_vmid = 0; 1354 /* activate the queue */ 1355 mqd->cp_hqd_active = 1; 1356 1357 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1358 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1359 PRELOAD_SIZE, 0x55); 1360 mqd->cp_hqd_persistent_state = tmp; 1361 1362 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1363 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1364 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1365 1366 /* 1367 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1368 * doorbell handling. This is a reserved CP internal register can 1369 * not be accesss by others 1370 */ 1371 mqd->reserved_184 = BIT(15); 1372 1373 return 0; 1374 } 1375 1376 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1377 { 1378 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1379 struct amdgpu_device *adev = ring->adev; 1380 uint32_t data = 0; 1381 1382 mutex_lock(&adev->srbm_mutex); 1383 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1384 1385 /* set CP_HQD_VMID.VMID = 0. */ 1386 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1387 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1388 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1389 1390 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1391 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1392 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1393 DOORBELL_EN, 0); 1394 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1395 1396 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1397 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1398 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1399 1400 /* set CP_MQD_CONTROL.VMID=0 */ 1401 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1402 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1403 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1404 1405 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1406 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1407 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1408 1409 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1410 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1411 mqd->cp_hqd_pq_rptr_report_addr_lo); 1412 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1413 mqd->cp_hqd_pq_rptr_report_addr_hi); 1414 1415 /* set CP_HQD_PQ_CONTROL */ 1416 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1417 1418 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1419 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1420 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1421 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1422 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1423 1424 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1425 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1426 mqd->cp_hqd_pq_doorbell_control); 1427 1428 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1429 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1430 1431 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1432 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1433 1434 soc21_grbm_select(adev, 0, 0, 0, 0); 1435 mutex_unlock(&adev->srbm_mutex); 1436 } 1437 1438 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1439 { 1440 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1441 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1442 int r; 1443 1444 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1445 return -EINVAL; 1446 1447 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1448 if (r) { 1449 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1450 return r; 1451 } 1452 1453 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1454 1455 r = amdgpu_ring_test_ring(kiq_ring); 1456 if (r) { 1457 DRM_ERROR("kfq enable failed\n"); 1458 kiq_ring->sched.ready = false; 1459 } 1460 return r; 1461 } 1462 1463 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1464 enum amdgpu_mes_pipe pipe) 1465 { 1466 struct amdgpu_ring *ring; 1467 int r; 1468 1469 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1470 ring = &adev->gfx.kiq[0].ring; 1471 else 1472 ring = &adev->mes.ring[pipe]; 1473 1474 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1475 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1476 *(ring->wptr_cpu_addr) = 0; 1477 *(ring->rptr_cpu_addr) = 0; 1478 amdgpu_ring_clear_ring(ring); 1479 } 1480 1481 r = mes_v12_0_mqd_init(ring); 1482 if (r) 1483 return r; 1484 1485 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1486 if (adev->enable_uni_mes) 1487 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 1488 else 1489 r = mes_v12_0_kiq_enable_queue(adev); 1490 if (r) 1491 return r; 1492 } else { 1493 mes_v12_0_queue_init_register(ring); 1494 } 1495 1496 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) || 1497 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) { 1498 /* get MES scheduler/KIQ versions */ 1499 mutex_lock(&adev->srbm_mutex); 1500 soc21_grbm_select(adev, 3, pipe, 0, 0); 1501 1502 if (pipe == AMDGPU_MES_SCHED_PIPE) 1503 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1504 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1505 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1506 1507 soc21_grbm_select(adev, 0, 0, 0, 0); 1508 mutex_unlock(&adev->srbm_mutex); 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1515 { 1516 struct amdgpu_ring *ring; 1517 1518 ring = &adev->mes.ring[pipe]; 1519 1520 ring->funcs = &mes_v12_0_ring_funcs; 1521 1522 ring->me = 3; 1523 ring->pipe = pipe; 1524 ring->queue = 0; 1525 1526 ring->ring_obj = NULL; 1527 ring->use_doorbell = true; 1528 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1529 ring->no_scheduler = true; 1530 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1531 1532 if (pipe == AMDGPU_MES_SCHED_PIPE) 1533 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1534 else 1535 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1536 1537 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1538 AMDGPU_RING_PRIO_DEFAULT, NULL); 1539 } 1540 1541 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1542 { 1543 struct amdgpu_ring *ring; 1544 1545 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1546 1547 ring = &adev->gfx.kiq[0].ring; 1548 1549 ring->me = 3; 1550 ring->pipe = 1; 1551 ring->queue = 0; 1552 1553 ring->adev = NULL; 1554 ring->ring_obj = NULL; 1555 ring->use_doorbell = true; 1556 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1557 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1558 ring->no_scheduler = true; 1559 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1560 ring->me, ring->pipe, ring->queue); 1561 1562 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1563 AMDGPU_RING_PRIO_DEFAULT, NULL); 1564 } 1565 1566 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1567 enum amdgpu_mes_pipe pipe) 1568 { 1569 int r, mqd_size = sizeof(struct v12_compute_mqd); 1570 struct amdgpu_ring *ring; 1571 1572 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1573 ring = &adev->gfx.kiq[0].ring; 1574 else 1575 ring = &adev->mes.ring[pipe]; 1576 1577 if (ring->mqd_obj) 1578 return 0; 1579 1580 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1581 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1582 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1583 if (r) { 1584 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1585 return r; 1586 } 1587 1588 memset(ring->mqd_ptr, 0, mqd_size); 1589 1590 /* prepare MQD backup */ 1591 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1592 if (!adev->mes.mqd_backup[pipe]) 1593 dev_warn(adev->dev, 1594 "no memory to create MQD backup for ring %s\n", 1595 ring->name); 1596 1597 return 0; 1598 } 1599 1600 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1601 { 1602 struct amdgpu_device *adev = ip_block->adev; 1603 int pipe, r; 1604 1605 adev->mes.funcs = &mes_v12_0_funcs; 1606 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1607 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1608 adev->mes.enable_legacy_queue_map = true; 1609 1610 adev->mes.event_log_size = adev->enable_uni_mes ? 1611 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : 1612 (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 1613 r = amdgpu_mes_init(adev); 1614 if (r) 1615 return r; 1616 1617 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1618 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1619 if (r) 1620 return r; 1621 1622 r = mes_v12_0_mqd_sw_init(adev, pipe); 1623 if (r) 1624 return r; 1625 1626 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) { 1627 r = mes_v12_0_kiq_ring_init(adev); 1628 } 1629 else { 1630 r = mes_v12_0_ring_init(adev, pipe); 1631 if (r) 1632 return r; 1633 r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1634 AMDGPU_GEM_DOMAIN_VRAM, 1635 &adev->mes.resource_1[pipe], 1636 &adev->mes.resource_1_gpu_addr[pipe], 1637 &adev->mes.resource_1_addr[pipe]); 1638 if (r) { 1639 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe); 1640 return r; 1641 } 1642 } 1643 } 1644 1645 return 0; 1646 } 1647 1648 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1649 { 1650 struct amdgpu_device *adev = ip_block->adev; 1651 int pipe; 1652 1653 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1654 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], 1655 &adev->mes.resource_1_gpu_addr[pipe], 1656 &adev->mes.resource_1_addr[pipe]); 1657 1658 kfree(adev->mes.mqd_backup[pipe]); 1659 1660 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1661 &adev->mes.eop_gpu_addr[pipe], 1662 NULL); 1663 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1664 1665 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1666 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1667 &adev->mes.ring[pipe].mqd_gpu_addr, 1668 &adev->mes.ring[pipe].mqd_ptr); 1669 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1670 } 1671 } 1672 1673 if (!adev->enable_uni_mes) { 1674 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1675 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1676 &adev->gfx.kiq[0].ring.mqd_ptr); 1677 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1678 } 1679 1680 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1681 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1682 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1683 } 1684 1685 amdgpu_mes_fini(adev); 1686 return 0; 1687 } 1688 1689 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1690 { 1691 uint32_t data; 1692 int i; 1693 1694 mutex_lock(&adev->srbm_mutex); 1695 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1696 1697 /* disable the queue if it's active */ 1698 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1699 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1700 for (i = 0; i < adev->usec_timeout; i++) { 1701 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1702 break; 1703 udelay(1); 1704 } 1705 } 1706 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1707 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1708 DOORBELL_EN, 0); 1709 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1710 DOORBELL_HIT, 1); 1711 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1712 1713 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1714 1715 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1716 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1717 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1718 1719 soc21_grbm_select(adev, 0, 0, 0, 0); 1720 mutex_unlock(&adev->srbm_mutex); 1721 1722 adev->mes.ring[0].sched.ready = false; 1723 } 1724 1725 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1726 { 1727 uint32_t tmp; 1728 struct amdgpu_device *adev = ring->adev; 1729 1730 /* tell RLC which is KIQ queue */ 1731 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1732 tmp &= 0xffffff00; 1733 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1734 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1735 } 1736 1737 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1738 { 1739 int r = 0; 1740 struct amdgpu_ip_block *ip_block; 1741 1742 if (adev->enable_uni_mes) 1743 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1744 else 1745 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1746 1747 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1748 1749 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1750 if (r) { 1751 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1752 return r; 1753 } 1754 1755 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1756 if (r) { 1757 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1758 return r; 1759 } 1760 1761 mes_v12_0_set_ucode_start_addr(adev); 1762 1763 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1764 mes_v12_0_set_ucode_start_addr(adev); 1765 1766 mes_v12_0_enable(adev, true); 1767 1768 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1769 if (unlikely(!ip_block)) { 1770 dev_err(adev->dev, "Failed to get MES handle\n"); 1771 return -EINVAL; 1772 } 1773 1774 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1775 if (r) 1776 goto failure; 1777 1778 if (adev->enable_uni_mes) { 1779 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1780 if (r) 1781 goto failure; 1782 1783 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1784 } 1785 1786 if (adev->mes.enable_legacy_queue_map) { 1787 r = mes_v12_0_hw_init(ip_block); 1788 if (r) 1789 goto failure; 1790 } 1791 1792 return r; 1793 1794 failure: 1795 mes_v12_0_hw_fini(ip_block); 1796 return r; 1797 } 1798 1799 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1800 { 1801 if (adev->mes.ring[0].sched.ready) { 1802 if (adev->enable_uni_mes) 1803 amdgpu_mes_unmap_legacy_queue(adev, 1804 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 1805 RESET_QUEUES, 0, 0, 0); 1806 else 1807 mes_v12_0_kiq_dequeue_sched(adev); 1808 1809 adev->mes.ring[0].sched.ready = false; 1810 } 1811 1812 mes_v12_0_enable(adev, false); 1813 1814 return 0; 1815 } 1816 1817 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 1818 { 1819 int r; 1820 struct amdgpu_device *adev = ip_block->adev; 1821 1822 if (adev->mes.ring[0].sched.ready) 1823 goto out; 1824 1825 if (!adev->enable_mes_kiq) { 1826 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1827 r = mes_v12_0_load_microcode(adev, 1828 AMDGPU_MES_SCHED_PIPE, true); 1829 if (r) { 1830 DRM_ERROR("failed to MES fw, r=%d\n", r); 1831 return r; 1832 } 1833 1834 mes_v12_0_set_ucode_start_addr(adev); 1835 1836 } else if (adev->firmware.load_type == 1837 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1838 1839 mes_v12_0_set_ucode_start_addr(adev); 1840 } 1841 1842 mes_v12_0_enable(adev, true); 1843 } 1844 1845 /* Enable the MES to handle doorbell ring on unmapped queue */ 1846 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1847 1848 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1849 if (r) 1850 goto failure; 1851 1852 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1853 if (r) 1854 goto failure; 1855 1856 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b) 1857 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1858 1859 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1860 1861 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1862 if (r) { 1863 DRM_ERROR("MES is busy\n"); 1864 goto failure; 1865 } 1866 1867 r = amdgpu_mes_update_enforce_isolation(adev); 1868 if (r) 1869 goto failure; 1870 1871 out: 1872 /* 1873 * Disable KIQ ring usage from the driver once MES is enabled. 1874 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1875 * with MES enabled. 1876 */ 1877 adev->gfx.kiq[0].ring.sched.ready = false; 1878 adev->mes.ring[0].sched.ready = true; 1879 1880 return 0; 1881 1882 failure: 1883 mes_v12_0_hw_fini(ip_block); 1884 return r; 1885 } 1886 1887 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 1888 { 1889 return 0; 1890 } 1891 1892 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) 1893 { 1894 return mes_v12_0_hw_fini(ip_block); 1895 } 1896 1897 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) 1898 { 1899 return mes_v12_0_hw_init(ip_block); 1900 } 1901 1902 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) 1903 { 1904 struct amdgpu_device *adev = ip_block->adev; 1905 int pipe, r; 1906 1907 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1908 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; 1909 1910 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1911 r = amdgpu_mes_init_microcode(adev, pipe); 1912 if (r) 1913 return r; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1920 .name = "mes_v12_0", 1921 .early_init = mes_v12_0_early_init, 1922 .late_init = NULL, 1923 .sw_init = mes_v12_0_sw_init, 1924 .sw_fini = mes_v12_0_sw_fini, 1925 .hw_init = mes_v12_0_hw_init, 1926 .hw_fini = mes_v12_0_hw_fini, 1927 .suspend = mes_v12_0_suspend, 1928 .resume = mes_v12_0_resume, 1929 }; 1930 1931 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1932 .type = AMD_IP_BLOCK_TYPE_MES, 1933 .major = 12, 1934 .minor = 0, 1935 .rev = 0, 1936 .funcs = &mes_v12_0_ip_funcs, 1937 }; 1938