1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "gfx_v12_0.h" 28 #include "soc15_common.h" 29 #include "soc21.h" 30 #include "gc/gc_12_0_0_offset.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v12_structs.h" 34 #include "mes_v12_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); 42 43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); 44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); 45 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v12_0_ring_get_rptr, 85 .get_wptr = mes_v12_0_ring_get_wptr, 86 .set_wptr = mes_v12_0_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static const char *mes_v12_0_opcodes[] = { 91 "SET_HW_RSRC", 92 "SET_SCHEDULING_CONFIG", 93 "ADD_QUEUE", 94 "REMOVE_QUEUE", 95 "PERFORM_YIELD", 96 "SET_GANG_PRIORITY_LEVEL", 97 "SUSPEND", 98 "RESUME", 99 "RESET", 100 "SET_LOG_BUFFER", 101 "CHANGE_GANG_PRORITY", 102 "QUERY_SCHEDULER_STATUS", 103 "unused", 104 "SET_DEBUG_VMID", 105 "MISC", 106 "UPDATE_ROOT_PAGE_TABLE", 107 "AMD_LOG", 108 "SET_SE_MODE", 109 "SET_GANG_SUBMIT", 110 "SET_HW_RSRC_1", 111 "INVALIDATE_TLBS", 112 }; 113 114 static const char *mes_v12_0_misc_opcodes[] = { 115 "WRITE_REG", 116 "INV_GART", 117 "QUERY_STATUS", 118 "READ_REG", 119 "WAIT_REG_MEM", 120 "SET_SHADER_DEBUGGER", 121 "NOTIFY_WORK_ON_UNMAPPED_QUEUE", 122 "NOTIFY_TO_UNMAP_PROCESSES", 123 }; 124 125 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt) 126 { 127 const char *op_str = NULL; 128 129 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes)) 130 op_str = mes_v12_0_opcodes[x_pkt->header.opcode]; 131 132 return op_str; 133 } 134 135 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 136 { 137 const char *op_str = NULL; 138 139 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 140 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes))) 141 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode]; 142 143 return op_str; 144 } 145 146 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 147 int pipe, void *pkt, int size, 148 int api_status_off) 149 { 150 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 151 signed long timeout = 2100000; /* 2100 ms */ 152 struct amdgpu_device *adev = mes->adev; 153 struct amdgpu_ring *ring = &mes->ring[pipe]; 154 spinlock_t *ring_lock = &mes->ring_lock[pipe]; 155 struct MES_API_STATUS *api_status; 156 union MESAPI__MISC *x_pkt = pkt; 157 const char *op_str, *misc_op_str; 158 unsigned long flags; 159 u64 status_gpu_addr; 160 u32 seq, status_offset; 161 u64 *status_ptr; 162 signed long r; 163 int ret; 164 165 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 166 return -EINVAL; 167 168 if (amdgpu_emu_mode) { 169 timeout *= 100; 170 } else if (amdgpu_sriov_vf(adev)) { 171 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 172 timeout = 15 * 600 * 1000; 173 } 174 175 ret = amdgpu_device_wb_get(adev, &status_offset); 176 if (ret) 177 return ret; 178 179 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 180 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 181 *status_ptr = 0; 182 183 spin_lock_irqsave(ring_lock, flags); 184 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 185 if (r) 186 goto error_unlock_free; 187 188 seq = ++ring->fence_drv.sync_seq; 189 r = amdgpu_fence_wait_polling(ring, 190 seq - ring->fence_drv.num_fences_mask, 191 timeout); 192 if (r < 1) 193 goto error_undo; 194 195 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 196 api_status->api_completion_fence_addr = status_gpu_addr; 197 api_status->api_completion_fence_value = 1; 198 199 amdgpu_ring_write_multiple(ring, pkt, size / 4); 200 201 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 202 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 203 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 204 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 205 mes_status_pkt.api_status.api_completion_fence_addr = 206 ring->fence_drv.gpu_addr; 207 mes_status_pkt.api_status.api_completion_fence_value = seq; 208 209 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 210 sizeof(mes_status_pkt) / 4); 211 212 amdgpu_ring_commit(ring); 213 spin_unlock_irqrestore(ring_lock, flags); 214 215 op_str = mes_v12_0_get_op_string(x_pkt); 216 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt); 217 218 if (misc_op_str) 219 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n", 220 pipe, op_str, misc_op_str); 221 else if (op_str) 222 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n", 223 pipe, op_str); 224 else 225 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n", 226 pipe, x_pkt->header.opcode); 227 228 r = amdgpu_fence_wait_polling(ring, seq, timeout); 229 if (r < 1 || !*status_ptr) { 230 231 if (misc_op_str) 232 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", 233 pipe, op_str, misc_op_str); 234 else if (op_str) 235 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n", 236 pipe, op_str); 237 else 238 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n", 239 pipe, x_pkt->header.opcode); 240 241 while (halt_if_hws_hang) 242 schedule(); 243 244 r = -ETIMEDOUT; 245 goto error_wb_free; 246 } 247 248 amdgpu_device_wb_free(adev, status_offset); 249 return 0; 250 251 error_undo: 252 dev_err(adev->dev, "MES ring buffer is full.\n"); 253 amdgpu_ring_undo(ring); 254 255 error_unlock_free: 256 spin_unlock_irqrestore(ring_lock, flags); 257 258 error_wb_free: 259 amdgpu_device_wb_free(adev, status_offset); 260 return r; 261 } 262 263 static int convert_to_mes_queue_type(int queue_type) 264 { 265 if (queue_type == AMDGPU_RING_TYPE_GFX) 266 return MES_QUEUE_TYPE_GFX; 267 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 268 return MES_QUEUE_TYPE_COMPUTE; 269 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 270 return MES_QUEUE_TYPE_SDMA; 271 else if (queue_type == AMDGPU_RING_TYPE_MES) 272 return MES_QUEUE_TYPE_SCHQ; 273 else 274 BUG(); 275 return -1; 276 } 277 278 static int convert_to_mes_priority_level(int priority_level) 279 { 280 switch (priority_level) { 281 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 282 return AMD_PRIORITY_LEVEL_LOW; 283 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 284 default: 285 return AMD_PRIORITY_LEVEL_NORMAL; 286 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 287 return AMD_PRIORITY_LEVEL_MEDIUM; 288 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 289 return AMD_PRIORITY_LEVEL_HIGH; 290 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 291 return AMD_PRIORITY_LEVEL_REALTIME; 292 } 293 } 294 295 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes, 296 struct mes_add_queue_input *input) 297 { 298 struct amdgpu_device *adev = mes->adev; 299 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 300 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 301 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 302 303 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 304 305 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 306 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 307 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 308 309 mes_add_queue_pkt.process_id = input->process_id; 310 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 311 mes_add_queue_pkt.process_va_start = input->process_va_start; 312 mes_add_queue_pkt.process_va_end = input->process_va_end; 313 mes_add_queue_pkt.process_quantum = input->process_quantum; 314 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 315 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 316 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 317 mes_add_queue_pkt.inprocess_gang_priority = 318 convert_to_mes_priority_level(input->inprocess_gang_priority); 319 mes_add_queue_pkt.gang_global_priority_level = 320 convert_to_mes_priority_level(input->gang_global_priority_level); 321 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 322 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 323 324 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 325 326 mes_add_queue_pkt.queue_type = 327 convert_to_mes_queue_type(input->queue_type); 328 mes_add_queue_pkt.paging = input->paging; 329 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 330 mes_add_queue_pkt.gws_base = input->gws_base; 331 mes_add_queue_pkt.gws_size = input->gws_size; 332 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 333 mes_add_queue_pkt.tma_addr = input->tma_addr; 334 mes_add_queue_pkt.trap_en = input->trap_en; 335 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 336 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 337 338 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 339 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 340 mes_add_queue_pkt.gds_size = input->queue_size; 341 342 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 343 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 344 mes_add_queue_pkt.gds_size = input->queue_size; 345 346 return mes_v12_0_submit_pkt_and_poll_completion(mes, 347 AMDGPU_MES_SCHED_PIPE, 348 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 349 offsetof(union MESAPI__ADD_QUEUE, api_status)); 350 } 351 352 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, 353 struct mes_remove_queue_input *input) 354 { 355 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 356 357 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 358 359 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 360 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 361 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 362 363 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 364 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 365 366 return mes_v12_0_submit_pkt_and_poll_completion(mes, 367 AMDGPU_MES_SCHED_PIPE, 368 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 369 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 370 } 371 372 int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev, 373 bool req) 374 { 375 u32 i, tmp, val; 376 377 for (i = 0; i < adev->usec_timeout; i++) { 378 /* Request with MeId=2, PipeId=0 */ 379 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 380 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 381 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 382 383 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 384 if (req) { 385 if (val == tmp) 386 break; 387 } else { 388 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 389 REQUEST, 1); 390 391 /* unlocked or locked by firmware */ 392 if (val != tmp) 393 break; 394 } 395 udelay(1); 396 } 397 398 if (i >= adev->usec_timeout) 399 return -EINVAL; 400 401 return 0; 402 } 403 404 static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 405 uint32_t me_id, uint32_t pipe_id, 406 uint32_t queue_id, uint32_t vmid) 407 { 408 struct amdgpu_device *adev = mes->adev; 409 uint32_t value, reg; 410 int i, r = 0; 411 412 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 413 414 if (queue_type == AMDGPU_RING_TYPE_GFX) { 415 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 416 me_id, pipe_id, queue_id, vmid); 417 418 mutex_lock(&adev->gfx.reset_sem_mutex); 419 gfx_v12_0_request_gfx_index_mutex(adev, true); 420 /* all se allow writes */ 421 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 422 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 423 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 424 if (pipe_id == 0) 425 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 426 else 427 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 428 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 429 gfx_v12_0_request_gfx_index_mutex(adev, false); 430 mutex_unlock(&adev->gfx.reset_sem_mutex); 431 432 mutex_lock(&adev->srbm_mutex); 433 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 434 /* wait till dequeue take effects */ 435 for (i = 0; i < adev->usec_timeout; i++) { 436 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 437 break; 438 udelay(1); 439 } 440 if (i >= adev->usec_timeout) { 441 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 442 r = -ETIMEDOUT; 443 } 444 445 soc21_grbm_select(adev, 0, 0, 0, 0); 446 mutex_unlock(&adev->srbm_mutex); 447 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 448 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 449 me_id, pipe_id, queue_id); 450 mutex_lock(&adev->srbm_mutex); 451 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 452 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 453 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 454 455 /* wait till dequeue take effects */ 456 for (i = 0; i < adev->usec_timeout; i++) { 457 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 458 break; 459 udelay(1); 460 } 461 if (i >= adev->usec_timeout) { 462 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 463 r = -ETIMEDOUT; 464 } 465 soc21_grbm_select(adev, 0, 0, 0, 0); 466 mutex_unlock(&adev->srbm_mutex); 467 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 468 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 469 me_id, pipe_id, queue_id); 470 switch (me_id) { 471 case 1: 472 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 473 break; 474 case 0: 475 default: 476 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 477 break; 478 } 479 480 value = 1 << queue_id; 481 WREG32(reg, value); 482 /* wait for queue reset done */ 483 for (i = 0; i < adev->usec_timeout; i++) { 484 if (!(RREG32(reg) & value)) 485 break; 486 udelay(1); 487 } 488 if (i >= adev->usec_timeout) { 489 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 490 r = -ETIMEDOUT; 491 } 492 } 493 494 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 495 return r; 496 } 497 498 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, 499 struct mes_map_legacy_queue_input *input) 500 { 501 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 502 int pipe; 503 504 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 505 506 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 507 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 508 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 509 510 mes_add_queue_pkt.pipe_id = input->pipe_id; 511 mes_add_queue_pkt.queue_id = input->queue_id; 512 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 513 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 514 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 515 mes_add_queue_pkt.queue_type = 516 convert_to_mes_queue_type(input->queue_type); 517 mes_add_queue_pkt.map_legacy_kq = 1; 518 519 if (mes->adev->enable_uni_mes) 520 pipe = AMDGPU_MES_KIQ_PIPE; 521 else 522 pipe = AMDGPU_MES_SCHED_PIPE; 523 524 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 525 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 526 offsetof(union MESAPI__ADD_QUEUE, api_status)); 527 } 528 529 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, 530 struct mes_unmap_legacy_queue_input *input) 531 { 532 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 533 int pipe; 534 535 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 536 537 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 538 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 539 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 540 541 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 542 mes_remove_queue_pkt.gang_context_addr = 0; 543 544 mes_remove_queue_pkt.pipe_id = input->pipe_id; 545 mes_remove_queue_pkt.queue_id = input->queue_id; 546 547 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 548 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 549 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 550 mes_remove_queue_pkt.tf_data = 551 lower_32_bits(input->trail_fence_data); 552 } else { 553 mes_remove_queue_pkt.unmap_legacy_queue = 1; 554 mes_remove_queue_pkt.queue_type = 555 convert_to_mes_queue_type(input->queue_type); 556 } 557 558 if (mes->adev->enable_uni_mes) 559 pipe = AMDGPU_MES_KIQ_PIPE; 560 else 561 pipe = AMDGPU_MES_SCHED_PIPE; 562 563 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 564 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 565 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 566 } 567 568 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 569 struct mes_suspend_gang_input *input) 570 { 571 return 0; 572 } 573 574 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 575 struct mes_resume_gang_input *input) 576 { 577 return 0; 578 } 579 580 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) 581 { 582 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 583 584 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 585 586 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 587 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 588 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 589 590 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 591 &mes_status_pkt, sizeof(mes_status_pkt), 592 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 593 } 594 595 static int mes_v12_0_misc_op(struct amdgpu_mes *mes, 596 struct mes_misc_op_input *input) 597 { 598 union MESAPI__MISC misc_pkt; 599 int pipe; 600 601 if (mes->adev->enable_uni_mes) 602 pipe = AMDGPU_MES_KIQ_PIPE; 603 else 604 pipe = AMDGPU_MES_SCHED_PIPE; 605 606 memset(&misc_pkt, 0, sizeof(misc_pkt)); 607 608 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 609 misc_pkt.header.opcode = MES_SCH_API_MISC; 610 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 611 612 switch (input->op) { 613 case MES_MISC_OP_READ_REG: 614 misc_pkt.opcode = MESAPI_MISC__READ_REG; 615 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 616 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 617 break; 618 case MES_MISC_OP_WRITE_REG: 619 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 620 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 621 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 622 break; 623 case MES_MISC_OP_WRM_REG_WAIT: 624 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 625 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 626 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 627 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 628 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 629 misc_pkt.wait_reg_mem.reg_offset2 = 0; 630 break; 631 case MES_MISC_OP_WRM_REG_WR_WAIT: 632 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 633 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 634 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 635 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 636 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 637 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 638 break; 639 case MES_MISC_OP_SET_SHADER_DEBUGGER: 640 pipe = AMDGPU_MES_SCHED_PIPE; 641 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 642 misc_pkt.set_shader_debugger.process_context_addr = 643 input->set_shader_debugger.process_context_addr; 644 misc_pkt.set_shader_debugger.flags.u32all = 645 input->set_shader_debugger.flags.u32all; 646 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 647 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 648 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 649 input->set_shader_debugger.tcp_watch_cntl, 650 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 651 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 652 break; 653 case MES_MISC_OP_CHANGE_CONFIG: 654 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 655 misc_pkt.change_config.opcode = 656 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 657 misc_pkt.change_config.option.bits.limit_single_process = 658 input->change_config.option.limit_single_process; 659 break; 660 661 default: 662 DRM_ERROR("unsupported misc op (%d) \n", input->op); 663 return -EINVAL; 664 } 665 666 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 667 &misc_pkt, sizeof(misc_pkt), 668 offsetof(union MESAPI__MISC, api_status)); 669 } 670 671 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) 672 { 673 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; 674 675 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); 676 677 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; 678 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 679 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 680 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa; 681 mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr = 682 mes->resource_1_gpu_addr[pipe]; 683 684 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 685 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), 686 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 687 } 688 689 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 690 { 691 int i; 692 struct amdgpu_device *adev = mes->adev; 693 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 694 695 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 696 697 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 698 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 699 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 700 701 if (pipe == AMDGPU_MES_SCHED_PIPE) { 702 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 703 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 704 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 705 mes_set_hw_res_pkt.paging_vmid = 0; 706 707 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 708 mes_set_hw_res_pkt.compute_hqd_mask[i] = 709 mes->compute_hqd_mask[i]; 710 711 for (i = 0; i < MAX_GFX_PIPES; i++) 712 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 713 mes->gfx_hqd_mask[i]; 714 715 for (i = 0; i < MAX_SDMA_PIPES; i++) 716 mes_set_hw_res_pkt.sdma_hqd_mask[i] = 717 mes->sdma_hqd_mask[i]; 718 719 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 720 mes_set_hw_res_pkt.aggregated_doorbells[i] = 721 mes->aggregated_doorbells[i]; 722 } 723 724 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = 725 mes->sch_ctx_gpu_addr[pipe]; 726 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 727 mes->query_status_fence_gpu_addr[pipe]; 728 729 for (i = 0; i < 5; i++) { 730 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 731 mes_set_hw_res_pkt.mmhub_base[i] = 732 adev->reg_offset[MMHUB_HWIP][0][i]; 733 mes_set_hw_res_pkt.osssys_base[i] = 734 adev->reg_offset[OSSSYS_HWIP][0][i]; 735 } 736 737 mes_set_hw_res_pkt.disable_reset = 1; 738 mes_set_hw_res_pkt.disable_mes_log = 1; 739 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 740 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 741 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 742 743 /* 744 * Keep oversubscribe timer for sdma . When we have unmapped doorbell 745 * handling support, other queue will not use the oversubscribe timer. 746 * handling mode - 0: disabled; 1: basic version; 2: basic+ version 747 */ 748 mes_set_hw_res_pkt.oversubscription_timer = 50; 749 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; 750 751 if (amdgpu_mes_log_enable) { 752 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 753 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + 754 pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 755 } 756 757 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 758 mes_set_hw_res_pkt.limit_single_process = 1; 759 760 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 761 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 762 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 763 } 764 765 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 766 { 767 struct amdgpu_device *adev = mes->adev; 768 uint32_t data; 769 770 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 771 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 772 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 773 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 774 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 775 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 776 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 777 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 778 779 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 780 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 781 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 782 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 783 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 784 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 785 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 786 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 787 788 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 789 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 790 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 791 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 792 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 793 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 794 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 795 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 796 797 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 798 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 799 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 800 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 801 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 802 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 803 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 804 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 805 806 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 807 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 808 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 809 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 810 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 811 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 812 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 813 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 814 815 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 816 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 817 } 818 819 820 static void mes_v12_0_enable_unmapped_doorbell_handling( 821 struct amdgpu_mes *mes, bool enable) 822 { 823 struct amdgpu_device *adev = mes->adev; 824 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL); 825 826 /* 827 * The default PROC_LSB settng is 0xc which means doorbell 828 * addr[16:12] gives the doorbell page number. For kfd, each 829 * process will use 2 pages of doorbell, we need to change the 830 * setting to 0xd 831 */ 832 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; 833 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; 834 835 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; 836 837 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data); 838 } 839 840 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 841 struct mes_reset_queue_input *input) 842 { 843 union MESAPI__RESET mes_reset_queue_pkt; 844 int pipe; 845 846 if (input->use_mmio) 847 return mes_v12_0_reset_queue_mmio(mes, input->queue_type, 848 input->me_id, input->pipe_id, 849 input->queue_id, input->vmid); 850 851 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 852 853 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 854 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 855 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 856 857 mes_reset_queue_pkt.queue_type = 858 convert_to_mes_queue_type(input->queue_type); 859 860 if (input->legacy_gfx) { 861 mes_reset_queue_pkt.reset_legacy_gfx = 1; 862 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 863 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 864 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 865 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 866 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 867 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 868 } else { 869 mes_reset_queue_pkt.reset_queue_only = 1; 870 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 871 } 872 873 if (input->is_kq) 874 pipe = AMDGPU_MES_KIQ_PIPE; 875 else 876 pipe = AMDGPU_MES_SCHED_PIPE; 877 878 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, 879 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 880 offsetof(union MESAPI__RESET, api_status)); 881 } 882 883 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 884 { 885 /* 886 * MES doesn't support invalidate gc_hub on slave xcc individually 887 * master xcc will invalidate all gc_hub for the partition 888 */ 889 if (AMDGPU_IS_GFXHUB(id)) 890 return 0; 891 else if (AMDGPU_IS_MMHUB0(id)) 892 return 1; 893 else 894 return -EINVAL; 895 896 } 897 898 static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, 899 struct mes_inv_tlbs_pasid_input *input) 900 { 901 union MESAPI__INV_TLBS mes_inv_tlbs; 902 903 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 904 905 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; 906 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; 907 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 908 909 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; 910 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; 911 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 912 913 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 914 mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 915 if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) 916 return -EINVAL; 917 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, 918 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 919 offsetof(union MESAPI__INV_TLBS, api_status)); 920 921 } 922 923 static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 924 .add_hw_queue = mes_v12_0_add_hw_queue, 925 .remove_hw_queue = mes_v12_0_remove_hw_queue, 926 .map_legacy_queue = mes_v12_0_map_legacy_queue, 927 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue, 928 .suspend_gang = mes_v12_0_suspend_gang, 929 .resume_gang = mes_v12_0_resume_gang, 930 .misc_op = mes_v12_0_misc_op, 931 .reset_hw_queue = mes_v12_0_reset_hw_queue, 932 .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, 933 }; 934 935 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 936 enum amdgpu_mes_pipe pipe) 937 { 938 int r; 939 const struct mes_firmware_header_v1_0 *mes_hdr; 940 const __le32 *fw_data; 941 unsigned fw_size; 942 943 mes_hdr = (const struct mes_firmware_header_v1_0 *) 944 adev->mes.fw[pipe]->data; 945 946 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 947 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 948 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 949 950 r = amdgpu_bo_create_reserved(adev, fw_size, 951 PAGE_SIZE, 952 AMDGPU_GEM_DOMAIN_VRAM, 953 &adev->mes.ucode_fw_obj[pipe], 954 &adev->mes.ucode_fw_gpu_addr[pipe], 955 (void **)&adev->mes.ucode_fw_ptr[pipe]); 956 if (r) { 957 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 958 return r; 959 } 960 961 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 962 963 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 964 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 965 966 return 0; 967 } 968 969 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 970 enum amdgpu_mes_pipe pipe) 971 { 972 int r; 973 const struct mes_firmware_header_v1_0 *mes_hdr; 974 const __le32 *fw_data; 975 unsigned fw_size; 976 977 mes_hdr = (const struct mes_firmware_header_v1_0 *) 978 adev->mes.fw[pipe]->data; 979 980 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 981 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 982 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 983 984 r = amdgpu_bo_create_reserved(adev, fw_size, 985 64 * 1024, 986 AMDGPU_GEM_DOMAIN_VRAM, 987 &adev->mes.data_fw_obj[pipe], 988 &adev->mes.data_fw_gpu_addr[pipe], 989 (void **)&adev->mes.data_fw_ptr[pipe]); 990 if (r) { 991 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 992 return r; 993 } 994 995 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 996 997 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 998 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 999 1000 return 0; 1001 } 1002 1003 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev, 1004 enum amdgpu_mes_pipe pipe) 1005 { 1006 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1007 &adev->mes.data_fw_gpu_addr[pipe], 1008 (void **)&adev->mes.data_fw_ptr[pipe]); 1009 1010 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1011 &adev->mes.ucode_fw_gpu_addr[pipe], 1012 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1013 } 1014 1015 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) 1016 { 1017 uint64_t ucode_addr; 1018 uint32_t pipe, data = 0; 1019 1020 if (enable) { 1021 mutex_lock(&adev->srbm_mutex); 1022 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1023 soc21_grbm_select(adev, 3, pipe, 0, 0); 1024 if (amdgpu_mes_log_enable) { 1025 u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1026 /* In case uni mes is not enabled, only program for pipe 0 */ 1027 if (adev->mes.event_log_size >= (pipe + 1) * log_size) { 1028 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1029 lower_32_bits(adev->mes.event_log_gpu_addr + 1030 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1031 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1032 upper_32_bits(adev->mes.event_log_gpu_addr + 1033 pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE)); 1034 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1035 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1036 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1037 } 1038 } 1039 1040 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1041 if (pipe == 0) 1042 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1043 else 1044 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1045 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1046 1047 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1048 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1049 lower_32_bits(ucode_addr)); 1050 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1051 upper_32_bits(ucode_addr)); 1052 1053 /* unhalt MES and activate one pipe each loop */ 1054 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1055 if (pipe) 1056 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); 1057 dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data); 1058 1059 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1060 1061 } 1062 soc21_grbm_select(adev, 0, 0, 0, 0); 1063 mutex_unlock(&adev->srbm_mutex); 1064 1065 if (amdgpu_emu_mode) 1066 msleep(100); 1067 else if (adev->enable_uni_mes) 1068 udelay(500); 1069 else 1070 udelay(50); 1071 } else { 1072 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1073 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1074 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1075 data = REG_SET_FIELD(data, CP_MES_CNTL, 1076 MES_INVALIDATE_ICACHE, 1); 1077 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1078 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); 1079 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1080 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1081 } 1082 } 1083 1084 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 1085 { 1086 uint64_t ucode_addr; 1087 int pipe; 1088 1089 mes_v12_0_enable(adev, false); 1090 1091 mutex_lock(&adev->srbm_mutex); 1092 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1093 /* me=3, queue=0 */ 1094 soc21_grbm_select(adev, 3, pipe, 0, 0); 1095 1096 /* set ucode start address */ 1097 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1098 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1099 lower_32_bits(ucode_addr)); 1100 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1101 upper_32_bits(ucode_addr)); 1102 1103 soc21_grbm_select(adev, 0, 0, 0, 0); 1104 } 1105 mutex_unlock(&adev->srbm_mutex); 1106 } 1107 1108 /* This function is for backdoor MES firmware */ 1109 static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 1110 enum amdgpu_mes_pipe pipe, bool prime_icache) 1111 { 1112 int r; 1113 uint32_t data; 1114 1115 mes_v12_0_enable(adev, false); 1116 1117 if (!adev->mes.fw[pipe]) 1118 return -EINVAL; 1119 1120 r = mes_v12_0_allocate_ucode_buffer(adev, pipe); 1121 if (r) 1122 return r; 1123 1124 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe); 1125 if (r) { 1126 mes_v12_0_free_ucode_buffers(adev, pipe); 1127 return r; 1128 } 1129 1130 mutex_lock(&adev->srbm_mutex); 1131 /* me=3, pipe=0, queue=0 */ 1132 soc21_grbm_select(adev, 3, pipe, 0, 0); 1133 1134 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1135 1136 /* set ucode fimrware address */ 1137 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1138 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1139 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1140 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1141 1142 /* set ucode instruction cache boundary to 2M-1 */ 1143 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1144 1145 /* set ucode data firmware address */ 1146 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1147 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1148 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1149 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1150 1151 /* Set data cache boundary CP_MES_MDBOUND_LO */ 1152 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1153 1154 if (prime_icache) { 1155 /* invalidate ICACHE */ 1156 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1157 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1158 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1159 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1160 1161 /* prime the ICACHE. */ 1162 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1163 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1164 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1165 } 1166 1167 soc21_grbm_select(adev, 0, 0, 0, 0); 1168 mutex_unlock(&adev->srbm_mutex); 1169 1170 return 0; 1171 } 1172 1173 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev, 1174 enum amdgpu_mes_pipe pipe) 1175 { 1176 int r; 1177 u32 *eop; 1178 1179 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1180 AMDGPU_GEM_DOMAIN_GTT, 1181 &adev->mes.eop_gpu_obj[pipe], 1182 &adev->mes.eop_gpu_addr[pipe], 1183 (void **)&eop); 1184 if (r) { 1185 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1186 return r; 1187 } 1188 1189 memset(eop, 0, 1190 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1191 1192 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1193 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1194 1195 return 0; 1196 } 1197 1198 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring) 1199 { 1200 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1201 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1202 uint32_t tmp; 1203 1204 mqd->header = 0xC0310800; 1205 mqd->compute_pipelinestat_enable = 0x00000001; 1206 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1207 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1208 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1209 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1210 mqd->compute_misc_reserved = 0x00000007; 1211 1212 eop_base_addr = ring->eop_gpu_addr >> 8; 1213 1214 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1215 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1216 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1217 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1218 1219 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1220 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1221 mqd->cp_hqd_eop_control = tmp; 1222 1223 /* disable the queue if it's active */ 1224 ring->wptr = 0; 1225 mqd->cp_hqd_pq_rptr = 0; 1226 mqd->cp_hqd_pq_wptr_lo = 0; 1227 mqd->cp_hqd_pq_wptr_hi = 0; 1228 1229 /* set the pointer to the MQD */ 1230 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1231 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1232 1233 /* set MQD vmid to 0 */ 1234 tmp = regCP_MQD_CONTROL_DEFAULT; 1235 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1236 mqd->cp_mqd_control = tmp; 1237 1238 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1239 hqd_gpu_addr = ring->gpu_addr >> 8; 1240 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1241 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1242 1243 /* set the wb address whether it's enabled or not */ 1244 wb_gpu_addr = ring->rptr_gpu_addr; 1245 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1246 mqd->cp_hqd_pq_rptr_report_addr_hi = 1247 upper_32_bits(wb_gpu_addr) & 0xffff; 1248 1249 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1250 wb_gpu_addr = ring->wptr_gpu_addr; 1251 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1252 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1253 1254 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1255 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1256 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1257 (order_base_2(ring->ring_size / 4) - 1)); 1258 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1259 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1260 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1261 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1262 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1263 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1264 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1265 mqd->cp_hqd_pq_control = tmp; 1266 1267 /* enable doorbell */ 1268 tmp = 0; 1269 if (ring->use_doorbell) { 1270 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1271 DOORBELL_OFFSET, ring->doorbell_index); 1272 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1273 DOORBELL_EN, 1); 1274 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1275 DOORBELL_SOURCE, 0); 1276 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1277 DOORBELL_HIT, 0); 1278 } else { 1279 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1280 DOORBELL_EN, 0); 1281 } 1282 mqd->cp_hqd_pq_doorbell_control = tmp; 1283 1284 mqd->cp_hqd_vmid = 0; 1285 /* activate the queue */ 1286 mqd->cp_hqd_active = 1; 1287 1288 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1289 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1290 PRELOAD_SIZE, 0x55); 1291 mqd->cp_hqd_persistent_state = tmp; 1292 1293 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1294 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1295 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1296 1297 /* 1298 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped 1299 * doorbell handling. This is a reserved CP internal register can 1300 * not be accesss by others 1301 */ 1302 mqd->reserved_184 = BIT(15); 1303 1304 return 0; 1305 } 1306 1307 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring) 1308 { 1309 struct v12_compute_mqd *mqd = ring->mqd_ptr; 1310 struct amdgpu_device *adev = ring->adev; 1311 uint32_t data = 0; 1312 1313 mutex_lock(&adev->srbm_mutex); 1314 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1315 1316 /* set CP_HQD_VMID.VMID = 0. */ 1317 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1318 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1319 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1320 1321 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1322 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1323 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1324 DOORBELL_EN, 0); 1325 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1326 1327 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1328 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1329 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1330 1331 /* set CP_MQD_CONTROL.VMID=0 */ 1332 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1333 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1334 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1335 1336 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1337 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1338 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1339 1340 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1341 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1342 mqd->cp_hqd_pq_rptr_report_addr_lo); 1343 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1344 mqd->cp_hqd_pq_rptr_report_addr_hi); 1345 1346 /* set CP_HQD_PQ_CONTROL */ 1347 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1348 1349 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1350 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1351 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1352 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1353 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1354 1355 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1356 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1357 mqd->cp_hqd_pq_doorbell_control); 1358 1359 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1360 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1361 1362 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1363 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1364 1365 soc21_grbm_select(adev, 0, 0, 0, 0); 1366 mutex_unlock(&adev->srbm_mutex); 1367 } 1368 1369 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 1370 { 1371 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1372 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1373 int r; 1374 1375 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1376 return -EINVAL; 1377 1378 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1379 if (r) { 1380 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1381 return r; 1382 } 1383 1384 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1385 1386 r = amdgpu_ring_test_ring(kiq_ring); 1387 if (r) { 1388 DRM_ERROR("kfq enable failed\n"); 1389 kiq_ring->sched.ready = false; 1390 } 1391 return r; 1392 } 1393 1394 static int mes_v12_0_queue_init(struct amdgpu_device *adev, 1395 enum amdgpu_mes_pipe pipe) 1396 { 1397 struct amdgpu_ring *ring; 1398 int r; 1399 1400 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1401 ring = &adev->gfx.kiq[0].ring; 1402 else 1403 ring = &adev->mes.ring[pipe]; 1404 1405 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && 1406 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1407 *(ring->wptr_cpu_addr) = 0; 1408 *(ring->rptr_cpu_addr) = 0; 1409 amdgpu_ring_clear_ring(ring); 1410 } 1411 1412 r = mes_v12_0_mqd_init(ring); 1413 if (r) 1414 return r; 1415 1416 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1417 if (adev->enable_uni_mes) 1418 r = amdgpu_mes_map_legacy_queue(adev, ring); 1419 else 1420 r = mes_v12_0_kiq_enable_queue(adev); 1421 if (r) 1422 return r; 1423 } else { 1424 mes_v12_0_queue_init_register(ring); 1425 } 1426 1427 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) || 1428 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) { 1429 /* get MES scheduler/KIQ versions */ 1430 mutex_lock(&adev->srbm_mutex); 1431 soc21_grbm_select(adev, 3, pipe, 0, 0); 1432 1433 if (pipe == AMDGPU_MES_SCHED_PIPE) 1434 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1435 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1436 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1437 1438 soc21_grbm_select(adev, 0, 0, 0, 0); 1439 mutex_unlock(&adev->srbm_mutex); 1440 } 1441 1442 return 0; 1443 } 1444 1445 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe) 1446 { 1447 struct amdgpu_ring *ring; 1448 1449 ring = &adev->mes.ring[pipe]; 1450 1451 ring->funcs = &mes_v12_0_ring_funcs; 1452 1453 ring->me = 3; 1454 ring->pipe = pipe; 1455 ring->queue = 0; 1456 1457 ring->ring_obj = NULL; 1458 ring->use_doorbell = true; 1459 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe]; 1460 ring->no_scheduler = true; 1461 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1462 1463 if (pipe == AMDGPU_MES_SCHED_PIPE) 1464 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1465 else 1466 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1467 1468 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1469 AMDGPU_RING_PRIO_DEFAULT, NULL); 1470 } 1471 1472 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 1473 { 1474 struct amdgpu_ring *ring; 1475 1476 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1477 1478 ring = &adev->gfx.kiq[0].ring; 1479 1480 ring->me = 3; 1481 ring->pipe = 1; 1482 ring->queue = 0; 1483 1484 ring->adev = NULL; 1485 ring->ring_obj = NULL; 1486 ring->use_doorbell = true; 1487 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1488 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1489 ring->no_scheduler = true; 1490 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1491 ring->me, ring->pipe, ring->queue); 1492 1493 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1494 AMDGPU_RING_PRIO_DEFAULT, NULL); 1495 } 1496 1497 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, 1498 enum amdgpu_mes_pipe pipe) 1499 { 1500 int r, mqd_size = sizeof(struct v12_compute_mqd); 1501 struct amdgpu_ring *ring; 1502 1503 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) 1504 ring = &adev->gfx.kiq[0].ring; 1505 else 1506 ring = &adev->mes.ring[pipe]; 1507 1508 if (ring->mqd_obj) 1509 return 0; 1510 1511 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1512 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1513 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1514 if (r) { 1515 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1516 return r; 1517 } 1518 1519 memset(ring->mqd_ptr, 0, mqd_size); 1520 1521 /* prepare MQD backup */ 1522 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1523 if (!adev->mes.mqd_backup[pipe]) 1524 dev_warn(adev->dev, 1525 "no memory to create MQD backup for ring %s\n", 1526 ring->name); 1527 1528 return 0; 1529 } 1530 1531 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1532 { 1533 struct amdgpu_device *adev = ip_block->adev; 1534 int pipe, r; 1535 1536 adev->mes.funcs = &mes_v12_0_funcs; 1537 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; 1538 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; 1539 adev->mes.enable_legacy_queue_map = true; 1540 1541 adev->mes.event_log_size = adev->enable_uni_mes ? 1542 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : 1543 (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE); 1544 r = amdgpu_mes_init(adev); 1545 if (r) 1546 return r; 1547 1548 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1549 r = mes_v12_0_allocate_eop_buf(adev, pipe); 1550 if (r) 1551 return r; 1552 1553 r = mes_v12_0_mqd_sw_init(adev, pipe); 1554 if (r) 1555 return r; 1556 1557 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) { 1558 r = mes_v12_0_kiq_ring_init(adev); 1559 } 1560 else { 1561 r = mes_v12_0_ring_init(adev, pipe); 1562 if (r) 1563 return r; 1564 r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, 1565 AMDGPU_GEM_DOMAIN_VRAM, 1566 &adev->mes.resource_1[pipe], 1567 &adev->mes.resource_1_gpu_addr[pipe], 1568 &adev->mes.resource_1_addr[pipe]); 1569 if (r) { 1570 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe); 1571 return r; 1572 } 1573 } 1574 } 1575 1576 return 0; 1577 } 1578 1579 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1580 { 1581 struct amdgpu_device *adev = ip_block->adev; 1582 int pipe; 1583 1584 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1585 amdgpu_bo_free_kernel(&adev->mes.resource_1[pipe], 1586 &adev->mes.resource_1_gpu_addr[pipe], 1587 &adev->mes.resource_1_addr[pipe]); 1588 1589 kfree(adev->mes.mqd_backup[pipe]); 1590 1591 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1592 &adev->mes.eop_gpu_addr[pipe], 1593 NULL); 1594 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1595 1596 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { 1597 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj, 1598 &adev->mes.ring[pipe].mqd_gpu_addr, 1599 &adev->mes.ring[pipe].mqd_ptr); 1600 amdgpu_ring_fini(&adev->mes.ring[pipe]); 1601 } 1602 } 1603 1604 if (!adev->enable_uni_mes) { 1605 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1606 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1607 &adev->gfx.kiq[0].ring.mqd_ptr); 1608 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1609 } 1610 1611 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1612 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1613 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1614 } 1615 1616 amdgpu_mes_fini(adev); 1617 return 0; 1618 } 1619 1620 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1621 { 1622 uint32_t data; 1623 int i; 1624 1625 mutex_lock(&adev->srbm_mutex); 1626 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1627 1628 /* disable the queue if it's active */ 1629 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1630 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1631 for (i = 0; i < adev->usec_timeout; i++) { 1632 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1633 break; 1634 udelay(1); 1635 } 1636 } 1637 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1638 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1639 DOORBELL_EN, 0); 1640 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1641 DOORBELL_HIT, 1); 1642 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1643 1644 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1645 1646 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1647 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1648 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1649 1650 soc21_grbm_select(adev, 0, 0, 0, 0); 1651 mutex_unlock(&adev->srbm_mutex); 1652 1653 adev->mes.ring[0].sched.ready = false; 1654 } 1655 1656 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) 1657 { 1658 uint32_t tmp; 1659 struct amdgpu_device *adev = ring->adev; 1660 1661 /* tell RLC which is KIQ queue */ 1662 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1663 tmp &= 0xffffff00; 1664 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1665 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1666 } 1667 1668 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1669 { 1670 int r = 0; 1671 struct amdgpu_ip_block *ip_block; 1672 1673 if (adev->enable_uni_mes) 1674 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); 1675 else 1676 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring); 1677 1678 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1679 1680 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1681 if (r) { 1682 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1683 return r; 1684 } 1685 1686 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1687 if (r) { 1688 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1689 return r; 1690 } 1691 1692 mes_v12_0_set_ucode_start_addr(adev); 1693 1694 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1695 mes_v12_0_set_ucode_start_addr(adev); 1696 1697 mes_v12_0_enable(adev, true); 1698 1699 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1700 if (unlikely(!ip_block)) { 1701 dev_err(adev->dev, "Failed to get MES handle\n"); 1702 return -EINVAL; 1703 } 1704 1705 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1706 if (r) 1707 goto failure; 1708 1709 if (adev->enable_uni_mes) { 1710 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1711 if (r) 1712 goto failure; 1713 1714 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); 1715 } 1716 1717 if (adev->mes.enable_legacy_queue_map) { 1718 r = mes_v12_0_hw_init(ip_block); 1719 if (r) 1720 goto failure; 1721 } 1722 1723 return r; 1724 1725 failure: 1726 mes_v12_0_hw_fini(ip_block); 1727 return r; 1728 } 1729 1730 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1731 { 1732 if (adev->mes.ring[0].sched.ready) { 1733 if (adev->enable_uni_mes) 1734 amdgpu_mes_unmap_legacy_queue(adev, 1735 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 1736 RESET_QUEUES, 0, 0); 1737 else 1738 mes_v12_0_kiq_dequeue_sched(adev); 1739 1740 adev->mes.ring[0].sched.ready = false; 1741 } 1742 1743 mes_v12_0_enable(adev, false); 1744 1745 return 0; 1746 } 1747 1748 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 1749 { 1750 int r; 1751 struct amdgpu_device *adev = ip_block->adev; 1752 1753 if (adev->mes.ring[0].sched.ready) 1754 goto out; 1755 1756 if (!adev->enable_mes_kiq) { 1757 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1758 r = mes_v12_0_load_microcode(adev, 1759 AMDGPU_MES_SCHED_PIPE, true); 1760 if (r) { 1761 DRM_ERROR("failed to MES fw, r=%d\n", r); 1762 return r; 1763 } 1764 1765 mes_v12_0_set_ucode_start_addr(adev); 1766 1767 } else if (adev->firmware.load_type == 1768 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1769 1770 mes_v12_0_set_ucode_start_addr(adev); 1771 } 1772 1773 mes_v12_0_enable(adev, true); 1774 } 1775 1776 /* Enable the MES to handle doorbell ring on unmapped queue */ 1777 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true); 1778 1779 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1780 if (r) 1781 goto failure; 1782 1783 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1784 if (r) 1785 goto failure; 1786 1787 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x4b) 1788 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1789 1790 mes_v12_0_init_aggregated_doorbell(&adev->mes); 1791 1792 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE); 1793 if (r) { 1794 DRM_ERROR("MES is busy\n"); 1795 goto failure; 1796 } 1797 1798 r = amdgpu_mes_update_enforce_isolation(adev); 1799 if (r) 1800 goto failure; 1801 1802 out: 1803 /* 1804 * Disable KIQ ring usage from the driver once MES is enabled. 1805 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1806 * with MES enabled. 1807 */ 1808 adev->gfx.kiq[0].ring.sched.ready = false; 1809 adev->mes.ring[0].sched.ready = true; 1810 1811 return 0; 1812 1813 failure: 1814 mes_v12_0_hw_fini(ip_block); 1815 return r; 1816 } 1817 1818 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 1819 { 1820 return 0; 1821 } 1822 1823 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) 1824 { 1825 return mes_v12_0_hw_fini(ip_block); 1826 } 1827 1828 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) 1829 { 1830 return mes_v12_0_hw_init(ip_block); 1831 } 1832 1833 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) 1834 { 1835 struct amdgpu_device *adev = ip_block->adev; 1836 int pipe, r; 1837 1838 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1839 r = amdgpu_mes_init_microcode(adev, pipe); 1840 if (r) 1841 return r; 1842 } 1843 1844 return 0; 1845 } 1846 1847 static const struct amd_ip_funcs mes_v12_0_ip_funcs = { 1848 .name = "mes_v12_0", 1849 .early_init = mes_v12_0_early_init, 1850 .late_init = NULL, 1851 .sw_init = mes_v12_0_sw_init, 1852 .sw_fini = mes_v12_0_sw_fini, 1853 .hw_init = mes_v12_0_hw_init, 1854 .hw_fini = mes_v12_0_hw_fini, 1855 .suspend = mes_v12_0_suspend, 1856 .resume = mes_v12_0_resume, 1857 }; 1858 1859 const struct amdgpu_ip_block_version mes_v12_0_ip_block = { 1860 .type = AMD_IP_BLOCK_TYPE_MES, 1861 .major = 12, 1862 .minor = 0, 1863 .rev = 0, 1864 .funcs = &mes_v12_0_ip_funcs, 1865 }; 1866