1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 55 static int mes_v11_0_hw_init(void *handle); 56 static int mes_v11_0_hw_fini(void *handle); 57 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 58 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 59 60 #define MES_EOP_SIZE 2048 61 #define GFX_MES_DRAM_SIZE 0x80000 62 63 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 if (ring->use_doorbell) { 68 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 69 ring->wptr); 70 WDOORBELL64(ring->doorbell_index, ring->wptr); 71 } else { 72 BUG(); 73 } 74 } 75 76 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 77 { 78 return *ring->rptr_cpu_addr; 79 } 80 81 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 82 { 83 u64 wptr; 84 85 if (ring->use_doorbell) 86 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 87 else 88 BUG(); 89 return wptr; 90 } 91 92 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 93 .type = AMDGPU_RING_TYPE_MES, 94 .align_mask = 1, 95 .nop = 0, 96 .support_64bit_ptrs = true, 97 .get_rptr = mes_v11_0_ring_get_rptr, 98 .get_wptr = mes_v11_0_ring_get_wptr, 99 .set_wptr = mes_v11_0_ring_set_wptr, 100 .insert_nop = amdgpu_ring_insert_nop, 101 }; 102 103 static const char *mes_v11_0_opcodes[] = { 104 "SET_HW_RSRC", 105 "SET_SCHEDULING_CONFIG", 106 "ADD_QUEUE", 107 "REMOVE_QUEUE", 108 "PERFORM_YIELD", 109 "SET_GANG_PRIORITY_LEVEL", 110 "SUSPEND", 111 "RESUME", 112 "RESET", 113 "SET_LOG_BUFFER", 114 "CHANGE_GANG_PRORITY", 115 "QUERY_SCHEDULER_STATUS", 116 "PROGRAM_GDS", 117 "SET_DEBUG_VMID", 118 "MISC", 119 "UPDATE_ROOT_PAGE_TABLE", 120 "AMD_LOG", 121 }; 122 123 static const char *mes_v11_0_misc_opcodes[] = { 124 "WRITE_REG", 125 "INV_GART", 126 "QUERY_STATUS", 127 "READ_REG", 128 "WAIT_REG_MEM", 129 "SET_SHADER_DEBUGGER", 130 }; 131 132 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 133 { 134 const char *op_str = NULL; 135 136 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 137 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 138 139 return op_str; 140 } 141 142 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 143 { 144 const char *op_str = NULL; 145 146 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 147 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 148 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 149 150 return op_str; 151 } 152 153 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 154 void *pkt, int size, 155 int api_status_off) 156 { 157 int ndw = size / 4; 158 signed long r; 159 union MESAPI__MISC *x_pkt = pkt; 160 struct MES_API_STATUS *api_status; 161 struct amdgpu_device *adev = mes->adev; 162 struct amdgpu_ring *ring = &mes->ring; 163 unsigned long flags; 164 signed long timeout = 3000000; /* 3000 ms */ 165 const char *op_str, *misc_op_str; 166 u32 fence_offset; 167 u64 fence_gpu_addr; 168 u64 *fence_ptr; 169 int ret; 170 171 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 172 return -EINVAL; 173 174 if (amdgpu_emu_mode) { 175 timeout *= 100; 176 } else if (amdgpu_sriov_vf(adev)) { 177 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 178 timeout = 15 * 600 * 1000; 179 } 180 BUG_ON(size % 4 != 0); 181 182 ret = amdgpu_device_wb_get(adev, &fence_offset); 183 if (ret) 184 return ret; 185 fence_gpu_addr = 186 adev->wb.gpu_addr + (fence_offset * 4); 187 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 188 *fence_ptr = 0; 189 190 spin_lock_irqsave(&mes->ring_lock, flags); 191 if (amdgpu_ring_alloc(ring, ndw)) { 192 spin_unlock_irqrestore(&mes->ring_lock, flags); 193 amdgpu_device_wb_free(adev, fence_offset); 194 return -ENOMEM; 195 } 196 197 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 198 api_status->api_completion_fence_addr = fence_gpu_addr; 199 api_status->api_completion_fence_value = 1; 200 201 amdgpu_ring_write_multiple(ring, pkt, ndw); 202 amdgpu_ring_commit(ring); 203 spin_unlock_irqrestore(&mes->ring_lock, flags); 204 205 op_str = mes_v11_0_get_op_string(x_pkt); 206 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 207 208 if (misc_op_str) 209 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, misc_op_str); 210 else if (op_str) 211 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 212 else 213 dev_dbg(adev->dev, "MES msg=%d was emitted\n", x_pkt->header.opcode); 214 215 r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout); 216 amdgpu_device_wb_free(adev, fence_offset); 217 if (r < 1) { 218 219 if (misc_op_str) 220 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 221 op_str, misc_op_str); 222 else if (op_str) 223 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 224 op_str); 225 else 226 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 227 x_pkt->header.opcode); 228 229 while (halt_if_hws_hang) 230 schedule(); 231 232 return -ETIMEDOUT; 233 } 234 235 return 0; 236 } 237 238 static int convert_to_mes_queue_type(int queue_type) 239 { 240 if (queue_type == AMDGPU_RING_TYPE_GFX) 241 return MES_QUEUE_TYPE_GFX; 242 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 243 return MES_QUEUE_TYPE_COMPUTE; 244 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 245 return MES_QUEUE_TYPE_SDMA; 246 else 247 BUG(); 248 return -1; 249 } 250 251 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 252 struct mes_add_queue_input *input) 253 { 254 struct amdgpu_device *adev = mes->adev; 255 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 256 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 257 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 258 259 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 260 261 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 262 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 263 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 264 265 mes_add_queue_pkt.process_id = input->process_id; 266 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 267 mes_add_queue_pkt.process_va_start = input->process_va_start; 268 mes_add_queue_pkt.process_va_end = input->process_va_end; 269 mes_add_queue_pkt.process_quantum = input->process_quantum; 270 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 271 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 272 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 273 mes_add_queue_pkt.inprocess_gang_priority = 274 input->inprocess_gang_priority; 275 mes_add_queue_pkt.gang_global_priority_level = 276 input->gang_global_priority_level; 277 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 278 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 279 280 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 281 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 282 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 283 else 284 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 285 286 mes_add_queue_pkt.queue_type = 287 convert_to_mes_queue_type(input->queue_type); 288 mes_add_queue_pkt.paging = input->paging; 289 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 290 mes_add_queue_pkt.gws_base = input->gws_base; 291 mes_add_queue_pkt.gws_size = input->gws_size; 292 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 293 mes_add_queue_pkt.tma_addr = input->tma_addr; 294 mes_add_queue_pkt.trap_en = input->trap_en; 295 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 296 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 297 298 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 299 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 300 mes_add_queue_pkt.gds_size = input->queue_size; 301 302 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 303 304 return mes_v11_0_submit_pkt_and_poll_completion(mes, 305 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 306 offsetof(union MESAPI__ADD_QUEUE, api_status)); 307 } 308 309 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 310 struct mes_remove_queue_input *input) 311 { 312 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 313 314 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 315 316 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 317 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 318 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 319 320 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 321 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 322 323 return mes_v11_0_submit_pkt_and_poll_completion(mes, 324 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 325 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 326 } 327 328 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 329 struct mes_map_legacy_queue_input *input) 330 { 331 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 332 333 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 334 335 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 336 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 337 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 338 339 mes_add_queue_pkt.pipe_id = input->pipe_id; 340 mes_add_queue_pkt.queue_id = input->queue_id; 341 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 342 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 343 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 344 mes_add_queue_pkt.queue_type = 345 convert_to_mes_queue_type(input->queue_type); 346 mes_add_queue_pkt.map_legacy_kq = 1; 347 348 return mes_v11_0_submit_pkt_and_poll_completion(mes, 349 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 350 offsetof(union MESAPI__ADD_QUEUE, api_status)); 351 } 352 353 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 354 struct mes_unmap_legacy_queue_input *input) 355 { 356 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 357 358 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 359 360 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 361 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 362 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 363 364 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 365 mes_remove_queue_pkt.gang_context_addr = 0; 366 367 mes_remove_queue_pkt.pipe_id = input->pipe_id; 368 mes_remove_queue_pkt.queue_id = input->queue_id; 369 370 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 371 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 372 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 373 mes_remove_queue_pkt.tf_data = 374 lower_32_bits(input->trail_fence_data); 375 } else { 376 mes_remove_queue_pkt.unmap_legacy_queue = 1; 377 mes_remove_queue_pkt.queue_type = 378 convert_to_mes_queue_type(input->queue_type); 379 } 380 381 return mes_v11_0_submit_pkt_and_poll_completion(mes, 382 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 383 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 384 } 385 386 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 387 struct mes_suspend_gang_input *input) 388 { 389 return 0; 390 } 391 392 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 393 struct mes_resume_gang_input *input) 394 { 395 return 0; 396 } 397 398 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 399 { 400 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 401 402 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 403 404 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 405 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 406 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 407 408 return mes_v11_0_submit_pkt_and_poll_completion(mes, 409 &mes_status_pkt, sizeof(mes_status_pkt), 410 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 411 } 412 413 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 414 struct mes_misc_op_input *input) 415 { 416 union MESAPI__MISC misc_pkt; 417 418 memset(&misc_pkt, 0, sizeof(misc_pkt)); 419 420 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 421 misc_pkt.header.opcode = MES_SCH_API_MISC; 422 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 423 424 switch (input->op) { 425 case MES_MISC_OP_READ_REG: 426 misc_pkt.opcode = MESAPI_MISC__READ_REG; 427 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 428 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 429 break; 430 case MES_MISC_OP_WRITE_REG: 431 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 432 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 433 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 434 break; 435 case MES_MISC_OP_WRM_REG_WAIT: 436 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 437 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 438 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 439 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 440 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 441 misc_pkt.wait_reg_mem.reg_offset2 = 0; 442 break; 443 case MES_MISC_OP_WRM_REG_WR_WAIT: 444 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 445 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 446 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 447 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 448 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 449 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 450 break; 451 case MES_MISC_OP_SET_SHADER_DEBUGGER: 452 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 453 misc_pkt.set_shader_debugger.process_context_addr = 454 input->set_shader_debugger.process_context_addr; 455 misc_pkt.set_shader_debugger.flags.u32all = 456 input->set_shader_debugger.flags.u32all; 457 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 458 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 459 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 460 input->set_shader_debugger.tcp_watch_cntl, 461 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 462 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 463 break; 464 default: 465 DRM_ERROR("unsupported misc op (%d) \n", input->op); 466 return -EINVAL; 467 } 468 469 return mes_v11_0_submit_pkt_and_poll_completion(mes, 470 &misc_pkt, sizeof(misc_pkt), 471 offsetof(union MESAPI__MISC, api_status)); 472 } 473 474 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 475 { 476 int i; 477 struct amdgpu_device *adev = mes->adev; 478 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 479 480 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 481 482 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 483 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 484 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 485 486 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 487 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 488 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 489 mes_set_hw_res_pkt.paging_vmid = 0; 490 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 491 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 492 mes->query_status_fence_gpu_addr; 493 494 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 495 mes_set_hw_res_pkt.compute_hqd_mask[i] = 496 mes->compute_hqd_mask[i]; 497 498 for (i = 0; i < MAX_GFX_PIPES; i++) 499 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 500 501 for (i = 0; i < MAX_SDMA_PIPES; i++) 502 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 503 504 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 505 mes_set_hw_res_pkt.aggregated_doorbells[i] = 506 mes->aggregated_doorbells[i]; 507 508 for (i = 0; i < 5; i++) { 509 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 510 mes_set_hw_res_pkt.mmhub_base[i] = 511 adev->reg_offset[MMHUB_HWIP][0][i]; 512 mes_set_hw_res_pkt.osssys_base[i] = 513 adev->reg_offset[OSSSYS_HWIP][0][i]; 514 } 515 516 mes_set_hw_res_pkt.disable_reset = 1; 517 mes_set_hw_res_pkt.disable_mes_log = 1; 518 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 519 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 520 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 521 mes_set_hw_res_pkt.oversubscription_timer = 50; 522 if (amdgpu_mes_log_enable) { 523 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 524 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 525 mes->event_log_gpu_addr; 526 } 527 528 return mes_v11_0_submit_pkt_and_poll_completion(mes, 529 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 530 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 531 } 532 533 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 534 { 535 int size = 128 * PAGE_SIZE; 536 int ret = 0; 537 struct amdgpu_device *adev = mes->adev; 538 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 539 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 540 541 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 542 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 543 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 544 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 545 546 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 547 AMDGPU_GEM_DOMAIN_VRAM, 548 &mes->resource_1, 549 &mes->resource_1_gpu_addr, 550 &mes->resource_1_addr); 551 if (ret) { 552 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 553 return ret; 554 } 555 556 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 557 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 558 return mes_v11_0_submit_pkt_and_poll_completion(mes, 559 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 560 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 561 } 562 563 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 564 .add_hw_queue = mes_v11_0_add_hw_queue, 565 .remove_hw_queue = mes_v11_0_remove_hw_queue, 566 .map_legacy_queue = mes_v11_0_map_legacy_queue, 567 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 568 .suspend_gang = mes_v11_0_suspend_gang, 569 .resume_gang = mes_v11_0_resume_gang, 570 .misc_op = mes_v11_0_misc_op, 571 }; 572 573 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 574 enum admgpu_mes_pipe pipe) 575 { 576 int r; 577 const struct mes_firmware_header_v1_0 *mes_hdr; 578 const __le32 *fw_data; 579 unsigned fw_size; 580 581 mes_hdr = (const struct mes_firmware_header_v1_0 *) 582 adev->mes.fw[pipe]->data; 583 584 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 585 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 586 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 587 588 r = amdgpu_bo_create_reserved(adev, fw_size, 589 PAGE_SIZE, 590 AMDGPU_GEM_DOMAIN_VRAM | 591 AMDGPU_GEM_DOMAIN_GTT, 592 &adev->mes.ucode_fw_obj[pipe], 593 &adev->mes.ucode_fw_gpu_addr[pipe], 594 (void **)&adev->mes.ucode_fw_ptr[pipe]); 595 if (r) { 596 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 597 return r; 598 } 599 600 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 601 602 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 603 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 604 605 return 0; 606 } 607 608 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 609 enum admgpu_mes_pipe pipe) 610 { 611 int r; 612 const struct mes_firmware_header_v1_0 *mes_hdr; 613 const __le32 *fw_data; 614 unsigned fw_size; 615 616 mes_hdr = (const struct mes_firmware_header_v1_0 *) 617 adev->mes.fw[pipe]->data; 618 619 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 620 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 621 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 622 623 if (fw_size > GFX_MES_DRAM_SIZE) { 624 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 625 pipe, fw_size, GFX_MES_DRAM_SIZE); 626 return -EINVAL; 627 } 628 629 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 630 64 * 1024, 631 AMDGPU_GEM_DOMAIN_VRAM | 632 AMDGPU_GEM_DOMAIN_GTT, 633 &adev->mes.data_fw_obj[pipe], 634 &adev->mes.data_fw_gpu_addr[pipe], 635 (void **)&adev->mes.data_fw_ptr[pipe]); 636 if (r) { 637 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 638 return r; 639 } 640 641 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 642 643 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 644 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 645 646 return 0; 647 } 648 649 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 650 enum admgpu_mes_pipe pipe) 651 { 652 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 653 &adev->mes.data_fw_gpu_addr[pipe], 654 (void **)&adev->mes.data_fw_ptr[pipe]); 655 656 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 657 &adev->mes.ucode_fw_gpu_addr[pipe], 658 (void **)&adev->mes.ucode_fw_ptr[pipe]); 659 } 660 661 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 662 { 663 uint64_t ucode_addr; 664 uint32_t pipe, data = 0; 665 666 if (enable) { 667 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 668 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 669 data = REG_SET_FIELD(data, CP_MES_CNTL, 670 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 671 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 672 673 mutex_lock(&adev->srbm_mutex); 674 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 675 if (!adev->enable_mes_kiq && 676 pipe == AMDGPU_MES_KIQ_PIPE) 677 continue; 678 679 soc21_grbm_select(adev, 3, pipe, 0, 0); 680 681 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 682 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 683 lower_32_bits(ucode_addr)); 684 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 685 upper_32_bits(ucode_addr)); 686 } 687 soc21_grbm_select(adev, 0, 0, 0, 0); 688 mutex_unlock(&adev->srbm_mutex); 689 690 /* unhalt MES and activate pipe0 */ 691 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 692 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 693 adev->enable_mes_kiq ? 1 : 0); 694 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 695 696 if (amdgpu_emu_mode) 697 msleep(100); 698 else 699 udelay(500); 700 } else { 701 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 702 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 703 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 704 data = REG_SET_FIELD(data, CP_MES_CNTL, 705 MES_INVALIDATE_ICACHE, 1); 706 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 707 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 708 adev->enable_mes_kiq ? 1 : 0); 709 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 710 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 711 } 712 } 713 714 /* This function is for backdoor MES firmware */ 715 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 716 enum admgpu_mes_pipe pipe, bool prime_icache) 717 { 718 int r; 719 uint32_t data; 720 uint64_t ucode_addr; 721 722 mes_v11_0_enable(adev, false); 723 724 if (!adev->mes.fw[pipe]) 725 return -EINVAL; 726 727 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 728 if (r) 729 return r; 730 731 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 732 if (r) { 733 mes_v11_0_free_ucode_buffers(adev, pipe); 734 return r; 735 } 736 737 mutex_lock(&adev->srbm_mutex); 738 /* me=3, pipe=0, queue=0 */ 739 soc21_grbm_select(adev, 3, pipe, 0, 0); 740 741 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 742 743 /* set ucode start address */ 744 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 745 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 746 lower_32_bits(ucode_addr)); 747 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 748 upper_32_bits(ucode_addr)); 749 750 /* set ucode fimrware address */ 751 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 752 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 753 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 754 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 755 756 /* set ucode instruction cache boundary to 2M-1 */ 757 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 758 759 /* set ucode data firmware address */ 760 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 761 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 762 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 763 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 764 765 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 766 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 767 768 if (prime_icache) { 769 /* invalidate ICACHE */ 770 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 771 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 772 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 773 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 774 775 /* prime the ICACHE. */ 776 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 777 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 778 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 779 } 780 781 soc21_grbm_select(adev, 0, 0, 0, 0); 782 mutex_unlock(&adev->srbm_mutex); 783 784 return 0; 785 } 786 787 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 788 enum admgpu_mes_pipe pipe) 789 { 790 int r; 791 u32 *eop; 792 793 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 794 AMDGPU_GEM_DOMAIN_GTT, 795 &adev->mes.eop_gpu_obj[pipe], 796 &adev->mes.eop_gpu_addr[pipe], 797 (void **)&eop); 798 if (r) { 799 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 800 return r; 801 } 802 803 memset(eop, 0, 804 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 805 806 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 807 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 808 809 return 0; 810 } 811 812 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 813 { 814 struct v11_compute_mqd *mqd = ring->mqd_ptr; 815 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 816 uint32_t tmp; 817 818 memset(mqd, 0, sizeof(*mqd)); 819 820 mqd->header = 0xC0310800; 821 mqd->compute_pipelinestat_enable = 0x00000001; 822 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 823 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 824 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 825 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 826 mqd->compute_misc_reserved = 0x00000007; 827 828 eop_base_addr = ring->eop_gpu_addr >> 8; 829 830 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 831 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 832 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 833 (order_base_2(MES_EOP_SIZE / 4) - 1)); 834 835 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 836 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 837 mqd->cp_hqd_eop_control = tmp; 838 839 /* disable the queue if it's active */ 840 ring->wptr = 0; 841 mqd->cp_hqd_pq_rptr = 0; 842 mqd->cp_hqd_pq_wptr_lo = 0; 843 mqd->cp_hqd_pq_wptr_hi = 0; 844 845 /* set the pointer to the MQD */ 846 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 847 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 848 849 /* set MQD vmid to 0 */ 850 tmp = regCP_MQD_CONTROL_DEFAULT; 851 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 852 mqd->cp_mqd_control = tmp; 853 854 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 855 hqd_gpu_addr = ring->gpu_addr >> 8; 856 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 857 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 858 859 /* set the wb address whether it's enabled or not */ 860 wb_gpu_addr = ring->rptr_gpu_addr; 861 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 862 mqd->cp_hqd_pq_rptr_report_addr_hi = 863 upper_32_bits(wb_gpu_addr) & 0xffff; 864 865 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 866 wb_gpu_addr = ring->wptr_gpu_addr; 867 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 868 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 869 870 /* set up the HQD, this is similar to CP_RB0_CNTL */ 871 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 872 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 873 (order_base_2(ring->ring_size / 4) - 1)); 874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 875 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 876 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 877 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 878 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 880 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 881 mqd->cp_hqd_pq_control = tmp; 882 883 /* enable doorbell */ 884 tmp = 0; 885 if (ring->use_doorbell) { 886 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 887 DOORBELL_OFFSET, ring->doorbell_index); 888 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 889 DOORBELL_EN, 1); 890 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 891 DOORBELL_SOURCE, 0); 892 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 893 DOORBELL_HIT, 0); 894 } else 895 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 896 DOORBELL_EN, 0); 897 mqd->cp_hqd_pq_doorbell_control = tmp; 898 899 mqd->cp_hqd_vmid = 0; 900 /* activate the queue */ 901 mqd->cp_hqd_active = 1; 902 903 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 904 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 905 PRELOAD_SIZE, 0x55); 906 mqd->cp_hqd_persistent_state = tmp; 907 908 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 909 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 910 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 911 912 amdgpu_device_flush_hdp(ring->adev, NULL); 913 return 0; 914 } 915 916 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 917 { 918 struct v11_compute_mqd *mqd = ring->mqd_ptr; 919 struct amdgpu_device *adev = ring->adev; 920 uint32_t data = 0; 921 922 mutex_lock(&adev->srbm_mutex); 923 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 924 925 /* set CP_HQD_VMID.VMID = 0. */ 926 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 927 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 928 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 929 930 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 931 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 932 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 933 DOORBELL_EN, 0); 934 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 935 936 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 937 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 938 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 939 940 /* set CP_MQD_CONTROL.VMID=0 */ 941 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 942 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 943 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 944 945 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 946 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 947 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 948 949 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 950 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 951 mqd->cp_hqd_pq_rptr_report_addr_lo); 952 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 953 mqd->cp_hqd_pq_rptr_report_addr_hi); 954 955 /* set CP_HQD_PQ_CONTROL */ 956 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 957 958 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 959 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 960 mqd->cp_hqd_pq_wptr_poll_addr_lo); 961 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 962 mqd->cp_hqd_pq_wptr_poll_addr_hi); 963 964 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 965 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 966 mqd->cp_hqd_pq_doorbell_control); 967 968 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 969 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 970 971 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 972 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 973 974 soc21_grbm_select(adev, 0, 0, 0, 0); 975 mutex_unlock(&adev->srbm_mutex); 976 } 977 978 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 979 { 980 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 981 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 982 int r; 983 984 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 985 return -EINVAL; 986 987 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 988 if (r) { 989 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 990 return r; 991 } 992 993 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 994 995 return amdgpu_ring_test_helper(kiq_ring); 996 } 997 998 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 999 enum admgpu_mes_pipe pipe) 1000 { 1001 struct amdgpu_ring *ring; 1002 int r; 1003 1004 if (pipe == AMDGPU_MES_KIQ_PIPE) 1005 ring = &adev->gfx.kiq[0].ring; 1006 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1007 ring = &adev->mes.ring; 1008 else 1009 BUG(); 1010 1011 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1012 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1013 *(ring->wptr_cpu_addr) = 0; 1014 *(ring->rptr_cpu_addr) = 0; 1015 amdgpu_ring_clear_ring(ring); 1016 } 1017 1018 r = mes_v11_0_mqd_init(ring); 1019 if (r) 1020 return r; 1021 1022 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1023 r = mes_v11_0_kiq_enable_queue(adev); 1024 if (r) 1025 return r; 1026 } else { 1027 mes_v11_0_queue_init_register(ring); 1028 } 1029 1030 /* get MES scheduler/KIQ versions */ 1031 mutex_lock(&adev->srbm_mutex); 1032 soc21_grbm_select(adev, 3, pipe, 0, 0); 1033 1034 if (pipe == AMDGPU_MES_SCHED_PIPE) 1035 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1036 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1037 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1038 1039 soc21_grbm_select(adev, 0, 0, 0, 0); 1040 mutex_unlock(&adev->srbm_mutex); 1041 1042 return 0; 1043 } 1044 1045 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1046 { 1047 struct amdgpu_ring *ring; 1048 1049 ring = &adev->mes.ring; 1050 1051 ring->funcs = &mes_v11_0_ring_funcs; 1052 1053 ring->me = 3; 1054 ring->pipe = 0; 1055 ring->queue = 0; 1056 1057 ring->ring_obj = NULL; 1058 ring->use_doorbell = true; 1059 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1060 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1061 ring->no_scheduler = true; 1062 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1063 1064 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1065 AMDGPU_RING_PRIO_DEFAULT, NULL); 1066 } 1067 1068 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1069 { 1070 struct amdgpu_ring *ring; 1071 1072 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1073 1074 ring = &adev->gfx.kiq[0].ring; 1075 1076 ring->me = 3; 1077 ring->pipe = 1; 1078 ring->queue = 0; 1079 1080 ring->adev = NULL; 1081 ring->ring_obj = NULL; 1082 ring->use_doorbell = true; 1083 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1084 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1085 ring->no_scheduler = true; 1086 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1087 ring->me, ring->pipe, ring->queue); 1088 1089 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1090 AMDGPU_RING_PRIO_DEFAULT, NULL); 1091 } 1092 1093 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1094 enum admgpu_mes_pipe pipe) 1095 { 1096 int r, mqd_size = sizeof(struct v11_compute_mqd); 1097 struct amdgpu_ring *ring; 1098 1099 if (pipe == AMDGPU_MES_KIQ_PIPE) 1100 ring = &adev->gfx.kiq[0].ring; 1101 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1102 ring = &adev->mes.ring; 1103 else 1104 BUG(); 1105 1106 if (ring->mqd_obj) 1107 return 0; 1108 1109 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1110 AMDGPU_GEM_DOMAIN_VRAM | 1111 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1112 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1113 if (r) { 1114 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1115 return r; 1116 } 1117 1118 memset(ring->mqd_ptr, 0, mqd_size); 1119 1120 /* prepare MQD backup */ 1121 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1122 if (!adev->mes.mqd_backup[pipe]) { 1123 dev_warn(adev->dev, 1124 "no memory to create MQD backup for ring %s\n", 1125 ring->name); 1126 return -ENOMEM; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int mes_v11_0_sw_init(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 int pipe, r; 1136 1137 adev->mes.funcs = &mes_v11_0_funcs; 1138 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1139 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1140 1141 r = amdgpu_mes_init(adev); 1142 if (r) 1143 return r; 1144 1145 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1146 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1147 continue; 1148 1149 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1150 if (r) 1151 return r; 1152 1153 r = mes_v11_0_mqd_sw_init(adev, pipe); 1154 if (r) 1155 return r; 1156 } 1157 1158 if (adev->enable_mes_kiq) { 1159 r = mes_v11_0_kiq_ring_init(adev); 1160 if (r) 1161 return r; 1162 } 1163 1164 r = mes_v11_0_ring_init(adev); 1165 if (r) 1166 return r; 1167 1168 return 0; 1169 } 1170 1171 static int mes_v11_0_sw_fini(void *handle) 1172 { 1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1174 int pipe; 1175 1176 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1177 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1178 1179 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1180 kfree(adev->mes.mqd_backup[pipe]); 1181 1182 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1183 &adev->mes.eop_gpu_addr[pipe], 1184 NULL); 1185 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1186 } 1187 1188 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1189 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1190 &adev->gfx.kiq[0].ring.mqd_ptr); 1191 1192 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1193 &adev->mes.ring.mqd_gpu_addr, 1194 &adev->mes.ring.mqd_ptr); 1195 1196 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1197 amdgpu_ring_fini(&adev->mes.ring); 1198 1199 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1200 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1201 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1202 } 1203 1204 amdgpu_mes_fini(adev); 1205 return 0; 1206 } 1207 1208 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1209 { 1210 uint32_t data; 1211 int i; 1212 struct amdgpu_device *adev = ring->adev; 1213 1214 mutex_lock(&adev->srbm_mutex); 1215 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1216 1217 /* disable the queue if it's active */ 1218 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1219 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1220 for (i = 0; i < adev->usec_timeout; i++) { 1221 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1222 break; 1223 udelay(1); 1224 } 1225 } 1226 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1227 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1228 DOORBELL_EN, 0); 1229 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1230 DOORBELL_HIT, 1); 1231 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1232 1233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1234 1235 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1236 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1237 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1238 1239 soc21_grbm_select(adev, 0, 0, 0, 0); 1240 mutex_unlock(&adev->srbm_mutex); 1241 } 1242 1243 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1244 { 1245 uint32_t tmp; 1246 struct amdgpu_device *adev = ring->adev; 1247 1248 /* tell RLC which is KIQ queue */ 1249 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1250 tmp &= 0xffffff00; 1251 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1252 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1253 tmp |= 0x80; 1254 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1255 } 1256 1257 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1258 { 1259 uint32_t tmp; 1260 1261 /* tell RLC which is KIQ dequeue */ 1262 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1263 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1264 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1265 } 1266 1267 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1268 { 1269 int r = 0; 1270 1271 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1272 1273 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1274 if (r) { 1275 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1276 return r; 1277 } 1278 1279 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1280 if (r) { 1281 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1282 return r; 1283 } 1284 1285 } 1286 1287 mes_v11_0_enable(adev, true); 1288 1289 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1290 1291 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1292 if (r) 1293 goto failure; 1294 1295 r = mes_v11_0_hw_init(adev); 1296 if (r) 1297 goto failure; 1298 1299 return r; 1300 1301 failure: 1302 mes_v11_0_hw_fini(adev); 1303 return r; 1304 } 1305 1306 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1307 { 1308 if (adev->mes.ring.sched.ready) { 1309 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1310 adev->mes.ring.sched.ready = false; 1311 } 1312 1313 if (amdgpu_sriov_vf(adev)) { 1314 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1315 mes_v11_0_kiq_clear(adev); 1316 } 1317 1318 mes_v11_0_enable(adev, false); 1319 1320 return 0; 1321 } 1322 1323 static int mes_v11_0_hw_init(void *handle) 1324 { 1325 int r; 1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1327 1328 if (adev->mes.ring.sched.ready) 1329 goto out; 1330 1331 if (!adev->enable_mes_kiq) { 1332 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1333 r = mes_v11_0_load_microcode(adev, 1334 AMDGPU_MES_SCHED_PIPE, true); 1335 if (r) { 1336 DRM_ERROR("failed to MES fw, r=%d\n", r); 1337 return r; 1338 } 1339 } 1340 1341 mes_v11_0_enable(adev, true); 1342 } 1343 1344 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1345 if (r) 1346 goto failure; 1347 1348 r = mes_v11_0_set_hw_resources(&adev->mes); 1349 if (r) 1350 goto failure; 1351 1352 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1353 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1354 if (r) { 1355 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1356 goto failure; 1357 } 1358 } 1359 1360 r = mes_v11_0_query_sched_status(&adev->mes); 1361 if (r) { 1362 DRM_ERROR("MES is busy\n"); 1363 goto failure; 1364 } 1365 1366 out: 1367 /* 1368 * Disable KIQ ring usage from the driver once MES is enabled. 1369 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1370 * with MES enabled. 1371 */ 1372 adev->gfx.kiq[0].ring.sched.ready = false; 1373 adev->mes.ring.sched.ready = true; 1374 1375 return 0; 1376 1377 failure: 1378 mes_v11_0_hw_fini(adev); 1379 return r; 1380 } 1381 1382 static int mes_v11_0_hw_fini(void *handle) 1383 { 1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1385 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1386 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1387 &adev->mes.resource_1_addr); 1388 } 1389 return 0; 1390 } 1391 1392 static int mes_v11_0_suspend(void *handle) 1393 { 1394 int r; 1395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1396 1397 r = amdgpu_mes_suspend(adev); 1398 if (r) 1399 return r; 1400 1401 return mes_v11_0_hw_fini(adev); 1402 } 1403 1404 static int mes_v11_0_resume(void *handle) 1405 { 1406 int r; 1407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1408 1409 r = mes_v11_0_hw_init(adev); 1410 if (r) 1411 return r; 1412 1413 return amdgpu_mes_resume(adev); 1414 } 1415 1416 static int mes_v11_0_early_init(void *handle) 1417 { 1418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1419 int pipe, r; 1420 1421 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1422 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1423 continue; 1424 r = amdgpu_mes_init_microcode(adev, pipe); 1425 if (r) 1426 return r; 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int mes_v11_0_late_init(void *handle) 1433 { 1434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1435 1436 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1437 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1438 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1439 amdgpu_mes_self_test(adev); 1440 1441 return 0; 1442 } 1443 1444 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1445 .name = "mes_v11_0", 1446 .early_init = mes_v11_0_early_init, 1447 .late_init = mes_v11_0_late_init, 1448 .sw_init = mes_v11_0_sw_init, 1449 .sw_fini = mes_v11_0_sw_fini, 1450 .hw_init = mes_v11_0_hw_init, 1451 .hw_fini = mes_v11_0_hw_fini, 1452 .suspend = mes_v11_0_suspend, 1453 .resume = mes_v11_0_resume, 1454 .dump_ip_state = NULL, 1455 .print_ip_state = NULL, 1456 }; 1457 1458 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1459 .type = AMD_IP_BLOCK_TYPE_MES, 1460 .major = 11, 1461 .minor = 0, 1462 .rev = 0, 1463 .funcs = &mes_v11_0_ip_funcs, 1464 }; 1465