1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 53 54 static int mes_v11_0_hw_fini(void *handle); 55 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 56 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 57 58 #define MES_EOP_SIZE 2048 59 60 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 61 { 62 struct amdgpu_device *adev = ring->adev; 63 64 if (ring->use_doorbell) { 65 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 66 ring->wptr); 67 WDOORBELL64(ring->doorbell_index, ring->wptr); 68 } else { 69 BUG(); 70 } 71 } 72 73 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 74 { 75 return *ring->rptr_cpu_addr; 76 } 77 78 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 79 { 80 u64 wptr; 81 82 if (ring->use_doorbell) 83 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 84 else 85 BUG(); 86 return wptr; 87 } 88 89 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 90 .type = AMDGPU_RING_TYPE_MES, 91 .align_mask = 1, 92 .nop = 0, 93 .support_64bit_ptrs = true, 94 .get_rptr = mes_v11_0_ring_get_rptr, 95 .get_wptr = mes_v11_0_ring_get_wptr, 96 .set_wptr = mes_v11_0_ring_set_wptr, 97 .insert_nop = amdgpu_ring_insert_nop, 98 }; 99 100 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 101 void *pkt, int size, 102 int api_status_off) 103 { 104 int ndw = size / 4; 105 signed long r; 106 union MESAPI__ADD_QUEUE *x_pkt = pkt; 107 struct MES_API_STATUS *api_status; 108 struct amdgpu_device *adev = mes->adev; 109 struct amdgpu_ring *ring = &mes->ring; 110 unsigned long flags; 111 signed long timeout = adev->usec_timeout; 112 113 if (amdgpu_emu_mode) { 114 timeout *= 100; 115 } else if (amdgpu_sriov_vf(adev)) { 116 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 117 timeout = 15 * 600 * 1000; 118 } 119 BUG_ON(size % 4 != 0); 120 121 spin_lock_irqsave(&mes->ring_lock, flags); 122 if (amdgpu_ring_alloc(ring, ndw)) { 123 spin_unlock_irqrestore(&mes->ring_lock, flags); 124 return -ENOMEM; 125 } 126 127 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 128 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 129 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 130 131 amdgpu_ring_write_multiple(ring, pkt, ndw); 132 amdgpu_ring_commit(ring); 133 spin_unlock_irqrestore(&mes->ring_lock, flags); 134 135 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 136 137 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 138 timeout); 139 if (r < 1) { 140 DRM_ERROR("MES failed to response msg=%d\n", 141 x_pkt->header.opcode); 142 143 while (halt_if_hws_hang) 144 schedule(); 145 146 return -ETIMEDOUT; 147 } 148 149 return 0; 150 } 151 152 static int convert_to_mes_queue_type(int queue_type) 153 { 154 if (queue_type == AMDGPU_RING_TYPE_GFX) 155 return MES_QUEUE_TYPE_GFX; 156 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 157 return MES_QUEUE_TYPE_COMPUTE; 158 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 159 return MES_QUEUE_TYPE_SDMA; 160 else 161 BUG(); 162 return -1; 163 } 164 165 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 166 struct mes_add_queue_input *input) 167 { 168 struct amdgpu_device *adev = mes->adev; 169 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 170 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 171 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 172 173 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 174 175 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 176 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 177 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 178 179 mes_add_queue_pkt.process_id = input->process_id; 180 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 181 mes_add_queue_pkt.process_va_start = input->process_va_start; 182 mes_add_queue_pkt.process_va_end = input->process_va_end; 183 mes_add_queue_pkt.process_quantum = input->process_quantum; 184 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 185 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 186 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 187 mes_add_queue_pkt.inprocess_gang_priority = 188 input->inprocess_gang_priority; 189 mes_add_queue_pkt.gang_global_priority_level = 190 input->gang_global_priority_level; 191 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 192 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 193 194 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 195 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 196 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 197 else 198 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 199 200 mes_add_queue_pkt.queue_type = 201 convert_to_mes_queue_type(input->queue_type); 202 mes_add_queue_pkt.paging = input->paging; 203 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 204 mes_add_queue_pkt.gws_base = input->gws_base; 205 mes_add_queue_pkt.gws_size = input->gws_size; 206 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 207 mes_add_queue_pkt.tma_addr = input->tma_addr; 208 mes_add_queue_pkt.trap_en = input->trap_en; 209 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 210 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 211 212 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 213 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 214 mes_add_queue_pkt.gds_size = input->queue_size; 215 216 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 217 218 return mes_v11_0_submit_pkt_and_poll_completion(mes, 219 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 220 offsetof(union MESAPI__ADD_QUEUE, api_status)); 221 } 222 223 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 224 struct mes_remove_queue_input *input) 225 { 226 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 227 228 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 229 230 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 231 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 232 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 233 234 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 235 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 236 237 return mes_v11_0_submit_pkt_and_poll_completion(mes, 238 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 239 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 240 } 241 242 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 243 struct mes_unmap_legacy_queue_input *input) 244 { 245 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 246 247 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 248 249 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 250 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 251 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 252 253 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 254 mes_remove_queue_pkt.gang_context_addr = 0; 255 256 mes_remove_queue_pkt.pipe_id = input->pipe_id; 257 mes_remove_queue_pkt.queue_id = input->queue_id; 258 259 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 260 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 261 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 262 mes_remove_queue_pkt.tf_data = 263 lower_32_bits(input->trail_fence_data); 264 } else { 265 mes_remove_queue_pkt.unmap_legacy_queue = 1; 266 mes_remove_queue_pkt.queue_type = 267 convert_to_mes_queue_type(input->queue_type); 268 } 269 270 return mes_v11_0_submit_pkt_and_poll_completion(mes, 271 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 272 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 273 } 274 275 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 276 struct mes_suspend_gang_input *input) 277 { 278 return 0; 279 } 280 281 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 282 struct mes_resume_gang_input *input) 283 { 284 return 0; 285 } 286 287 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 288 { 289 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 290 291 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 292 293 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 294 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 295 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 296 297 return mes_v11_0_submit_pkt_and_poll_completion(mes, 298 &mes_status_pkt, sizeof(mes_status_pkt), 299 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 300 } 301 302 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 303 struct mes_misc_op_input *input) 304 { 305 union MESAPI__MISC misc_pkt; 306 307 memset(&misc_pkt, 0, sizeof(misc_pkt)); 308 309 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 310 misc_pkt.header.opcode = MES_SCH_API_MISC; 311 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 312 313 switch (input->op) { 314 case MES_MISC_OP_READ_REG: 315 misc_pkt.opcode = MESAPI_MISC__READ_REG; 316 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 317 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 318 break; 319 case MES_MISC_OP_WRITE_REG: 320 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 321 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 322 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 323 break; 324 case MES_MISC_OP_WRM_REG_WAIT: 325 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 326 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 327 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 328 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 329 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 330 misc_pkt.wait_reg_mem.reg_offset2 = 0; 331 break; 332 case MES_MISC_OP_WRM_REG_WR_WAIT: 333 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 334 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 335 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 336 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 337 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 338 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 339 break; 340 case MES_MISC_OP_SET_SHADER_DEBUGGER: 341 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 342 misc_pkt.set_shader_debugger.process_context_addr = 343 input->set_shader_debugger.process_context_addr; 344 misc_pkt.set_shader_debugger.flags.u32all = 345 input->set_shader_debugger.flags.u32all; 346 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 347 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 348 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 349 input->set_shader_debugger.tcp_watch_cntl, 350 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 351 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 352 break; 353 default: 354 DRM_ERROR("unsupported misc op (%d) \n", input->op); 355 return -EINVAL; 356 } 357 358 return mes_v11_0_submit_pkt_and_poll_completion(mes, 359 &misc_pkt, sizeof(misc_pkt), 360 offsetof(union MESAPI__MISC, api_status)); 361 } 362 363 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 364 { 365 int i; 366 struct amdgpu_device *adev = mes->adev; 367 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 368 369 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 370 371 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 372 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 373 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 374 375 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 376 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 377 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 378 mes_set_hw_res_pkt.paging_vmid = 0; 379 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 380 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 381 mes->query_status_fence_gpu_addr; 382 383 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 384 mes_set_hw_res_pkt.compute_hqd_mask[i] = 385 mes->compute_hqd_mask[i]; 386 387 for (i = 0; i < MAX_GFX_PIPES; i++) 388 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 389 390 for (i = 0; i < MAX_SDMA_PIPES; i++) 391 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 392 393 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 394 mes_set_hw_res_pkt.aggregated_doorbells[i] = 395 mes->aggregated_doorbells[i]; 396 397 for (i = 0; i < 5; i++) { 398 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 399 mes_set_hw_res_pkt.mmhub_base[i] = 400 adev->reg_offset[MMHUB_HWIP][0][i]; 401 mes_set_hw_res_pkt.osssys_base[i] = 402 adev->reg_offset[OSSSYS_HWIP][0][i]; 403 } 404 405 mes_set_hw_res_pkt.disable_reset = 1; 406 mes_set_hw_res_pkt.disable_mes_log = 1; 407 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 408 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 409 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 410 mes_set_hw_res_pkt.oversubscription_timer = 50; 411 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 412 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 413 414 return mes_v11_0_submit_pkt_and_poll_completion(mes, 415 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 416 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 417 } 418 419 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 420 .add_hw_queue = mes_v11_0_add_hw_queue, 421 .remove_hw_queue = mes_v11_0_remove_hw_queue, 422 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 423 .suspend_gang = mes_v11_0_suspend_gang, 424 .resume_gang = mes_v11_0_resume_gang, 425 .misc_op = mes_v11_0_misc_op, 426 }; 427 428 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 429 enum admgpu_mes_pipe pipe) 430 { 431 int r; 432 const struct mes_firmware_header_v1_0 *mes_hdr; 433 const __le32 *fw_data; 434 unsigned fw_size; 435 436 mes_hdr = (const struct mes_firmware_header_v1_0 *) 437 adev->mes.fw[pipe]->data; 438 439 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 440 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 441 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 442 443 r = amdgpu_bo_create_reserved(adev, fw_size, 444 PAGE_SIZE, 445 AMDGPU_GEM_DOMAIN_VRAM | 446 AMDGPU_GEM_DOMAIN_GTT, 447 &adev->mes.ucode_fw_obj[pipe], 448 &adev->mes.ucode_fw_gpu_addr[pipe], 449 (void **)&adev->mes.ucode_fw_ptr[pipe]); 450 if (r) { 451 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 452 return r; 453 } 454 455 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 456 457 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 458 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 459 460 return 0; 461 } 462 463 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 464 enum admgpu_mes_pipe pipe) 465 { 466 int r; 467 const struct mes_firmware_header_v1_0 *mes_hdr; 468 const __le32 *fw_data; 469 unsigned fw_size; 470 471 mes_hdr = (const struct mes_firmware_header_v1_0 *) 472 adev->mes.fw[pipe]->data; 473 474 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 475 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 476 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 477 478 r = amdgpu_bo_create_reserved(adev, fw_size, 479 64 * 1024, 480 AMDGPU_GEM_DOMAIN_VRAM | 481 AMDGPU_GEM_DOMAIN_GTT, 482 &adev->mes.data_fw_obj[pipe], 483 &adev->mes.data_fw_gpu_addr[pipe], 484 (void **)&adev->mes.data_fw_ptr[pipe]); 485 if (r) { 486 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 487 return r; 488 } 489 490 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 491 492 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 493 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 494 495 return 0; 496 } 497 498 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 499 enum admgpu_mes_pipe pipe) 500 { 501 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 502 &adev->mes.data_fw_gpu_addr[pipe], 503 (void **)&adev->mes.data_fw_ptr[pipe]); 504 505 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 506 &adev->mes.ucode_fw_gpu_addr[pipe], 507 (void **)&adev->mes.ucode_fw_ptr[pipe]); 508 } 509 510 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 511 { 512 uint64_t ucode_addr; 513 uint32_t pipe, data = 0; 514 515 if (enable) { 516 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 517 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 518 data = REG_SET_FIELD(data, CP_MES_CNTL, 519 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 520 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 521 522 mutex_lock(&adev->srbm_mutex); 523 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 524 if (!adev->enable_mes_kiq && 525 pipe == AMDGPU_MES_KIQ_PIPE) 526 continue; 527 528 soc21_grbm_select(adev, 3, pipe, 0, 0); 529 530 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 531 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 532 lower_32_bits(ucode_addr)); 533 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 534 upper_32_bits(ucode_addr)); 535 } 536 soc21_grbm_select(adev, 0, 0, 0, 0); 537 mutex_unlock(&adev->srbm_mutex); 538 539 /* unhalt MES and activate pipe0 */ 540 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 541 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 542 adev->enable_mes_kiq ? 1 : 0); 543 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 544 545 if (amdgpu_emu_mode) 546 msleep(100); 547 else 548 udelay(50); 549 } else { 550 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 551 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 552 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 553 data = REG_SET_FIELD(data, CP_MES_CNTL, 554 MES_INVALIDATE_ICACHE, 1); 555 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 556 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 557 adev->enable_mes_kiq ? 1 : 0); 558 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 559 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 560 } 561 } 562 563 /* This function is for backdoor MES firmware */ 564 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 565 enum admgpu_mes_pipe pipe, bool prime_icache) 566 { 567 int r; 568 uint32_t data; 569 uint64_t ucode_addr; 570 571 mes_v11_0_enable(adev, false); 572 573 if (!adev->mes.fw[pipe]) 574 return -EINVAL; 575 576 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 577 if (r) 578 return r; 579 580 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 581 if (r) { 582 mes_v11_0_free_ucode_buffers(adev, pipe); 583 return r; 584 } 585 586 mutex_lock(&adev->srbm_mutex); 587 /* me=3, pipe=0, queue=0 */ 588 soc21_grbm_select(adev, 3, pipe, 0, 0); 589 590 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 591 592 /* set ucode start address */ 593 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 594 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 595 lower_32_bits(ucode_addr)); 596 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 597 upper_32_bits(ucode_addr)); 598 599 /* set ucode fimrware address */ 600 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 601 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 602 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 603 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 604 605 /* set ucode instruction cache boundary to 2M-1 */ 606 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 607 608 /* set ucode data firmware address */ 609 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 610 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 611 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 612 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 613 614 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 615 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 616 617 if (prime_icache) { 618 /* invalidate ICACHE */ 619 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 620 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 621 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 622 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 623 624 /* prime the ICACHE. */ 625 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 626 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 627 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 628 } 629 630 soc21_grbm_select(adev, 0, 0, 0, 0); 631 mutex_unlock(&adev->srbm_mutex); 632 633 return 0; 634 } 635 636 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 637 enum admgpu_mes_pipe pipe) 638 { 639 int r; 640 u32 *eop; 641 642 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 643 AMDGPU_GEM_DOMAIN_GTT, 644 &adev->mes.eop_gpu_obj[pipe], 645 &adev->mes.eop_gpu_addr[pipe], 646 (void **)&eop); 647 if (r) { 648 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 649 return r; 650 } 651 652 memset(eop, 0, 653 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 654 655 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 656 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 657 658 return 0; 659 } 660 661 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 662 { 663 struct v11_compute_mqd *mqd = ring->mqd_ptr; 664 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 665 uint32_t tmp; 666 667 memset(mqd, 0, sizeof(*mqd)); 668 669 mqd->header = 0xC0310800; 670 mqd->compute_pipelinestat_enable = 0x00000001; 671 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 672 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 673 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 674 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 675 mqd->compute_misc_reserved = 0x00000007; 676 677 eop_base_addr = ring->eop_gpu_addr >> 8; 678 679 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 680 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 681 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 682 (order_base_2(MES_EOP_SIZE / 4) - 1)); 683 684 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 685 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 686 mqd->cp_hqd_eop_control = tmp; 687 688 /* disable the queue if it's active */ 689 ring->wptr = 0; 690 mqd->cp_hqd_pq_rptr = 0; 691 mqd->cp_hqd_pq_wptr_lo = 0; 692 mqd->cp_hqd_pq_wptr_hi = 0; 693 694 /* set the pointer to the MQD */ 695 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 696 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 697 698 /* set MQD vmid to 0 */ 699 tmp = regCP_MQD_CONTROL_DEFAULT; 700 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 701 mqd->cp_mqd_control = tmp; 702 703 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 704 hqd_gpu_addr = ring->gpu_addr >> 8; 705 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 706 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 707 708 /* set the wb address whether it's enabled or not */ 709 wb_gpu_addr = ring->rptr_gpu_addr; 710 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 711 mqd->cp_hqd_pq_rptr_report_addr_hi = 712 upper_32_bits(wb_gpu_addr) & 0xffff; 713 714 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 715 wb_gpu_addr = ring->wptr_gpu_addr; 716 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 717 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 718 719 /* set up the HQD, this is similar to CP_RB0_CNTL */ 720 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 721 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 722 (order_base_2(ring->ring_size / 4) - 1)); 723 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 724 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 725 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 726 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 727 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 728 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 729 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 730 mqd->cp_hqd_pq_control = tmp; 731 732 /* enable doorbell */ 733 tmp = 0; 734 if (ring->use_doorbell) { 735 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 736 DOORBELL_OFFSET, ring->doorbell_index); 737 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 738 DOORBELL_EN, 1); 739 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 740 DOORBELL_SOURCE, 0); 741 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 742 DOORBELL_HIT, 0); 743 } else 744 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 745 DOORBELL_EN, 0); 746 mqd->cp_hqd_pq_doorbell_control = tmp; 747 748 mqd->cp_hqd_vmid = 0; 749 /* activate the queue */ 750 mqd->cp_hqd_active = 1; 751 752 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 753 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 754 PRELOAD_SIZE, 0x55); 755 mqd->cp_hqd_persistent_state = tmp; 756 757 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 758 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 759 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 760 761 amdgpu_device_flush_hdp(ring->adev, NULL); 762 return 0; 763 } 764 765 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 766 { 767 struct v11_compute_mqd *mqd = ring->mqd_ptr; 768 struct amdgpu_device *adev = ring->adev; 769 uint32_t data = 0; 770 771 mutex_lock(&adev->srbm_mutex); 772 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 773 774 /* set CP_HQD_VMID.VMID = 0. */ 775 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 776 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 777 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 778 779 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 780 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 781 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 782 DOORBELL_EN, 0); 783 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 784 785 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 786 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 787 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 788 789 /* set CP_MQD_CONTROL.VMID=0 */ 790 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 791 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 792 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 793 794 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 795 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 796 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 797 798 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 799 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 800 mqd->cp_hqd_pq_rptr_report_addr_lo); 801 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 802 mqd->cp_hqd_pq_rptr_report_addr_hi); 803 804 /* set CP_HQD_PQ_CONTROL */ 805 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 806 807 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 808 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 809 mqd->cp_hqd_pq_wptr_poll_addr_lo); 810 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 811 mqd->cp_hqd_pq_wptr_poll_addr_hi); 812 813 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 814 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 815 mqd->cp_hqd_pq_doorbell_control); 816 817 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 818 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 819 820 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 821 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 822 823 soc21_grbm_select(adev, 0, 0, 0, 0); 824 mutex_unlock(&adev->srbm_mutex); 825 } 826 827 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 828 { 829 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 830 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 831 int r; 832 833 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 834 return -EINVAL; 835 836 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 837 if (r) { 838 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 839 return r; 840 } 841 842 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 843 844 return amdgpu_ring_test_helper(kiq_ring); 845 } 846 847 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 848 enum admgpu_mes_pipe pipe) 849 { 850 struct amdgpu_ring *ring; 851 int r; 852 853 if (pipe == AMDGPU_MES_KIQ_PIPE) 854 ring = &adev->gfx.kiq[0].ring; 855 else if (pipe == AMDGPU_MES_SCHED_PIPE) 856 ring = &adev->mes.ring; 857 else 858 BUG(); 859 860 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 861 (amdgpu_in_reset(adev) || adev->in_suspend)) { 862 *(ring->wptr_cpu_addr) = 0; 863 *(ring->rptr_cpu_addr) = 0; 864 amdgpu_ring_clear_ring(ring); 865 } 866 867 r = mes_v11_0_mqd_init(ring); 868 if (r) 869 return r; 870 871 if (pipe == AMDGPU_MES_SCHED_PIPE) { 872 r = mes_v11_0_kiq_enable_queue(adev); 873 if (r) 874 return r; 875 } else { 876 mes_v11_0_queue_init_register(ring); 877 } 878 879 /* get MES scheduler/KIQ versions */ 880 mutex_lock(&adev->srbm_mutex); 881 soc21_grbm_select(adev, 3, pipe, 0, 0); 882 883 if (pipe == AMDGPU_MES_SCHED_PIPE) 884 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 885 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 886 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 887 888 soc21_grbm_select(adev, 0, 0, 0, 0); 889 mutex_unlock(&adev->srbm_mutex); 890 891 return 0; 892 } 893 894 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 895 { 896 struct amdgpu_ring *ring; 897 898 ring = &adev->mes.ring; 899 900 ring->funcs = &mes_v11_0_ring_funcs; 901 902 ring->me = 3; 903 ring->pipe = 0; 904 ring->queue = 0; 905 906 ring->ring_obj = NULL; 907 ring->use_doorbell = true; 908 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 909 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 910 ring->no_scheduler = true; 911 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 912 913 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 914 AMDGPU_RING_PRIO_DEFAULT, NULL); 915 } 916 917 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 918 { 919 struct amdgpu_ring *ring; 920 921 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 922 923 ring = &adev->gfx.kiq[0].ring; 924 925 ring->me = 3; 926 ring->pipe = 1; 927 ring->queue = 0; 928 929 ring->adev = NULL; 930 ring->ring_obj = NULL; 931 ring->use_doorbell = true; 932 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 933 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 934 ring->no_scheduler = true; 935 sprintf(ring->name, "mes_kiq_%d.%d.%d", 936 ring->me, ring->pipe, ring->queue); 937 938 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 939 AMDGPU_RING_PRIO_DEFAULT, NULL); 940 } 941 942 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 943 enum admgpu_mes_pipe pipe) 944 { 945 int r, mqd_size = sizeof(struct v11_compute_mqd); 946 struct amdgpu_ring *ring; 947 948 if (pipe == AMDGPU_MES_KIQ_PIPE) 949 ring = &adev->gfx.kiq[0].ring; 950 else if (pipe == AMDGPU_MES_SCHED_PIPE) 951 ring = &adev->mes.ring; 952 else 953 BUG(); 954 955 if (ring->mqd_obj) 956 return 0; 957 958 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 959 AMDGPU_GEM_DOMAIN_VRAM | 960 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 961 &ring->mqd_gpu_addr, &ring->mqd_ptr); 962 if (r) { 963 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 964 return r; 965 } 966 967 memset(ring->mqd_ptr, 0, mqd_size); 968 969 /* prepare MQD backup */ 970 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 971 if (!adev->mes.mqd_backup[pipe]) { 972 dev_warn(adev->dev, 973 "no memory to create MQD backup for ring %s\n", 974 ring->name); 975 return -ENOMEM; 976 } 977 978 return 0; 979 } 980 981 static int mes_v11_0_sw_init(void *handle) 982 { 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 984 int pipe, r; 985 986 adev->mes.funcs = &mes_v11_0_funcs; 987 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 988 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 989 990 r = amdgpu_mes_init(adev); 991 if (r) 992 return r; 993 994 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 995 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 996 continue; 997 998 r = mes_v11_0_allocate_eop_buf(adev, pipe); 999 if (r) 1000 return r; 1001 1002 r = mes_v11_0_mqd_sw_init(adev, pipe); 1003 if (r) 1004 return r; 1005 } 1006 1007 if (adev->enable_mes_kiq) { 1008 r = mes_v11_0_kiq_ring_init(adev); 1009 if (r) 1010 return r; 1011 } 1012 1013 r = mes_v11_0_ring_init(adev); 1014 if (r) 1015 return r; 1016 1017 return 0; 1018 } 1019 1020 static int mes_v11_0_sw_fini(void *handle) 1021 { 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1023 int pipe; 1024 1025 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1026 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1027 1028 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1029 kfree(adev->mes.mqd_backup[pipe]); 1030 1031 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1032 &adev->mes.eop_gpu_addr[pipe], 1033 NULL); 1034 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1035 } 1036 1037 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1038 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1039 &adev->gfx.kiq[0].ring.mqd_ptr); 1040 1041 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1042 &adev->mes.ring.mqd_gpu_addr, 1043 &adev->mes.ring.mqd_ptr); 1044 1045 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1046 amdgpu_ring_fini(&adev->mes.ring); 1047 1048 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1049 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1050 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1051 } 1052 1053 amdgpu_mes_fini(adev); 1054 return 0; 1055 } 1056 1057 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1058 { 1059 uint32_t data; 1060 int i; 1061 struct amdgpu_device *adev = ring->adev; 1062 1063 mutex_lock(&adev->srbm_mutex); 1064 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1065 1066 /* disable the queue if it's active */ 1067 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1068 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1069 for (i = 0; i < adev->usec_timeout; i++) { 1070 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1071 break; 1072 udelay(1); 1073 } 1074 } 1075 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1076 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1077 DOORBELL_EN, 0); 1078 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1079 DOORBELL_HIT, 1); 1080 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1081 1082 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1083 1084 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1085 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1086 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1087 1088 soc21_grbm_select(adev, 0, 0, 0, 0); 1089 mutex_unlock(&adev->srbm_mutex); 1090 } 1091 1092 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1093 { 1094 uint32_t tmp; 1095 struct amdgpu_device *adev = ring->adev; 1096 1097 /* tell RLC which is KIQ queue */ 1098 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1099 tmp &= 0xffffff00; 1100 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1101 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1102 tmp |= 0x80; 1103 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1104 } 1105 1106 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1107 { 1108 uint32_t tmp; 1109 1110 /* tell RLC which is KIQ dequeue */ 1111 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1112 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1113 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1114 } 1115 1116 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1117 { 1118 int r = 0; 1119 1120 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1121 1122 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1123 if (r) { 1124 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1125 return r; 1126 } 1127 1128 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1129 if (r) { 1130 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1131 return r; 1132 } 1133 1134 } 1135 1136 mes_v11_0_enable(adev, true); 1137 1138 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1139 1140 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1141 if (r) 1142 goto failure; 1143 1144 return r; 1145 1146 failure: 1147 mes_v11_0_hw_fini(adev); 1148 return r; 1149 } 1150 1151 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1152 { 1153 if (adev->mes.ring.sched.ready) { 1154 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1155 adev->mes.ring.sched.ready = false; 1156 } 1157 1158 if (amdgpu_sriov_vf(adev)) { 1159 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1160 mes_v11_0_kiq_clear(adev); 1161 } 1162 1163 mes_v11_0_enable(adev, false); 1164 1165 return 0; 1166 } 1167 1168 static int mes_v11_0_hw_init(void *handle) 1169 { 1170 int r; 1171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1172 1173 if (!adev->enable_mes_kiq) { 1174 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1175 r = mes_v11_0_load_microcode(adev, 1176 AMDGPU_MES_SCHED_PIPE, true); 1177 if (r) { 1178 DRM_ERROR("failed to MES fw, r=%d\n", r); 1179 return r; 1180 } 1181 } 1182 1183 mes_v11_0_enable(adev, true); 1184 } 1185 1186 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1187 if (r) 1188 goto failure; 1189 1190 r = mes_v11_0_set_hw_resources(&adev->mes); 1191 if (r) 1192 goto failure; 1193 1194 r = mes_v11_0_query_sched_status(&adev->mes); 1195 if (r) { 1196 DRM_ERROR("MES is busy\n"); 1197 goto failure; 1198 } 1199 1200 /* 1201 * Disable KIQ ring usage from the driver once MES is enabled. 1202 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1203 * with MES enabled. 1204 */ 1205 adev->gfx.kiq[0].ring.sched.ready = false; 1206 adev->mes.ring.sched.ready = true; 1207 1208 return 0; 1209 1210 failure: 1211 mes_v11_0_hw_fini(adev); 1212 return r; 1213 } 1214 1215 static int mes_v11_0_hw_fini(void *handle) 1216 { 1217 return 0; 1218 } 1219 1220 static int mes_v11_0_suspend(void *handle) 1221 { 1222 int r; 1223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1224 1225 r = amdgpu_mes_suspend(adev); 1226 if (r) 1227 return r; 1228 1229 return mes_v11_0_hw_fini(adev); 1230 } 1231 1232 static int mes_v11_0_resume(void *handle) 1233 { 1234 int r; 1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236 1237 r = mes_v11_0_hw_init(adev); 1238 if (r) 1239 return r; 1240 1241 return amdgpu_mes_resume(adev); 1242 } 1243 1244 static int mes_v11_0_early_init(void *handle) 1245 { 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1247 int pipe, r; 1248 1249 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1250 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1251 continue; 1252 r = amdgpu_mes_init_microcode(adev, pipe); 1253 if (r) 1254 return r; 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int mes_v11_0_late_init(void *handle) 1261 { 1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1263 1264 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1265 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1266 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1267 amdgpu_mes_self_test(adev); 1268 1269 return 0; 1270 } 1271 1272 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1273 .name = "mes_v11_0", 1274 .early_init = mes_v11_0_early_init, 1275 .late_init = mes_v11_0_late_init, 1276 .sw_init = mes_v11_0_sw_init, 1277 .sw_fini = mes_v11_0_sw_fini, 1278 .hw_init = mes_v11_0_hw_init, 1279 .hw_fini = mes_v11_0_hw_fini, 1280 .suspend = mes_v11_0_suspend, 1281 .resume = mes_v11_0_resume, 1282 }; 1283 1284 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1285 .type = AMD_IP_BLOCK_TYPE_MES, 1286 .major = 11, 1287 .minor = 0, 1288 .rev = 0, 1289 .funcs = &mes_v11_0_ip_funcs, 1290 }; 1291