1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 62 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 63 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 64 65 #define MES_EOP_SIZE 2048 66 #define GFX_MES_DRAM_SIZE 0x80000 67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 68 69 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 70 { 71 struct amdgpu_device *adev = ring->adev; 72 73 if (ring->use_doorbell) { 74 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 75 ring->wptr); 76 WDOORBELL64(ring->doorbell_index, ring->wptr); 77 } else { 78 BUG(); 79 } 80 } 81 82 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 83 { 84 return *ring->rptr_cpu_addr; 85 } 86 87 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 88 { 89 u64 wptr; 90 91 if (ring->use_doorbell) 92 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 93 else 94 BUG(); 95 return wptr; 96 } 97 98 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 99 .type = AMDGPU_RING_TYPE_MES, 100 .align_mask = 1, 101 .nop = 0, 102 .support_64bit_ptrs = true, 103 .get_rptr = mes_v11_0_ring_get_rptr, 104 .get_wptr = mes_v11_0_ring_get_wptr, 105 .set_wptr = mes_v11_0_ring_set_wptr, 106 .insert_nop = amdgpu_ring_insert_nop, 107 }; 108 109 static const char *mes_v11_0_opcodes[] = { 110 "SET_HW_RSRC", 111 "SET_SCHEDULING_CONFIG", 112 "ADD_QUEUE", 113 "REMOVE_QUEUE", 114 "PERFORM_YIELD", 115 "SET_GANG_PRIORITY_LEVEL", 116 "SUSPEND", 117 "RESUME", 118 "RESET", 119 "SET_LOG_BUFFER", 120 "CHANGE_GANG_PRORITY", 121 "QUERY_SCHEDULER_STATUS", 122 "PROGRAM_GDS", 123 "SET_DEBUG_VMID", 124 "MISC", 125 "UPDATE_ROOT_PAGE_TABLE", 126 "AMD_LOG", 127 "unused", 128 "unused", 129 "SET_HW_RSRC_1", 130 }; 131 132 static const char *mes_v11_0_misc_opcodes[] = { 133 "WRITE_REG", 134 "INV_GART", 135 "QUERY_STATUS", 136 "READ_REG", 137 "WAIT_REG_MEM", 138 "SET_SHADER_DEBUGGER", 139 }; 140 141 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 142 { 143 const char *op_str = NULL; 144 145 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 146 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 147 148 return op_str; 149 } 150 151 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 152 { 153 const char *op_str = NULL; 154 155 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 156 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 157 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 158 159 return op_str; 160 } 161 162 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 163 void *pkt, int size, 164 int api_status_off) 165 { 166 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 167 signed long timeout = 2100000; /* 2100 ms */ 168 struct amdgpu_device *adev = mes->adev; 169 struct amdgpu_ring *ring = &mes->ring[0]; 170 struct MES_API_STATUS *api_status; 171 union MESAPI__MISC *x_pkt = pkt; 172 const char *op_str, *misc_op_str; 173 unsigned long flags; 174 u64 status_gpu_addr; 175 u32 seq, status_offset; 176 u64 *status_ptr; 177 signed long r; 178 int ret; 179 180 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 181 return -EINVAL; 182 183 if (amdgpu_emu_mode) { 184 timeout *= 100; 185 } else if (amdgpu_sriov_vf(adev)) { 186 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 187 timeout = 15 * 600 * 1000; 188 } 189 190 ret = amdgpu_device_wb_get(adev, &status_offset); 191 if (ret) 192 return ret; 193 194 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 195 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 196 *status_ptr = 0; 197 198 spin_lock_irqsave(&mes->ring_lock[0], flags); 199 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 200 if (r) 201 goto error_unlock_free; 202 203 seq = ++ring->fence_drv.sync_seq; 204 r = amdgpu_fence_wait_polling(ring, 205 seq - ring->fence_drv.num_fences_mask, 206 timeout); 207 if (r < 1) 208 goto error_undo; 209 210 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 211 api_status->api_completion_fence_addr = status_gpu_addr; 212 api_status->api_completion_fence_value = 1; 213 214 amdgpu_ring_write_multiple(ring, pkt, size / 4); 215 216 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 217 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 218 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 219 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 220 mes_status_pkt.api_status.api_completion_fence_addr = 221 ring->fence_drv.gpu_addr; 222 mes_status_pkt.api_status.api_completion_fence_value = seq; 223 224 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 225 sizeof(mes_status_pkt) / 4); 226 227 amdgpu_ring_commit(ring); 228 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 229 230 op_str = mes_v11_0_get_op_string(x_pkt); 231 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 232 233 if (misc_op_str) 234 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 235 misc_op_str); 236 else if (op_str) 237 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 238 else 239 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 240 x_pkt->header.opcode); 241 242 r = amdgpu_fence_wait_polling(ring, seq, timeout); 243 if (r < 1 || !*status_ptr) { 244 245 if (misc_op_str) 246 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 247 op_str, misc_op_str); 248 else if (op_str) 249 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 250 op_str); 251 else 252 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 253 x_pkt->header.opcode); 254 255 while (halt_if_hws_hang) 256 schedule(); 257 258 r = -ETIMEDOUT; 259 goto error_wb_free; 260 } 261 262 amdgpu_device_wb_free(adev, status_offset); 263 return 0; 264 265 error_undo: 266 dev_err(adev->dev, "MES ring buffer is full.\n"); 267 amdgpu_ring_undo(ring); 268 269 error_unlock_free: 270 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 271 272 error_wb_free: 273 amdgpu_device_wb_free(adev, status_offset); 274 return r; 275 } 276 277 static int convert_to_mes_queue_type(int queue_type) 278 { 279 if (queue_type == AMDGPU_RING_TYPE_GFX) 280 return MES_QUEUE_TYPE_GFX; 281 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 282 return MES_QUEUE_TYPE_COMPUTE; 283 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 284 return MES_QUEUE_TYPE_SDMA; 285 else 286 BUG(); 287 return -1; 288 } 289 290 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 291 struct mes_add_queue_input *input) 292 { 293 struct amdgpu_device *adev = mes->adev; 294 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 295 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 296 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 297 298 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 299 300 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 301 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 302 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 303 304 mes_add_queue_pkt.process_id = input->process_id; 305 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 306 mes_add_queue_pkt.process_va_start = input->process_va_start; 307 mes_add_queue_pkt.process_va_end = input->process_va_end; 308 mes_add_queue_pkt.process_quantum = input->process_quantum; 309 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 310 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 311 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 312 mes_add_queue_pkt.inprocess_gang_priority = 313 input->inprocess_gang_priority; 314 mes_add_queue_pkt.gang_global_priority_level = 315 input->gang_global_priority_level; 316 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 317 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 318 319 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 320 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 321 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 322 else 323 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 324 325 mes_add_queue_pkt.queue_type = 326 convert_to_mes_queue_type(input->queue_type); 327 mes_add_queue_pkt.paging = input->paging; 328 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 329 mes_add_queue_pkt.gws_base = input->gws_base; 330 mes_add_queue_pkt.gws_size = input->gws_size; 331 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 332 mes_add_queue_pkt.tma_addr = input->tma_addr; 333 mes_add_queue_pkt.trap_en = input->trap_en; 334 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 335 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 336 337 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 338 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 339 mes_add_queue_pkt.gds_size = input->queue_size; 340 341 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 342 343 return mes_v11_0_submit_pkt_and_poll_completion(mes, 344 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 345 offsetof(union MESAPI__ADD_QUEUE, api_status)); 346 } 347 348 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 349 struct mes_remove_queue_input *input) 350 { 351 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 352 353 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 354 355 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 356 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 357 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 358 359 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 360 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 361 362 return mes_v11_0_submit_pkt_and_poll_completion(mes, 363 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 364 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 365 } 366 367 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 368 uint32_t me_id, uint32_t pipe_id, 369 uint32_t queue_id, uint32_t vmid) 370 { 371 struct amdgpu_device *adev = mes->adev; 372 uint32_t value, reg; 373 int i, r = 0; 374 375 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 376 377 if (queue_type == AMDGPU_RING_TYPE_GFX) { 378 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 379 me_id, pipe_id, queue_id, vmid); 380 381 mutex_lock(&adev->gfx.reset_sem_mutex); 382 gfx_v11_0_request_gfx_index_mutex(adev, true); 383 /* all se allow writes */ 384 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 385 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 386 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 387 if (pipe_id == 0) 388 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 389 else 390 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 391 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 392 gfx_v11_0_request_gfx_index_mutex(adev, false); 393 mutex_unlock(&adev->gfx.reset_sem_mutex); 394 395 mutex_lock(&adev->srbm_mutex); 396 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 397 /* wait till dequeue take effects */ 398 for (i = 0; i < adev->usec_timeout; i++) { 399 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 400 break; 401 udelay(1); 402 } 403 if (i >= adev->usec_timeout) { 404 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 405 r = -ETIMEDOUT; 406 } 407 408 soc21_grbm_select(adev, 0, 0, 0, 0); 409 mutex_unlock(&adev->srbm_mutex); 410 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 411 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 412 me_id, pipe_id, queue_id); 413 mutex_lock(&adev->srbm_mutex); 414 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 415 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 416 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 417 418 /* wait till dequeue take effects */ 419 for (i = 0; i < adev->usec_timeout; i++) { 420 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 421 break; 422 udelay(1); 423 } 424 if (i >= adev->usec_timeout) { 425 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 426 r = -ETIMEDOUT; 427 } 428 soc21_grbm_select(adev, 0, 0, 0, 0); 429 mutex_unlock(&adev->srbm_mutex); 430 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 431 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 432 me_id, pipe_id, queue_id); 433 switch (me_id) { 434 case 1: 435 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 436 break; 437 case 0: 438 default: 439 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 440 break; 441 } 442 443 value = 1 << queue_id; 444 WREG32(reg, value); 445 /* wait for queue reset done */ 446 for (i = 0; i < adev->usec_timeout; i++) { 447 if (!(RREG32(reg) & value)) 448 break; 449 udelay(1); 450 } 451 if (i >= adev->usec_timeout) { 452 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 453 r = -ETIMEDOUT; 454 } 455 } 456 457 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 458 return r; 459 } 460 461 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 462 struct mes_reset_queue_input *input) 463 { 464 if (input->use_mmio) 465 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 466 input->me_id, input->pipe_id, 467 input->queue_id, input->vmid); 468 469 union MESAPI__RESET mes_reset_queue_pkt; 470 471 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 472 473 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 474 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 475 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 476 477 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 478 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; 479 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 480 481 return mes_v11_0_submit_pkt_and_poll_completion(mes, 482 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 483 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 484 } 485 486 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 487 struct mes_map_legacy_queue_input *input) 488 { 489 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 490 491 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 492 493 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 494 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 495 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 496 497 mes_add_queue_pkt.pipe_id = input->pipe_id; 498 mes_add_queue_pkt.queue_id = input->queue_id; 499 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 500 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 501 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 502 mes_add_queue_pkt.queue_type = 503 convert_to_mes_queue_type(input->queue_type); 504 mes_add_queue_pkt.map_legacy_kq = 1; 505 506 return mes_v11_0_submit_pkt_and_poll_completion(mes, 507 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 508 offsetof(union MESAPI__ADD_QUEUE, api_status)); 509 } 510 511 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 512 struct mes_unmap_legacy_queue_input *input) 513 { 514 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 515 516 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 517 518 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 519 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 520 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 521 522 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 523 mes_remove_queue_pkt.gang_context_addr = 0; 524 525 mes_remove_queue_pkt.pipe_id = input->pipe_id; 526 mes_remove_queue_pkt.queue_id = input->queue_id; 527 528 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 529 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 530 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 531 mes_remove_queue_pkt.tf_data = 532 lower_32_bits(input->trail_fence_data); 533 } else { 534 mes_remove_queue_pkt.unmap_legacy_queue = 1; 535 mes_remove_queue_pkt.queue_type = 536 convert_to_mes_queue_type(input->queue_type); 537 } 538 539 return mes_v11_0_submit_pkt_and_poll_completion(mes, 540 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 541 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 542 } 543 544 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 545 struct mes_suspend_gang_input *input) 546 { 547 union MESAPI__SUSPEND mes_suspend_gang_pkt; 548 549 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 550 551 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 552 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 553 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 554 555 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 556 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 557 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 558 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 559 560 return mes_v11_0_submit_pkt_and_poll_completion(mes, 561 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 562 offsetof(union MESAPI__SUSPEND, api_status)); 563 } 564 565 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 566 struct mes_resume_gang_input *input) 567 { 568 union MESAPI__RESUME mes_resume_gang_pkt; 569 570 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 571 572 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 573 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 574 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 575 576 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 577 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 578 579 return mes_v11_0_submit_pkt_and_poll_completion(mes, 580 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 581 offsetof(union MESAPI__RESUME, api_status)); 582 } 583 584 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 585 { 586 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 587 588 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 589 590 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 591 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 592 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 593 594 return mes_v11_0_submit_pkt_and_poll_completion(mes, 595 &mes_status_pkt, sizeof(mes_status_pkt), 596 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 597 } 598 599 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 600 struct mes_misc_op_input *input) 601 { 602 union MESAPI__MISC misc_pkt; 603 604 memset(&misc_pkt, 0, sizeof(misc_pkt)); 605 606 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 607 misc_pkt.header.opcode = MES_SCH_API_MISC; 608 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 609 610 switch (input->op) { 611 case MES_MISC_OP_READ_REG: 612 misc_pkt.opcode = MESAPI_MISC__READ_REG; 613 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 614 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 615 break; 616 case MES_MISC_OP_WRITE_REG: 617 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 618 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 619 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 620 break; 621 case MES_MISC_OP_WRM_REG_WAIT: 622 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 623 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 624 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 625 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 626 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 627 misc_pkt.wait_reg_mem.reg_offset2 = 0; 628 break; 629 case MES_MISC_OP_WRM_REG_WR_WAIT: 630 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 631 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 632 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 633 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 634 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 635 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 636 break; 637 case MES_MISC_OP_SET_SHADER_DEBUGGER: 638 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 639 misc_pkt.set_shader_debugger.process_context_addr = 640 input->set_shader_debugger.process_context_addr; 641 misc_pkt.set_shader_debugger.flags.u32all = 642 input->set_shader_debugger.flags.u32all; 643 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 644 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 645 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 646 input->set_shader_debugger.tcp_watch_cntl, 647 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 648 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 649 break; 650 case MES_MISC_OP_CHANGE_CONFIG: 651 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 652 dev_err(mes->adev->dev, "MES FW versoin must be larger than 0x63 to support limit single process feature.\n"); 653 return -EINVAL; 654 } 655 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 656 misc_pkt.change_config.opcode = 657 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 658 misc_pkt.change_config.option.bits.limit_single_process = 659 input->change_config.option.limit_single_process; 660 break; 661 662 default: 663 DRM_ERROR("unsupported misc op (%d) \n", input->op); 664 return -EINVAL; 665 } 666 667 return mes_v11_0_submit_pkt_and_poll_completion(mes, 668 &misc_pkt, sizeof(misc_pkt), 669 offsetof(union MESAPI__MISC, api_status)); 670 } 671 672 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 673 { 674 int i; 675 struct amdgpu_device *adev = mes->adev; 676 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 677 678 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 679 680 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 681 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 682 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 683 684 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 685 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 686 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 687 mes_set_hw_res_pkt.paging_vmid = 0; 688 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 689 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 690 mes->query_status_fence_gpu_addr[0]; 691 692 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 693 mes_set_hw_res_pkt.compute_hqd_mask[i] = 694 mes->compute_hqd_mask[i]; 695 696 for (i = 0; i < MAX_GFX_PIPES; i++) 697 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 698 699 for (i = 0; i < MAX_SDMA_PIPES; i++) 700 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 701 702 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 703 mes_set_hw_res_pkt.aggregated_doorbells[i] = 704 mes->aggregated_doorbells[i]; 705 706 for (i = 0; i < 5; i++) { 707 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 708 mes_set_hw_res_pkt.mmhub_base[i] = 709 adev->reg_offset[MMHUB_HWIP][0][i]; 710 mes_set_hw_res_pkt.osssys_base[i] = 711 adev->reg_offset[OSSSYS_HWIP][0][i]; 712 } 713 714 mes_set_hw_res_pkt.disable_reset = 1; 715 mes_set_hw_res_pkt.disable_mes_log = 1; 716 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 717 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 718 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 719 mes_set_hw_res_pkt.oversubscription_timer = 50; 720 if (amdgpu_mes_log_enable) { 721 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 722 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 723 mes->event_log_gpu_addr; 724 } 725 726 if (enforce_isolation) 727 mes_set_hw_res_pkt.limit_single_process = 1; 728 729 return mes_v11_0_submit_pkt_and_poll_completion(mes, 730 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 731 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 732 } 733 734 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 735 { 736 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 737 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 738 739 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 740 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 741 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 742 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 743 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 744 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 745 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = 746 mes->resource_1_gpu_addr + MES11_HW_RESOURCE_1_SIZE; 747 748 return mes_v11_0_submit_pkt_and_poll_completion(mes, 749 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 750 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 751 } 752 753 static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes, 754 struct mes_reset_legacy_queue_input *input) 755 { 756 union MESAPI__RESET mes_reset_queue_pkt; 757 758 if (input->use_mmio) 759 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 760 input->me_id, input->pipe_id, 761 input->queue_id, input->vmid); 762 763 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 764 765 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 766 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 767 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 768 769 mes_reset_queue_pkt.queue_type = 770 convert_to_mes_queue_type(input->queue_type); 771 772 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 773 mes_reset_queue_pkt.reset_legacy_gfx = 1; 774 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 775 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 776 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 777 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 778 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 779 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 780 } else { 781 mes_reset_queue_pkt.reset_queue_only = 1; 782 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 783 } 784 785 return mes_v11_0_submit_pkt_and_poll_completion(mes, 786 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 787 offsetof(union MESAPI__RESET, api_status)); 788 } 789 790 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 791 .add_hw_queue = mes_v11_0_add_hw_queue, 792 .remove_hw_queue = mes_v11_0_remove_hw_queue, 793 .map_legacy_queue = mes_v11_0_map_legacy_queue, 794 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 795 .suspend_gang = mes_v11_0_suspend_gang, 796 .resume_gang = mes_v11_0_resume_gang, 797 .misc_op = mes_v11_0_misc_op, 798 .reset_legacy_queue = mes_v11_0_reset_legacy_queue, 799 .reset_hw_queue = mes_v11_0_reset_hw_queue, 800 }; 801 802 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 803 enum admgpu_mes_pipe pipe) 804 { 805 int r; 806 const struct mes_firmware_header_v1_0 *mes_hdr; 807 const __le32 *fw_data; 808 unsigned fw_size; 809 810 mes_hdr = (const struct mes_firmware_header_v1_0 *) 811 adev->mes.fw[pipe]->data; 812 813 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 814 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 815 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 816 817 r = amdgpu_bo_create_reserved(adev, fw_size, 818 PAGE_SIZE, 819 AMDGPU_GEM_DOMAIN_VRAM | 820 AMDGPU_GEM_DOMAIN_GTT, 821 &adev->mes.ucode_fw_obj[pipe], 822 &adev->mes.ucode_fw_gpu_addr[pipe], 823 (void **)&adev->mes.ucode_fw_ptr[pipe]); 824 if (r) { 825 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 826 return r; 827 } 828 829 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 830 831 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 832 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 833 834 return 0; 835 } 836 837 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 838 enum admgpu_mes_pipe pipe) 839 { 840 int r; 841 const struct mes_firmware_header_v1_0 *mes_hdr; 842 const __le32 *fw_data; 843 unsigned fw_size; 844 845 mes_hdr = (const struct mes_firmware_header_v1_0 *) 846 adev->mes.fw[pipe]->data; 847 848 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 849 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 850 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 851 852 if (fw_size > GFX_MES_DRAM_SIZE) { 853 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 854 pipe, fw_size, GFX_MES_DRAM_SIZE); 855 return -EINVAL; 856 } 857 858 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 859 64 * 1024, 860 AMDGPU_GEM_DOMAIN_VRAM | 861 AMDGPU_GEM_DOMAIN_GTT, 862 &adev->mes.data_fw_obj[pipe], 863 &adev->mes.data_fw_gpu_addr[pipe], 864 (void **)&adev->mes.data_fw_ptr[pipe]); 865 if (r) { 866 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 867 return r; 868 } 869 870 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 871 872 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 873 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 874 875 return 0; 876 } 877 878 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 879 enum admgpu_mes_pipe pipe) 880 { 881 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 882 &adev->mes.data_fw_gpu_addr[pipe], 883 (void **)&adev->mes.data_fw_ptr[pipe]); 884 885 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 886 &adev->mes.ucode_fw_gpu_addr[pipe], 887 (void **)&adev->mes.ucode_fw_ptr[pipe]); 888 } 889 890 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 891 { 892 int pipe; 893 894 /* get MES scheduler/KIQ versions */ 895 mutex_lock(&adev->srbm_mutex); 896 897 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 898 soc21_grbm_select(adev, 3, pipe, 0, 0); 899 900 if (pipe == AMDGPU_MES_SCHED_PIPE) 901 adev->mes.sched_version = 902 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 903 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 904 adev->mes.kiq_version = 905 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 906 } 907 908 soc21_grbm_select(adev, 0, 0, 0, 0); 909 mutex_unlock(&adev->srbm_mutex); 910 } 911 912 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 913 { 914 uint64_t ucode_addr; 915 uint32_t pipe, data = 0; 916 917 if (enable) { 918 if (amdgpu_mes_log_enable) { 919 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 920 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 921 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 922 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 923 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 924 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 925 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 926 } 927 928 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 929 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 930 data = REG_SET_FIELD(data, CP_MES_CNTL, 931 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 932 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 933 934 mutex_lock(&adev->srbm_mutex); 935 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 936 if (!adev->enable_mes_kiq && 937 pipe == AMDGPU_MES_KIQ_PIPE) 938 continue; 939 940 soc21_grbm_select(adev, 3, pipe, 0, 0); 941 942 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 943 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 944 lower_32_bits(ucode_addr)); 945 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 946 upper_32_bits(ucode_addr)); 947 } 948 soc21_grbm_select(adev, 0, 0, 0, 0); 949 mutex_unlock(&adev->srbm_mutex); 950 951 /* unhalt MES and activate pipe0 */ 952 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 953 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 954 adev->enable_mes_kiq ? 1 : 0); 955 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 956 957 if (amdgpu_emu_mode) 958 msleep(100); 959 else 960 udelay(500); 961 } else { 962 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 963 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 964 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 965 data = REG_SET_FIELD(data, CP_MES_CNTL, 966 MES_INVALIDATE_ICACHE, 1); 967 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 968 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 969 adev->enable_mes_kiq ? 1 : 0); 970 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 971 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 972 } 973 } 974 975 /* This function is for backdoor MES firmware */ 976 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 977 enum admgpu_mes_pipe pipe, bool prime_icache) 978 { 979 int r; 980 uint32_t data; 981 uint64_t ucode_addr; 982 983 mes_v11_0_enable(adev, false); 984 985 if (!adev->mes.fw[pipe]) 986 return -EINVAL; 987 988 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 989 if (r) 990 return r; 991 992 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 993 if (r) { 994 mes_v11_0_free_ucode_buffers(adev, pipe); 995 return r; 996 } 997 998 mutex_lock(&adev->srbm_mutex); 999 /* me=3, pipe=0, queue=0 */ 1000 soc21_grbm_select(adev, 3, pipe, 0, 0); 1001 1002 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1003 1004 /* set ucode start address */ 1005 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1006 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1007 lower_32_bits(ucode_addr)); 1008 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1009 upper_32_bits(ucode_addr)); 1010 1011 /* set ucode fimrware address */ 1012 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1013 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1014 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1015 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1016 1017 /* set ucode instruction cache boundary to 2M-1 */ 1018 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1019 1020 /* set ucode data firmware address */ 1021 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1022 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1023 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1024 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1025 1026 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1027 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1028 1029 if (prime_icache) { 1030 /* invalidate ICACHE */ 1031 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1032 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1033 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1034 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1035 1036 /* prime the ICACHE. */ 1037 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1038 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1039 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1040 } 1041 1042 soc21_grbm_select(adev, 0, 0, 0, 0); 1043 mutex_unlock(&adev->srbm_mutex); 1044 1045 return 0; 1046 } 1047 1048 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1049 enum admgpu_mes_pipe pipe) 1050 { 1051 int r; 1052 u32 *eop; 1053 1054 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1055 AMDGPU_GEM_DOMAIN_GTT, 1056 &adev->mes.eop_gpu_obj[pipe], 1057 &adev->mes.eop_gpu_addr[pipe], 1058 (void **)&eop); 1059 if (r) { 1060 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1061 return r; 1062 } 1063 1064 memset(eop, 0, 1065 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1066 1067 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1068 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1069 1070 return 0; 1071 } 1072 1073 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1074 { 1075 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1076 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1077 uint32_t tmp; 1078 1079 memset(mqd, 0, sizeof(*mqd)); 1080 1081 mqd->header = 0xC0310800; 1082 mqd->compute_pipelinestat_enable = 0x00000001; 1083 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1084 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1085 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1086 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1087 mqd->compute_misc_reserved = 0x00000007; 1088 1089 eop_base_addr = ring->eop_gpu_addr >> 8; 1090 1091 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1092 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1093 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1094 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1095 1096 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1097 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1098 mqd->cp_hqd_eop_control = tmp; 1099 1100 /* disable the queue if it's active */ 1101 ring->wptr = 0; 1102 mqd->cp_hqd_pq_rptr = 0; 1103 mqd->cp_hqd_pq_wptr_lo = 0; 1104 mqd->cp_hqd_pq_wptr_hi = 0; 1105 1106 /* set the pointer to the MQD */ 1107 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1108 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1109 1110 /* set MQD vmid to 0 */ 1111 tmp = regCP_MQD_CONTROL_DEFAULT; 1112 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1113 mqd->cp_mqd_control = tmp; 1114 1115 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1116 hqd_gpu_addr = ring->gpu_addr >> 8; 1117 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1118 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1119 1120 /* set the wb address whether it's enabled or not */ 1121 wb_gpu_addr = ring->rptr_gpu_addr; 1122 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1123 mqd->cp_hqd_pq_rptr_report_addr_hi = 1124 upper_32_bits(wb_gpu_addr) & 0xffff; 1125 1126 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1127 wb_gpu_addr = ring->wptr_gpu_addr; 1128 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1129 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1130 1131 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1132 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1133 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1134 (order_base_2(ring->ring_size / 4) - 1)); 1135 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1136 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1137 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1138 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1139 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1140 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1142 mqd->cp_hqd_pq_control = tmp; 1143 1144 /* enable doorbell */ 1145 tmp = 0; 1146 if (ring->use_doorbell) { 1147 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1148 DOORBELL_OFFSET, ring->doorbell_index); 1149 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1150 DOORBELL_EN, 1); 1151 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1152 DOORBELL_SOURCE, 0); 1153 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1154 DOORBELL_HIT, 0); 1155 } else 1156 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1157 DOORBELL_EN, 0); 1158 mqd->cp_hqd_pq_doorbell_control = tmp; 1159 1160 mqd->cp_hqd_vmid = 0; 1161 /* activate the queue */ 1162 mqd->cp_hqd_active = 1; 1163 1164 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1165 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1166 PRELOAD_SIZE, 0x55); 1167 mqd->cp_hqd_persistent_state = tmp; 1168 1169 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1170 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1171 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1172 1173 amdgpu_device_flush_hdp(ring->adev, NULL); 1174 return 0; 1175 } 1176 1177 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1178 { 1179 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1180 struct amdgpu_device *adev = ring->adev; 1181 uint32_t data = 0; 1182 1183 mutex_lock(&adev->srbm_mutex); 1184 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1185 1186 /* set CP_HQD_VMID.VMID = 0. */ 1187 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1188 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1189 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1190 1191 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1192 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1193 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1194 DOORBELL_EN, 0); 1195 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1196 1197 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1198 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1199 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1200 1201 /* set CP_MQD_CONTROL.VMID=0 */ 1202 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1203 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1204 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1205 1206 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1208 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1209 1210 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1211 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1212 mqd->cp_hqd_pq_rptr_report_addr_lo); 1213 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1214 mqd->cp_hqd_pq_rptr_report_addr_hi); 1215 1216 /* set CP_HQD_PQ_CONTROL */ 1217 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1218 1219 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1220 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1221 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1222 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1223 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1224 1225 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1226 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1227 mqd->cp_hqd_pq_doorbell_control); 1228 1229 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1230 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1231 1232 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1233 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1234 1235 soc21_grbm_select(adev, 0, 0, 0, 0); 1236 mutex_unlock(&adev->srbm_mutex); 1237 } 1238 1239 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1240 { 1241 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1242 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1243 int r; 1244 1245 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1246 return -EINVAL; 1247 1248 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1249 if (r) { 1250 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1251 return r; 1252 } 1253 1254 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1255 1256 return amdgpu_ring_test_helper(kiq_ring); 1257 } 1258 1259 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1260 enum admgpu_mes_pipe pipe) 1261 { 1262 struct amdgpu_ring *ring; 1263 int r; 1264 1265 if (pipe == AMDGPU_MES_KIQ_PIPE) 1266 ring = &adev->gfx.kiq[0].ring; 1267 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1268 ring = &adev->mes.ring[0]; 1269 else 1270 BUG(); 1271 1272 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1273 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1274 *(ring->wptr_cpu_addr) = 0; 1275 *(ring->rptr_cpu_addr) = 0; 1276 amdgpu_ring_clear_ring(ring); 1277 } 1278 1279 r = mes_v11_0_mqd_init(ring); 1280 if (r) 1281 return r; 1282 1283 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1284 r = mes_v11_0_kiq_enable_queue(adev); 1285 if (r) 1286 return r; 1287 } else { 1288 mes_v11_0_queue_init_register(ring); 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1295 { 1296 struct amdgpu_ring *ring; 1297 1298 ring = &adev->mes.ring[0]; 1299 1300 ring->funcs = &mes_v11_0_ring_funcs; 1301 1302 ring->me = 3; 1303 ring->pipe = 0; 1304 ring->queue = 0; 1305 1306 ring->ring_obj = NULL; 1307 ring->use_doorbell = true; 1308 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1309 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1310 ring->no_scheduler = true; 1311 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1312 1313 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1314 AMDGPU_RING_PRIO_DEFAULT, NULL); 1315 } 1316 1317 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1318 { 1319 struct amdgpu_ring *ring; 1320 1321 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1322 1323 ring = &adev->gfx.kiq[0].ring; 1324 1325 ring->me = 3; 1326 ring->pipe = 1; 1327 ring->queue = 0; 1328 1329 ring->adev = NULL; 1330 ring->ring_obj = NULL; 1331 ring->use_doorbell = true; 1332 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1333 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1334 ring->no_scheduler = true; 1335 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1336 ring->me, ring->pipe, ring->queue); 1337 1338 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1339 AMDGPU_RING_PRIO_DEFAULT, NULL); 1340 } 1341 1342 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1343 enum admgpu_mes_pipe pipe) 1344 { 1345 int r, mqd_size = sizeof(struct v11_compute_mqd); 1346 struct amdgpu_ring *ring; 1347 1348 if (pipe == AMDGPU_MES_KIQ_PIPE) 1349 ring = &adev->gfx.kiq[0].ring; 1350 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1351 ring = &adev->mes.ring[0]; 1352 else 1353 BUG(); 1354 1355 if (ring->mqd_obj) 1356 return 0; 1357 1358 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1359 AMDGPU_GEM_DOMAIN_VRAM | 1360 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1361 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1362 if (r) { 1363 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1364 return r; 1365 } 1366 1367 memset(ring->mqd_ptr, 0, mqd_size); 1368 1369 /* prepare MQD backup */ 1370 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1371 if (!adev->mes.mqd_backup[pipe]) { 1372 dev_warn(adev->dev, 1373 "no memory to create MQD backup for ring %s\n", 1374 ring->name); 1375 return -ENOMEM; 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1382 { 1383 struct amdgpu_device *adev = ip_block->adev; 1384 int pipe, r; 1385 1386 adev->mes.funcs = &mes_v11_0_funcs; 1387 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1388 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1389 1390 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1391 1392 r = amdgpu_mes_init(adev); 1393 if (r) 1394 return r; 1395 1396 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1397 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1398 continue; 1399 1400 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1401 if (r) 1402 return r; 1403 1404 r = mes_v11_0_mqd_sw_init(adev, pipe); 1405 if (r) 1406 return r; 1407 } 1408 1409 if (adev->enable_mes_kiq) { 1410 r = mes_v11_0_kiq_ring_init(adev); 1411 if (r) 1412 return r; 1413 } 1414 1415 r = mes_v11_0_ring_init(adev); 1416 if (r) 1417 return r; 1418 1419 if (amdgpu_sriov_is_mes_info_enable(adev) || 1420 adev->gfx.enable_cleaner_shader) { 1421 r = amdgpu_bo_create_kernel(adev, 1422 MES11_HW_RESOURCE_1_SIZE + AMDGPU_GPU_PAGE_SIZE, 1423 PAGE_SIZE, 1424 AMDGPU_GEM_DOMAIN_VRAM, 1425 &adev->mes.resource_1, 1426 &adev->mes.resource_1_gpu_addr, 1427 &adev->mes.resource_1_addr); 1428 if (r) { 1429 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1430 return r; 1431 } 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1438 { 1439 struct amdgpu_device *adev = ip_block->adev; 1440 int pipe; 1441 1442 if (amdgpu_sriov_is_mes_info_enable(adev) || 1443 adev->gfx.enable_cleaner_shader) { 1444 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1445 &adev->mes.resource_1_addr); 1446 } 1447 1448 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1449 kfree(adev->mes.mqd_backup[pipe]); 1450 1451 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1452 &adev->mes.eop_gpu_addr[pipe], 1453 NULL); 1454 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1455 } 1456 1457 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1458 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1459 &adev->gfx.kiq[0].ring.mqd_ptr); 1460 1461 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1462 &adev->mes.ring[0].mqd_gpu_addr, 1463 &adev->mes.ring[0].mqd_ptr); 1464 1465 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1466 amdgpu_ring_fini(&adev->mes.ring[0]); 1467 1468 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1469 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1470 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1471 } 1472 1473 amdgpu_mes_fini(adev); 1474 return 0; 1475 } 1476 1477 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1478 { 1479 uint32_t data; 1480 int i; 1481 struct amdgpu_device *adev = ring->adev; 1482 1483 mutex_lock(&adev->srbm_mutex); 1484 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1485 1486 /* disable the queue if it's active */ 1487 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1488 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1489 for (i = 0; i < adev->usec_timeout; i++) { 1490 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1491 break; 1492 udelay(1); 1493 } 1494 } 1495 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1496 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1497 DOORBELL_EN, 0); 1498 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1499 DOORBELL_HIT, 1); 1500 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1501 1502 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1503 1504 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1505 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1506 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1507 1508 soc21_grbm_select(adev, 0, 0, 0, 0); 1509 mutex_unlock(&adev->srbm_mutex); 1510 } 1511 1512 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1513 { 1514 uint32_t tmp; 1515 struct amdgpu_device *adev = ring->adev; 1516 1517 /* tell RLC which is KIQ queue */ 1518 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1519 tmp &= 0xffffff00; 1520 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1521 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1522 } 1523 1524 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1525 { 1526 uint32_t tmp; 1527 1528 /* tell RLC which is KIQ dequeue */ 1529 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1530 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1531 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1532 } 1533 1534 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1535 { 1536 int r = 0; 1537 struct amdgpu_ip_block *ip_block; 1538 1539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1540 1541 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1542 if (r) { 1543 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1544 return r; 1545 } 1546 1547 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1548 if (r) { 1549 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1550 return r; 1551 } 1552 1553 } 1554 1555 mes_v11_0_enable(adev, true); 1556 1557 mes_v11_0_get_fw_version(adev); 1558 1559 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1560 1561 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1562 if (unlikely(!ip_block)) { 1563 dev_err(adev->dev, "Failed to get MES handle\n"); 1564 return -EINVAL; 1565 } 1566 1567 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1568 if (r) 1569 goto failure; 1570 1571 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1572 adev->mes.enable_legacy_queue_map = true; 1573 else 1574 adev->mes.enable_legacy_queue_map = false; 1575 1576 if (adev->mes.enable_legacy_queue_map) { 1577 r = mes_v11_0_hw_init(ip_block); 1578 if (r) 1579 goto failure; 1580 } 1581 1582 return r; 1583 1584 failure: 1585 mes_v11_0_hw_fini(ip_block); 1586 return r; 1587 } 1588 1589 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1590 { 1591 if (adev->mes.ring[0].sched.ready) { 1592 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1593 adev->mes.ring[0].sched.ready = false; 1594 } 1595 1596 if (amdgpu_sriov_vf(adev)) { 1597 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1598 mes_v11_0_kiq_clear(adev); 1599 } 1600 1601 mes_v11_0_enable(adev, false); 1602 1603 return 0; 1604 } 1605 1606 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1607 { 1608 int r; 1609 struct amdgpu_device *adev = ip_block->adev; 1610 1611 if (adev->mes.ring[0].sched.ready) 1612 goto out; 1613 1614 if (!adev->enable_mes_kiq) { 1615 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1616 r = mes_v11_0_load_microcode(adev, 1617 AMDGPU_MES_SCHED_PIPE, true); 1618 if (r) { 1619 DRM_ERROR("failed to MES fw, r=%d\n", r); 1620 return r; 1621 } 1622 } 1623 1624 mes_v11_0_enable(adev, true); 1625 } 1626 1627 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1628 if (r) 1629 goto failure; 1630 1631 r = mes_v11_0_set_hw_resources(&adev->mes); 1632 if (r) 1633 goto failure; 1634 1635 if (amdgpu_sriov_is_mes_info_enable(adev) || 1636 adev->gfx.enable_cleaner_shader) { 1637 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1638 if (r) { 1639 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1640 goto failure; 1641 } 1642 } 1643 1644 r = mes_v11_0_query_sched_status(&adev->mes); 1645 if (r) { 1646 DRM_ERROR("MES is busy\n"); 1647 goto failure; 1648 } 1649 1650 out: 1651 /* 1652 * Disable KIQ ring usage from the driver once MES is enabled. 1653 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1654 * with MES enabled. 1655 */ 1656 adev->gfx.kiq[0].ring.sched.ready = false; 1657 adev->mes.ring[0].sched.ready = true; 1658 1659 return 0; 1660 1661 failure: 1662 mes_v11_0_hw_fini(ip_block); 1663 return r; 1664 } 1665 1666 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1667 { 1668 return 0; 1669 } 1670 1671 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1672 { 1673 int r; 1674 1675 r = amdgpu_mes_suspend(ip_block->adev); 1676 if (r) 1677 return r; 1678 1679 return mes_v11_0_hw_fini(ip_block); 1680 } 1681 1682 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1683 { 1684 int r; 1685 1686 r = mes_v11_0_hw_init(ip_block); 1687 if (r) 1688 return r; 1689 1690 return amdgpu_mes_resume(ip_block->adev); 1691 } 1692 1693 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1694 { 1695 struct amdgpu_device *adev = ip_block->adev; 1696 int pipe, r; 1697 1698 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1699 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1700 continue; 1701 r = amdgpu_mes_init_microcode(adev, pipe); 1702 if (r) 1703 return r; 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int mes_v11_0_late_init(struct amdgpu_ip_block *ip_block) 1710 { 1711 struct amdgpu_device *adev = ip_block->adev; 1712 1713 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1714 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1715 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1716 amdgpu_mes_self_test(adev); 1717 1718 return 0; 1719 } 1720 1721 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1722 .name = "mes_v11_0", 1723 .early_init = mes_v11_0_early_init, 1724 .late_init = mes_v11_0_late_init, 1725 .sw_init = mes_v11_0_sw_init, 1726 .sw_fini = mes_v11_0_sw_fini, 1727 .hw_init = mes_v11_0_hw_init, 1728 .hw_fini = mes_v11_0_hw_fini, 1729 .suspend = mes_v11_0_suspend, 1730 .resume = mes_v11_0_resume, 1731 }; 1732 1733 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1734 .type = AMD_IP_BLOCK_TYPE_MES, 1735 .major = 11, 1736 .minor = 0, 1737 .rev = 0, 1738 .funcs = &mes_v11_0_ip_funcs, 1739 }; 1740