1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin"); 67 68 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 69 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 72 73 #define MES_EOP_SIZE 2048 74 #define GFX_MES_DRAM_SIZE 0x80000 75 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 76 77 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 78 #define MES11_HUNG_HQD_INFO_OFFSET 4 79 80 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 81 { 82 struct amdgpu_device *adev = ring->adev; 83 84 if (ring->use_doorbell) { 85 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 86 ring->wptr); 87 WDOORBELL64(ring->doorbell_index, ring->wptr); 88 } else { 89 BUG(); 90 } 91 } 92 93 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 94 { 95 return *ring->rptr_cpu_addr; 96 } 97 98 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 99 { 100 u64 wptr; 101 102 if (ring->use_doorbell) 103 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 104 else 105 BUG(); 106 return wptr; 107 } 108 109 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 110 .type = AMDGPU_RING_TYPE_MES, 111 .align_mask = 1, 112 .nop = 0, 113 .support_64bit_ptrs = true, 114 .get_rptr = mes_v11_0_ring_get_rptr, 115 .get_wptr = mes_v11_0_ring_get_wptr, 116 .set_wptr = mes_v11_0_ring_set_wptr, 117 .insert_nop = amdgpu_ring_insert_nop, 118 }; 119 120 static const char *mes_v11_0_opcodes[] = { 121 "SET_HW_RSRC", 122 "SET_SCHEDULING_CONFIG", 123 "ADD_QUEUE", 124 "REMOVE_QUEUE", 125 "PERFORM_YIELD", 126 "SET_GANG_PRIORITY_LEVEL", 127 "SUSPEND", 128 "RESUME", 129 "RESET", 130 "SET_LOG_BUFFER", 131 "CHANGE_GANG_PRORITY", 132 "QUERY_SCHEDULER_STATUS", 133 "PROGRAM_GDS", 134 "SET_DEBUG_VMID", 135 "MISC", 136 "UPDATE_ROOT_PAGE_TABLE", 137 "AMD_LOG", 138 "unused", 139 "unused", 140 "SET_HW_RSRC_1", 141 }; 142 143 static const char *mes_v11_0_misc_opcodes[] = { 144 "WRITE_REG", 145 "INV_GART", 146 "QUERY_STATUS", 147 "READ_REG", 148 "WAIT_REG_MEM", 149 "SET_SHADER_DEBUGGER", 150 }; 151 152 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 153 { 154 const char *op_str = NULL; 155 156 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 157 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 158 159 return op_str; 160 } 161 162 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 163 { 164 const char *op_str = NULL; 165 166 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 167 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 168 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 169 170 return op_str; 171 } 172 173 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 174 void *pkt, int size, 175 int api_status_off) 176 { 177 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 178 signed long timeout = 2100000; /* 2100 ms */ 179 struct amdgpu_device *adev = mes->adev; 180 struct amdgpu_ring *ring = &mes->ring[0]; 181 struct MES_API_STATUS *api_status; 182 union MESAPI__MISC *x_pkt = pkt; 183 const char *op_str, *misc_op_str; 184 unsigned long flags; 185 u64 status_gpu_addr; 186 u32 seq, status_offset; 187 u64 *status_ptr; 188 signed long r; 189 int ret; 190 191 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 192 return -EINVAL; 193 194 if (amdgpu_emu_mode) { 195 timeout *= 100; 196 } else if (amdgpu_sriov_vf(adev)) { 197 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 198 timeout = 15 * 600 * 1000; 199 } 200 201 ret = amdgpu_wb_get(adev, &status_offset); 202 if (ret) 203 return ret; 204 205 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 206 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 207 *status_ptr = 0; 208 209 spin_lock_irqsave(&mes->ring_lock[0], flags); 210 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 211 if (r) 212 goto error_unlock_free; 213 214 seq = ++ring->fence_drv.sync_seq; 215 r = amdgpu_fence_wait_polling(ring, 216 seq - ring->fence_drv.num_fences_mask, 217 timeout); 218 if (r < 1) 219 goto error_undo; 220 221 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 222 api_status->api_completion_fence_addr = status_gpu_addr; 223 api_status->api_completion_fence_value = 1; 224 225 amdgpu_ring_write_multiple(ring, pkt, size / 4); 226 227 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 228 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 229 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 230 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 231 mes_status_pkt.api_status.api_completion_fence_addr = 232 ring->fence_drv.gpu_addr; 233 mes_status_pkt.api_status.api_completion_fence_value = seq; 234 235 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 236 sizeof(mes_status_pkt) / 4); 237 238 amdgpu_ring_commit(ring); 239 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 240 241 op_str = mes_v11_0_get_op_string(x_pkt); 242 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 243 244 if (misc_op_str) 245 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 246 misc_op_str); 247 else if (op_str) 248 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 249 else 250 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 251 x_pkt->header.opcode); 252 253 r = amdgpu_fence_wait_polling(ring, seq, timeout); 254 if (r < 1 || !*status_ptr) { 255 256 if (misc_op_str) 257 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 258 op_str, misc_op_str); 259 else if (op_str) 260 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 261 op_str); 262 else 263 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 264 x_pkt->header.opcode); 265 266 while (halt_if_hws_hang) 267 schedule(); 268 269 r = -ETIMEDOUT; 270 goto error_wb_free; 271 } 272 273 amdgpu_wb_free(adev, status_offset); 274 return 0; 275 276 error_undo: 277 dev_err(adev->dev, "MES ring buffer is full.\n"); 278 amdgpu_ring_undo(ring); 279 280 error_unlock_free: 281 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 282 283 error_wb_free: 284 amdgpu_wb_free(adev, status_offset); 285 return r; 286 } 287 288 static int convert_to_mes_queue_type(int queue_type) 289 { 290 if (queue_type == AMDGPU_RING_TYPE_GFX) 291 return MES_QUEUE_TYPE_GFX; 292 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 293 return MES_QUEUE_TYPE_COMPUTE; 294 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 295 return MES_QUEUE_TYPE_SDMA; 296 else 297 BUG(); 298 return -1; 299 } 300 301 static int convert_to_mes_priority_level(int priority_level) 302 { 303 switch (priority_level) { 304 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 305 return AMD_PRIORITY_LEVEL_LOW; 306 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 307 default: 308 return AMD_PRIORITY_LEVEL_NORMAL; 309 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 310 return AMD_PRIORITY_LEVEL_MEDIUM; 311 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 312 return AMD_PRIORITY_LEVEL_HIGH; 313 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 314 return AMD_PRIORITY_LEVEL_REALTIME; 315 } 316 } 317 318 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 319 struct mes_add_queue_input *input) 320 { 321 struct amdgpu_device *adev = mes->adev; 322 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 323 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 324 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 325 326 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 327 328 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 329 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 330 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 331 332 mes_add_queue_pkt.process_id = input->process_id; 333 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 334 mes_add_queue_pkt.process_va_start = input->process_va_start; 335 mes_add_queue_pkt.process_va_end = input->process_va_end; 336 mes_add_queue_pkt.process_quantum = input->process_quantum; 337 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 338 mes_add_queue_pkt.process_context_array_index = input->process_context_array_index; 339 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 340 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 341 mes_add_queue_pkt.inprocess_gang_priority = 342 convert_to_mes_priority_level(input->inprocess_gang_priority); 343 mes_add_queue_pkt.gang_global_priority_level = 344 convert_to_mes_priority_level(input->gang_global_priority_level); 345 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 346 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 347 348 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 349 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 350 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 351 else 352 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 353 354 mes_add_queue_pkt.queue_type = 355 convert_to_mes_queue_type(input->queue_type); 356 mes_add_queue_pkt.paging = input->paging; 357 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 358 mes_add_queue_pkt.gws_base = input->gws_base; 359 mes_add_queue_pkt.gws_size = input->gws_size; 360 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 361 mes_add_queue_pkt.tma_addr = input->tma_addr; 362 mes_add_queue_pkt.trap_en = input->trap_en; 363 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 364 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 365 366 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 367 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 368 mes_add_queue_pkt.gds_size = input->queue_size; 369 370 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 371 372 return mes_v11_0_submit_pkt_and_poll_completion(mes, 373 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 374 offsetof(union MESAPI__ADD_QUEUE, api_status)); 375 } 376 377 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 378 struct mes_remove_queue_input *input) 379 { 380 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 381 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 382 383 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 384 385 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 386 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 387 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 388 389 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 390 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 391 mes_remove_queue_pkt.queue_type = 392 convert_to_mes_queue_type(input->queue_type); 393 394 if (mes_rev >= 0x60) 395 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 396 397 return mes_v11_0_submit_pkt_and_poll_completion(mes, 398 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 399 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 400 } 401 402 static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev) 403 { 404 /* Disable the pipe reset until the CPFW fully support it.*/ 405 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 406 return false; 407 } 408 static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 409 u32 me, u32 pipe, u32 queue) 410 { 411 uint32_t reset_pipe = 0, clean_pipe = 0; 412 int r; 413 414 if (!mes_v11_0_pipe_reset_support(adev)) 415 return -EOPNOTSUPP; 416 417 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 418 mutex_lock(&adev->srbm_mutex); 419 soc21_grbm_select(adev, me, pipe, queue, 0); 420 421 switch (pipe) { 422 case 0: 423 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 424 PFP_PIPE0_RESET, 1); 425 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 426 ME_PIPE0_RESET, 1); 427 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 428 PFP_PIPE0_RESET, 0); 429 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 430 ME_PIPE0_RESET, 0); 431 break; 432 case 1: 433 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 434 PFP_PIPE1_RESET, 1); 435 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 436 ME_PIPE1_RESET, 1); 437 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 438 PFP_PIPE1_RESET, 0); 439 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 440 ME_PIPE1_RESET, 0); 441 break; 442 default: 443 break; 444 } 445 446 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 447 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 448 449 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 450 RS64_FW_UC_START_ADDR_LO; 451 soc21_grbm_select(adev, 0, 0, 0, 0); 452 mutex_unlock(&adev->srbm_mutex); 453 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 454 455 dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n", 456 r == 0 ? "successfully" : "failed"); 457 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 458 * so the pipe reset status relies on the later gfx ring test result. 459 */ 460 return 0; 461 } 462 463 /* 464 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 465 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 466 * asserted; only then clear the pipe reset bit. 467 * Caller must hold adev->srbm_mutex. 468 */ 469 static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 470 u32 pipe) 471 { 472 unsigned int q; 473 474 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 475 soc21_grbm_select(adev, me, pipe, q, 0); 476 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 477 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 478 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 479 } 480 } 481 482 static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 483 u32 me, u32 pipe, u32 queue) 484 { 485 uint32_t reset_val, clean_val; 486 int r; 487 488 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 489 mutex_lock(&adev->srbm_mutex); 490 soc21_grbm_select(adev, me, pipe, queue, 0); 491 492 if (adev->gfx.rs64_enable) { 493 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 494 clean_val = reset_val; 495 496 switch (pipe) { 497 case 0: 498 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 499 MEC_PIPE0_RESET, 1); 500 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 501 MEC_PIPE0_RESET, 0); 502 break; 503 case 1: 504 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 505 MEC_PIPE1_RESET, 1); 506 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 507 MEC_PIPE1_RESET, 0); 508 break; 509 case 2: 510 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 511 MEC_PIPE2_RESET, 1); 512 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 513 MEC_PIPE2_RESET, 0); 514 break; 515 case 3: 516 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 517 MEC_PIPE3_RESET, 1); 518 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 519 MEC_PIPE3_RESET, 0); 520 break; 521 default: 522 break; 523 } 524 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 525 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 526 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 527 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 528 RS64_FW_UC_START_ADDR_LO; 529 } else { 530 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 531 clean_val = reset_val; 532 533 if (me == 1) { 534 switch (pipe) { 535 case 0: 536 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 537 MEC_ME1_PIPE0_RESET, 1); 538 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 539 MEC_ME1_PIPE0_RESET, 0); 540 break; 541 case 1: 542 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 543 MEC_ME1_PIPE1_RESET, 1); 544 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 545 MEC_ME1_PIPE1_RESET, 0); 546 break; 547 case 2: 548 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 549 MEC_ME1_PIPE2_RESET, 1); 550 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 551 MEC_ME1_PIPE2_RESET, 0); 552 break; 553 case 3: 554 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 555 MEC_ME1_PIPE3_RESET, 1); 556 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 557 MEC_ME1_PIPE3_RESET, 0); 558 break; 559 default: 560 break; 561 } 562 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 563 } else { 564 switch (pipe) { 565 case 0: 566 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 567 MEC_ME2_PIPE0_RESET, 1); 568 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 569 MEC_ME2_PIPE0_RESET, 0); 570 break; 571 case 1: 572 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 573 MEC_ME2_PIPE1_RESET, 1); 574 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 575 MEC_ME2_PIPE1_RESET, 0); 576 break; 577 case 2: 578 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 579 MEC_ME2_PIPE2_RESET, 1); 580 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 581 MEC_ME2_PIPE2_RESET, 0); 582 break; 583 case 3: 584 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 585 MEC_ME2_PIPE3_RESET, 1); 586 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 587 MEC_ME2_PIPE3_RESET, 0); 588 break; 589 default: 590 break; 591 } 592 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 593 } 594 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 595 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 596 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 597 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 598 } 599 600 soc21_grbm_select(adev, 0, 0, 0, 0); 601 mutex_unlock(&adev->srbm_mutex); 602 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 603 604 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 605 me, pipe, queue, r == 0 ? "successfully" : "failed"); 606 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 607 * reset status relies on the compute ring test result. 608 */ 609 return 0; 610 } 611 612 static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 613 uint32_t me_id, uint32_t pipe_id, 614 uint32_t queue_id, uint32_t vmid) 615 { 616 struct amdgpu_device *adev = mes->adev; 617 618 if (queue_type == AMDGPU_RING_TYPE_GFX) 619 return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 620 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 621 return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 622 else 623 return -EOPNOTSUPP; 624 } 625 626 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 627 uint32_t me_id, uint32_t pipe_id, 628 uint32_t queue_id, uint32_t vmid) 629 { 630 struct amdgpu_device *adev = mes->adev; 631 uint32_t value, reg; 632 int i, r = 0; 633 634 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 635 636 if (queue_type == AMDGPU_RING_TYPE_GFX) { 637 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 638 me_id, pipe_id, queue_id, vmid); 639 640 mutex_lock(&adev->gfx.reset_sem_mutex); 641 gfx_v11_0_request_gfx_index_mutex(adev, true); 642 /* all se allow writes */ 643 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 644 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 645 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 646 if (pipe_id == 0) 647 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 648 else 649 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 650 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 651 gfx_v11_0_request_gfx_index_mutex(adev, false); 652 mutex_unlock(&adev->gfx.reset_sem_mutex); 653 654 mutex_lock(&adev->srbm_mutex); 655 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 656 /* wait till dequeue take effects */ 657 for (i = 0; i < adev->usec_timeout; i++) { 658 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 659 break; 660 udelay(1); 661 } 662 if (i >= adev->usec_timeout) { 663 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 664 r = -ETIMEDOUT; 665 } 666 667 soc21_grbm_select(adev, 0, 0, 0, 0); 668 mutex_unlock(&adev->srbm_mutex); 669 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 670 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 671 me_id, pipe_id, queue_id); 672 mutex_lock(&adev->srbm_mutex); 673 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 674 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 675 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 676 677 /* wait till dequeue take effects */ 678 for (i = 0; i < adev->usec_timeout; i++) { 679 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 680 break; 681 udelay(1); 682 } 683 if (i >= adev->usec_timeout) { 684 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 685 r = -ETIMEDOUT; 686 } 687 soc21_grbm_select(adev, 0, 0, 0, 0); 688 mutex_unlock(&adev->srbm_mutex); 689 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 690 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 691 me_id, pipe_id, queue_id); 692 switch (me_id) { 693 case 1: 694 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 695 break; 696 case 0: 697 default: 698 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 699 break; 700 } 701 702 value = 1 << queue_id; 703 WREG32(reg, value); 704 /* wait for queue reset done */ 705 for (i = 0; i < adev->usec_timeout; i++) { 706 if (!(RREG32(reg) & value)) 707 break; 708 udelay(1); 709 } 710 if (i >= adev->usec_timeout) { 711 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 712 r = -ETIMEDOUT; 713 } 714 } 715 716 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 717 return r; 718 } 719 720 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 721 struct mes_map_legacy_queue_input *input) 722 { 723 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 724 725 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 726 727 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 728 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 729 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 730 731 mes_add_queue_pkt.pipe_id = input->pipe_id; 732 mes_add_queue_pkt.queue_id = input->queue_id; 733 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 734 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 735 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 736 mes_add_queue_pkt.queue_type = 737 convert_to_mes_queue_type(input->queue_type); 738 mes_add_queue_pkt.map_legacy_kq = 1; 739 740 return mes_v11_0_submit_pkt_and_poll_completion(mes, 741 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 742 offsetof(union MESAPI__ADD_QUEUE, api_status)); 743 } 744 745 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 746 struct mes_unmap_legacy_queue_input *input) 747 { 748 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 749 750 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 751 752 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 753 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 754 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 755 756 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 757 mes_remove_queue_pkt.gang_context_addr = 0; 758 759 mes_remove_queue_pkt.pipe_id = input->pipe_id; 760 mes_remove_queue_pkt.queue_id = input->queue_id; 761 762 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 763 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 764 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 765 mes_remove_queue_pkt.tf_data = 766 lower_32_bits(input->trail_fence_data); 767 } else { 768 mes_remove_queue_pkt.unmap_legacy_queue = 1; 769 mes_remove_queue_pkt.queue_type = 770 convert_to_mes_queue_type(input->queue_type); 771 } 772 773 if (input->action == RESET_QUEUES && 774 (mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x60) 775 mes_remove_queue_pkt.remove_queue_after_reset = 1; 776 777 778 return mes_v11_0_submit_pkt_and_poll_completion(mes, 779 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 780 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 781 } 782 783 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 784 struct mes_suspend_gang_input *input) 785 { 786 union MESAPI__SUSPEND mes_suspend_gang_pkt; 787 788 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 789 790 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 791 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 792 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 793 794 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 795 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 796 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 797 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 798 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 799 800 return mes_v11_0_submit_pkt_and_poll_completion(mes, 801 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 802 offsetof(union MESAPI__SUSPEND, api_status)); 803 } 804 805 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 806 struct mes_resume_gang_input *input) 807 { 808 union MESAPI__RESUME mes_resume_gang_pkt; 809 810 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 811 812 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 813 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 814 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 815 816 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 817 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 818 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 819 820 return mes_v11_0_submit_pkt_and_poll_completion(mes, 821 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 822 offsetof(union MESAPI__RESUME, api_status)); 823 } 824 825 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 826 { 827 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 828 829 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 830 831 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 832 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 833 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 834 835 return mes_v11_0_submit_pkt_and_poll_completion(mes, 836 &mes_status_pkt, sizeof(mes_status_pkt), 837 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 838 } 839 840 /* 841 * QUERY_SCHEDULER_STATUS: get proc/gang context array sizes 842 */ 843 static int mes_v11_0_query_ctx_array_sizes(struct amdgpu_mes *mes) 844 { 845 struct amdgpu_device *adev = mes->adev; 846 union MESAPI__QUERY_MES_STATUS mes_query_pkt; 847 int r; 848 849 if (!mes->ctx_array_size_cpu_ptr) 850 return -EINVAL; 851 852 /* Clear the output buffer */ 853 mes->ctx_array_size_cpu_ptr[0] = 0; /* proc_ctx_array_size */ 854 mes->ctx_array_size_cpu_ptr[1] = 0; /* gang_ctx_array_size */ 855 856 memset(&mes_query_pkt, 0, sizeof(mes_query_pkt)); 857 858 mes_query_pkt.header.type = MES_API_TYPE_SCHEDULER; 859 mes_query_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 860 mes_query_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 861 862 mes_query_pkt.subopcode = MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE; 863 864 /* 865 * MES FW will write the array sizes to these GPU addresses: 866 * proc_ctx_array_size_addr -> uint32_t N (e.g., 50) 867 * gang_ctx_array_size_addr -> uint32_t M (e.g., 300) 868 */ 869 mes_query_pkt.ctx_array_size.proc_ctx_array_size_addr = 870 mes->ctx_array_size_gpu_addr; 871 mes_query_pkt.ctx_array_size.gang_ctx_array_size_addr = 872 mes->ctx_array_size_gpu_addr + sizeof(uint32_t); 873 874 mes_query_pkt.api_status.api_completion_fence_addr = 875 mes->ring[0].fence_drv.gpu_addr; 876 mes_query_pkt.api_status.api_completion_fence_value = 877 ++mes->ring[0].fence_drv.sync_seq; 878 879 r = mes_v11_0_submit_pkt_and_poll_completion(mes, 880 &mes_query_pkt, sizeof(mes_query_pkt), 881 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 882 if (r) { 883 dev_err(adev->dev, 884 "MES QUERY_SCHEDULER_STATUS (GET_CTX_ARRAY_SIZE) failed, r=%d\n", r); 885 return r; 886 } 887 888 /* MES has written the sizes - now set up bitmaps */ 889 return amdgpu_mes_rs64mem_setup_bitmaps(mes); 890 } 891 892 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 893 struct mes_misc_op_input *input) 894 { 895 union MESAPI__MISC misc_pkt; 896 897 memset(&misc_pkt, 0, sizeof(misc_pkt)); 898 899 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 900 misc_pkt.header.opcode = MES_SCH_API_MISC; 901 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 902 903 switch (input->op) { 904 case MES_MISC_OP_READ_REG: 905 misc_pkt.opcode = MESAPI_MISC__READ_REG; 906 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 907 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 908 break; 909 case MES_MISC_OP_WRITE_REG: 910 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 911 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 912 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 913 break; 914 case MES_MISC_OP_WRM_REG_WAIT: 915 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 916 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 917 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 918 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 919 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 920 misc_pkt.wait_reg_mem.reg_offset2 = 0; 921 break; 922 case MES_MISC_OP_WRM_REG_WR_WAIT: 923 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 924 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 925 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 926 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 927 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 928 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 929 break; 930 case MES_MISC_OP_SET_SHADER_DEBUGGER: 931 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 932 misc_pkt.set_shader_debugger.process_context_addr = 933 input->set_shader_debugger.process_context_addr; 934 misc_pkt.set_shader_debugger.flags.u32all = 935 input->set_shader_debugger.flags.u32all; 936 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 937 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 938 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 939 input->set_shader_debugger.tcp_watch_cntl, 940 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 941 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 942 break; 943 case MES_MISC_OP_CHANGE_CONFIG: 944 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 945 dev_warn_once(mes->adev->dev, 946 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 947 return 0; 948 } 949 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 950 misc_pkt.change_config.opcode = 951 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 952 misc_pkt.change_config.option.bits.limit_single_process = 953 input->change_config.option.limit_single_process; 954 break; 955 956 default: 957 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 958 return -EINVAL; 959 } 960 961 return mes_v11_0_submit_pkt_and_poll_completion(mes, 962 &misc_pkt, sizeof(misc_pkt), 963 offsetof(union MESAPI__MISC, api_status)); 964 } 965 966 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 967 { 968 int i; 969 struct amdgpu_device *adev = mes->adev; 970 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 971 972 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 973 974 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 975 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 976 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 977 978 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 979 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 980 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 981 mes_set_hw_res_pkt.paging_vmid = 0; 982 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 983 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 984 mes->query_status_fence_gpu_addr[0]; 985 986 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 987 mes_set_hw_res_pkt.compute_hqd_mask[i] = 988 mes->compute_hqd_mask[i]; 989 990 for (i = 0; i < MAX_GFX_PIPES; i++) 991 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 992 mes->gfx_hqd_mask[i]; 993 994 for (i = 0; i < MAX_SDMA_PIPES; i++) 995 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 996 997 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 998 mes_set_hw_res_pkt.aggregated_doorbells[i] = 999 mes->aggregated_doorbells[i]; 1000 1001 for (i = 0; i < 5; i++) { 1002 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 1003 mes_set_hw_res_pkt.mmhub_base[i] = 1004 adev->reg_offset[MMHUB_HWIP][0][i]; 1005 mes_set_hw_res_pkt.osssys_base[i] = 1006 adev->reg_offset[OSSSYS_HWIP][0][i]; 1007 } 1008 1009 mes_set_hw_res_pkt.disable_reset = 1; 1010 mes_set_hw_res_pkt.disable_mes_log = 1; 1011 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 1012 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 1013 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 1014 mes_set_hw_res_pkt.oversubscription_timer = 50; 1015 1016 if (amdgpu_mes_log_enable) { 1017 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 1018 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 1019 mes->event_log_gpu_addr; 1020 } 1021 1022 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 1023 mes_set_hw_res_pkt.limit_single_process = 1; 1024 1025 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1026 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1027 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 1028 } 1029 1030 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 1031 { 1032 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 1033 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 1034 1035 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 1036 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 1037 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1038 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 1039 1040 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 1041 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 1042 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 1043 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 1044 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 1045 } 1046 1047 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1048 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1049 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 1050 } 1051 1052 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 1053 struct mes_reset_queue_input *input) 1054 { 1055 union MESAPI__RESET mes_reset_queue_pkt; 1056 1057 if (input->use_mmio) { 1058 int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type, 1059 input->me_id, input->pipe_id, 1060 input->queue_id, input->vmid); 1061 if (r) 1062 return mes_v11_0_reset_pipe_mmio(mes, input->queue_type, 1063 input->me_id, input->pipe_id, 1064 input->queue_id, input->vmid); 1065 return 0; 1066 } 1067 1068 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1069 1070 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1071 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1072 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1073 1074 mes_reset_queue_pkt.queue_type = 1075 convert_to_mes_queue_type(input->queue_type); 1076 1077 if (input->legacy_gfx) { 1078 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1079 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1080 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1081 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1082 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1083 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1084 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1085 } else { 1086 mes_reset_queue_pkt.reset_queue_only = 1; 1087 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1088 } 1089 1090 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1091 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1092 offsetof(union MESAPI__RESET, api_status)); 1093 } 1094 1095 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1096 struct mes_detect_and_reset_queue_input *input) 1097 { 1098 union MESAPI__RESET mes_reset_queue_pkt; 1099 1100 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1101 1102 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1103 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1104 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1105 1106 mes_reset_queue_pkt.queue_type = 1107 convert_to_mes_queue_type(input->queue_type); 1108 mes_reset_queue_pkt.doorbell_offset_addr = 1109 mes->hung_queue_db_array_gpu_addr[0]; 1110 1111 if (input->detect_only) 1112 mes_reset_queue_pkt.hang_detect_only = 1; 1113 else 1114 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1115 1116 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1117 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1118 offsetof(union MESAPI__RESET, api_status)); 1119 } 1120 1121 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 1122 .add_hw_queue = mes_v11_0_add_hw_queue, 1123 .remove_hw_queue = mes_v11_0_remove_hw_queue, 1124 .map_legacy_queue = mes_v11_0_map_legacy_queue, 1125 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 1126 .suspend_gang = mes_v11_0_suspend_gang, 1127 .resume_gang = mes_v11_0_resume_gang, 1128 .misc_op = mes_v11_0_misc_op, 1129 .reset_hw_queue = mes_v11_0_reset_hw_queue, 1130 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 1131 }; 1132 1133 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1134 enum amdgpu_mes_pipe pipe) 1135 { 1136 int r; 1137 const struct mes_firmware_header_v1_0 *mes_hdr; 1138 const __le32 *fw_data; 1139 unsigned fw_size; 1140 1141 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1142 adev->mes.fw[pipe]->data; 1143 1144 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1145 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1146 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1147 1148 r = amdgpu_bo_create_reserved(adev, fw_size, 1149 PAGE_SIZE, 1150 AMDGPU_GEM_DOMAIN_VRAM | 1151 AMDGPU_GEM_DOMAIN_GTT, 1152 &adev->mes.ucode_fw_obj[pipe], 1153 &adev->mes.ucode_fw_gpu_addr[pipe], 1154 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1155 if (r) { 1156 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1157 return r; 1158 } 1159 1160 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1161 1162 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1163 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1164 1165 return 0; 1166 } 1167 1168 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1169 enum amdgpu_mes_pipe pipe) 1170 { 1171 int r; 1172 const struct mes_firmware_header_v1_0 *mes_hdr; 1173 const __le32 *fw_data; 1174 unsigned fw_size; 1175 1176 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1177 adev->mes.fw[pipe]->data; 1178 1179 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1180 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1181 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1182 1183 if (fw_size > GFX_MES_DRAM_SIZE) { 1184 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 1185 pipe, fw_size, GFX_MES_DRAM_SIZE); 1186 return -EINVAL; 1187 } 1188 1189 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 1190 64 * 1024, 1191 AMDGPU_GEM_DOMAIN_VRAM | 1192 AMDGPU_GEM_DOMAIN_GTT, 1193 &adev->mes.data_fw_obj[pipe], 1194 &adev->mes.data_fw_gpu_addr[pipe], 1195 (void **)&adev->mes.data_fw_ptr[pipe]); 1196 if (r) { 1197 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1198 return r; 1199 } 1200 1201 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1202 1203 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1204 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1205 1206 return 0; 1207 } 1208 1209 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 1210 enum amdgpu_mes_pipe pipe) 1211 { 1212 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1213 &adev->mes.data_fw_gpu_addr[pipe], 1214 (void **)&adev->mes.data_fw_ptr[pipe]); 1215 1216 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1217 &adev->mes.ucode_fw_gpu_addr[pipe], 1218 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1219 } 1220 1221 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 1222 { 1223 int pipe; 1224 1225 /* return early if we have already fetched these */ 1226 if (adev->mes.sched_version && adev->mes.kiq_version) 1227 return; 1228 1229 /* get MES scheduler/KIQ versions */ 1230 mutex_lock(&adev->srbm_mutex); 1231 1232 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1233 soc21_grbm_select(adev, 3, pipe, 0, 0); 1234 1235 if (pipe == AMDGPU_MES_SCHED_PIPE) 1236 adev->mes.sched_version = 1237 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1238 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1239 adev->mes.kiq_version = 1240 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1241 } 1242 1243 soc21_grbm_select(adev, 0, 0, 0, 0); 1244 mutex_unlock(&adev->srbm_mutex); 1245 } 1246 1247 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 1248 { 1249 uint64_t ucode_addr; 1250 uint32_t pipe, data = 0; 1251 1252 if (enable) { 1253 if (amdgpu_mes_log_enable) { 1254 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1255 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1256 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1257 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1258 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1259 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1260 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1261 } 1262 1263 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1264 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1265 data = REG_SET_FIELD(data, CP_MES_CNTL, 1266 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 1267 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1268 1269 mutex_lock(&adev->srbm_mutex); 1270 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1271 if (!adev->enable_mes_kiq && 1272 pipe == AMDGPU_MES_KIQ_PIPE) 1273 continue; 1274 1275 soc21_grbm_select(adev, 3, pipe, 0, 0); 1276 1277 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1278 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1279 lower_32_bits(ucode_addr)); 1280 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1281 upper_32_bits(ucode_addr)); 1282 } 1283 soc21_grbm_select(adev, 0, 0, 0, 0); 1284 mutex_unlock(&adev->srbm_mutex); 1285 1286 /* unhalt MES and activate pipe0 */ 1287 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1288 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1289 adev->enable_mes_kiq ? 1 : 0); 1290 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1291 1292 if (amdgpu_emu_mode) 1293 msleep(100); 1294 else 1295 udelay(500); 1296 } else { 1297 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1298 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1299 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1300 data = REG_SET_FIELD(data, CP_MES_CNTL, 1301 MES_INVALIDATE_ICACHE, 1); 1302 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1303 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1304 adev->enable_mes_kiq ? 1 : 0); 1305 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1306 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1307 } 1308 } 1309 1310 /* This function is for backdoor MES firmware */ 1311 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1312 enum amdgpu_mes_pipe pipe, bool prime_icache) 1313 { 1314 int r; 1315 uint32_t data; 1316 uint64_t ucode_addr; 1317 1318 mes_v11_0_enable(adev, false); 1319 1320 if (!adev->mes.fw[pipe]) 1321 return -EINVAL; 1322 1323 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1324 if (r) 1325 return r; 1326 1327 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1328 if (r) { 1329 mes_v11_0_free_ucode_buffers(adev, pipe); 1330 return r; 1331 } 1332 1333 mutex_lock(&adev->srbm_mutex); 1334 /* me=3, pipe=0, queue=0 */ 1335 soc21_grbm_select(adev, 3, pipe, 0, 0); 1336 1337 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1338 1339 /* set ucode start address */ 1340 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1341 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1342 lower_32_bits(ucode_addr)); 1343 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1344 upper_32_bits(ucode_addr)); 1345 1346 /* set ucode fimrware address */ 1347 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1348 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1349 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1350 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1351 1352 /* set ucode instruction cache boundary to 2M-1 */ 1353 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1354 1355 /* set ucode data firmware address */ 1356 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1357 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1358 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1359 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1360 1361 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1362 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1363 1364 if (prime_icache) { 1365 /* invalidate ICACHE */ 1366 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1367 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1368 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1369 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1370 1371 /* prime the ICACHE. */ 1372 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1373 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1374 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1375 } 1376 1377 soc21_grbm_select(adev, 0, 0, 0, 0); 1378 mutex_unlock(&adev->srbm_mutex); 1379 1380 return 0; 1381 } 1382 1383 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1384 enum amdgpu_mes_pipe pipe) 1385 { 1386 int r; 1387 u32 *eop; 1388 1389 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1390 AMDGPU_GEM_DOMAIN_GTT, 1391 &adev->mes.eop_gpu_obj[pipe], 1392 &adev->mes.eop_gpu_addr[pipe], 1393 (void **)&eop); 1394 if (r) { 1395 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1396 return r; 1397 } 1398 1399 memset(eop, 0, 1400 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1401 1402 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1403 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1404 1405 return 0; 1406 } 1407 1408 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1409 { 1410 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1411 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1412 uint32_t tmp; 1413 1414 memset(mqd, 0, sizeof(*mqd)); 1415 1416 mqd->header = 0xC0310800; 1417 mqd->compute_pipelinestat_enable = 0x00000001; 1418 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1419 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1420 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1421 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1422 mqd->compute_misc_reserved = 0x00000007; 1423 1424 eop_base_addr = ring->eop_gpu_addr >> 8; 1425 1426 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1427 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1428 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1429 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1430 1431 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1432 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1433 mqd->cp_hqd_eop_control = tmp; 1434 1435 /* disable the queue if it's active */ 1436 ring->wptr = 0; 1437 mqd->cp_hqd_pq_rptr = 0; 1438 mqd->cp_hqd_pq_wptr_lo = 0; 1439 mqd->cp_hqd_pq_wptr_hi = 0; 1440 1441 /* set the pointer to the MQD */ 1442 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1443 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1444 1445 /* set MQD vmid to 0 */ 1446 tmp = regCP_MQD_CONTROL_DEFAULT; 1447 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1448 mqd->cp_mqd_control = tmp; 1449 1450 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1451 hqd_gpu_addr = ring->gpu_addr >> 8; 1452 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1453 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1454 1455 /* set the wb address whether it's enabled or not */ 1456 wb_gpu_addr = ring->rptr_gpu_addr; 1457 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1458 mqd->cp_hqd_pq_rptr_report_addr_hi = 1459 upper_32_bits(wb_gpu_addr) & 0xffff; 1460 1461 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1462 wb_gpu_addr = ring->wptr_gpu_addr; 1463 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1464 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1465 1466 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1467 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1468 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1469 (order_base_2(ring->ring_size / 4) - 1)); 1470 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1471 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1474 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1476 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1477 mqd->cp_hqd_pq_control = tmp; 1478 1479 /* enable doorbell */ 1480 tmp = 0; 1481 if (ring->use_doorbell) { 1482 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1483 DOORBELL_OFFSET, ring->doorbell_index); 1484 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1485 DOORBELL_EN, 1); 1486 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1487 DOORBELL_SOURCE, 0); 1488 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1489 DOORBELL_HIT, 0); 1490 } else 1491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1492 DOORBELL_EN, 0); 1493 mqd->cp_hqd_pq_doorbell_control = tmp; 1494 1495 mqd->cp_hqd_vmid = 0; 1496 /* activate the queue */ 1497 mqd->cp_hqd_active = 1; 1498 1499 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1500 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1501 PRELOAD_SIZE, 0x55); 1502 mqd->cp_hqd_persistent_state = tmp; 1503 1504 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1505 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1506 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1507 1508 amdgpu_device_flush_hdp(ring->adev, NULL); 1509 return 0; 1510 } 1511 1512 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1513 { 1514 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1515 struct amdgpu_device *adev = ring->adev; 1516 uint32_t data = 0; 1517 1518 mutex_lock(&adev->srbm_mutex); 1519 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1520 1521 /* set CP_HQD_VMID.VMID = 0. */ 1522 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1523 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1524 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1525 1526 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1527 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1528 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1529 DOORBELL_EN, 0); 1530 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1531 1532 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1533 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1534 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1535 1536 /* set CP_MQD_CONTROL.VMID=0 */ 1537 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1538 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1539 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1540 1541 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1542 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1543 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1544 1545 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1546 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1547 mqd->cp_hqd_pq_rptr_report_addr_lo); 1548 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1549 mqd->cp_hqd_pq_rptr_report_addr_hi); 1550 1551 /* set CP_HQD_PQ_CONTROL */ 1552 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1553 1554 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1555 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1556 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1557 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1558 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1559 1560 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1561 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1562 mqd->cp_hqd_pq_doorbell_control); 1563 1564 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1565 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1566 1567 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1568 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1569 1570 soc21_grbm_select(adev, 0, 0, 0, 0); 1571 mutex_unlock(&adev->srbm_mutex); 1572 } 1573 1574 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1575 { 1576 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1577 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1578 int r; 1579 1580 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1581 return -EINVAL; 1582 1583 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1584 if (r) { 1585 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1586 return r; 1587 } 1588 1589 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1590 1591 return amdgpu_ring_test_helper(kiq_ring); 1592 } 1593 1594 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1595 enum amdgpu_mes_pipe pipe) 1596 { 1597 struct amdgpu_ring *ring; 1598 int r; 1599 1600 if (pipe == AMDGPU_MES_KIQ_PIPE) 1601 ring = &adev->gfx.kiq[0].ring; 1602 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1603 ring = &adev->mes.ring[0]; 1604 else 1605 BUG(); 1606 1607 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1608 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1609 *(ring->wptr_cpu_addr) = 0; 1610 *(ring->rptr_cpu_addr) = 0; 1611 amdgpu_ring_clear_ring(ring); 1612 } 1613 1614 r = mes_v11_0_mqd_init(ring); 1615 if (r) 1616 return r; 1617 1618 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1619 r = mes_v11_0_kiq_enable_queue(adev); 1620 if (r) 1621 return r; 1622 } else { 1623 mes_v11_0_queue_init_register(ring); 1624 } 1625 1626 return 0; 1627 } 1628 1629 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1630 { 1631 struct amdgpu_ring *ring; 1632 1633 ring = &adev->mes.ring[0]; 1634 1635 ring->funcs = &mes_v11_0_ring_funcs; 1636 1637 ring->me = 3; 1638 ring->pipe = 0; 1639 ring->queue = 0; 1640 1641 ring->ring_obj = NULL; 1642 ring->use_doorbell = true; 1643 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1644 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1645 ring->no_scheduler = true; 1646 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1647 1648 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1649 AMDGPU_RING_PRIO_DEFAULT, NULL); 1650 } 1651 1652 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1653 { 1654 struct amdgpu_ring *ring; 1655 1656 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1657 1658 ring = &adev->gfx.kiq[0].ring; 1659 1660 ring->me = 3; 1661 ring->pipe = 1; 1662 ring->queue = 0; 1663 1664 ring->adev = NULL; 1665 ring->ring_obj = NULL; 1666 ring->use_doorbell = true; 1667 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1668 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1669 ring->no_scheduler = true; 1670 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1671 ring->me, ring->pipe, ring->queue); 1672 1673 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1674 AMDGPU_RING_PRIO_DEFAULT, NULL); 1675 } 1676 1677 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1678 enum amdgpu_mes_pipe pipe) 1679 { 1680 int r, mqd_size = sizeof(struct v11_compute_mqd); 1681 struct amdgpu_ring *ring; 1682 1683 if (pipe == AMDGPU_MES_KIQ_PIPE) 1684 ring = &adev->gfx.kiq[0].ring; 1685 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1686 ring = &adev->mes.ring[0]; 1687 else 1688 BUG(); 1689 1690 if (ring->mqd_obj) 1691 return 0; 1692 1693 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1694 AMDGPU_GEM_DOMAIN_VRAM | 1695 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1696 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1697 if (r) { 1698 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1699 return r; 1700 } 1701 1702 memset(ring->mqd_ptr, 0, mqd_size); 1703 1704 /* prepare MQD backup */ 1705 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1706 if (!adev->mes.mqd_backup[pipe]) { 1707 dev_warn(adev->dev, 1708 "no memory to create MQD backup for ring %s\n", 1709 ring->name); 1710 return -ENOMEM; 1711 } 1712 1713 return 0; 1714 } 1715 1716 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1717 { 1718 struct amdgpu_device *adev = ip_block->adev; 1719 int pipe, r, bo_size; 1720 1721 adev->mes.funcs = &mes_v11_0_funcs; 1722 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1723 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1724 1725 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1726 1727 r = amdgpu_mes_init(adev); 1728 if (r) 1729 return r; 1730 1731 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1732 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1733 continue; 1734 1735 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1736 if (r) 1737 return r; 1738 1739 r = mes_v11_0_mqd_sw_init(adev, pipe); 1740 if (r) 1741 return r; 1742 } 1743 1744 if (adev->enable_mes_kiq) { 1745 r = mes_v11_0_kiq_ring_init(adev); 1746 if (r) 1747 return r; 1748 } 1749 1750 r = mes_v11_0_ring_init(adev); 1751 if (r) 1752 return r; 1753 1754 bo_size = AMDGPU_GPU_PAGE_SIZE; 1755 if (amdgpu_sriov_is_mes_info_enable(adev)) 1756 bo_size += MES11_HW_RESOURCE_1_SIZE; 1757 1758 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1759 r = amdgpu_bo_create_kernel(adev, 1760 bo_size, 1761 PAGE_SIZE, 1762 AMDGPU_GEM_DOMAIN_VRAM, 1763 &adev->mes.resource_1[0], 1764 &adev->mes.resource_1_gpu_addr[0], 1765 &adev->mes.resource_1_addr[0]); 1766 if (r) { 1767 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1768 return r; 1769 } 1770 1771 return 0; 1772 } 1773 1774 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1775 { 1776 struct amdgpu_device *adev = ip_block->adev; 1777 int pipe; 1778 1779 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1780 &adev->mes.resource_1_addr[0]); 1781 1782 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1783 kfree(adev->mes.mqd_backup[pipe]); 1784 1785 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1786 &adev->mes.eop_gpu_addr[pipe], 1787 NULL); 1788 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1789 } 1790 1791 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1792 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1793 &adev->gfx.kiq[0].ring.mqd_ptr); 1794 1795 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1796 &adev->mes.ring[0].mqd_gpu_addr, 1797 &adev->mes.ring[0].mqd_ptr); 1798 1799 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1800 amdgpu_ring_fini(&adev->mes.ring[0]); 1801 1802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1803 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1804 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1805 } 1806 1807 amdgpu_mes_fini(adev); 1808 return 0; 1809 } 1810 1811 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1812 { 1813 uint32_t data; 1814 int i; 1815 struct amdgpu_device *adev = ring->adev; 1816 1817 mutex_lock(&adev->srbm_mutex); 1818 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1819 1820 /* disable the queue if it's active */ 1821 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1822 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1823 for (i = 0; i < adev->usec_timeout; i++) { 1824 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1825 break; 1826 udelay(1); 1827 } 1828 } 1829 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1830 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1831 DOORBELL_EN, 0); 1832 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1833 DOORBELL_HIT, 1); 1834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1835 1836 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1837 1838 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1839 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1840 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1841 1842 soc21_grbm_select(adev, 0, 0, 0, 0); 1843 mutex_unlock(&adev->srbm_mutex); 1844 } 1845 1846 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1847 { 1848 uint32_t tmp; 1849 struct amdgpu_device *adev = ring->adev; 1850 1851 /* tell RLC which is KIQ queue */ 1852 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1853 tmp &= 0xffffff00; 1854 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1855 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1856 } 1857 1858 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1859 { 1860 uint32_t tmp; 1861 1862 /* tell RLC which is KIQ dequeue */ 1863 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1864 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1865 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1866 } 1867 1868 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1869 { 1870 int r = 0; 1871 struct amdgpu_ip_block *ip_block; 1872 1873 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1874 1875 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1876 if (r) { 1877 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1878 return r; 1879 } 1880 1881 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1882 if (r) { 1883 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1884 return r; 1885 } 1886 1887 } 1888 1889 mes_v11_0_enable(adev, true); 1890 1891 mes_v11_0_get_fw_version(adev); 1892 1893 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1894 1895 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1896 if (unlikely(!ip_block)) { 1897 dev_err(adev->dev, "Failed to get MES handle\n"); 1898 return -EINVAL; 1899 } 1900 1901 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1902 if (r) 1903 goto failure; 1904 1905 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1906 adev->mes.enable_legacy_queue_map = true; 1907 else 1908 adev->mes.enable_legacy_queue_map = false; 1909 1910 if (adev->mes.enable_legacy_queue_map) { 1911 r = mes_v11_0_hw_init(ip_block); 1912 if (r) 1913 goto failure; 1914 } 1915 1916 return r; 1917 1918 failure: 1919 mes_v11_0_hw_fini(ip_block); 1920 return r; 1921 } 1922 1923 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1924 { 1925 if (adev->mes.ring[0].sched.ready) { 1926 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1927 adev->mes.ring[0].sched.ready = false; 1928 } 1929 1930 if (amdgpu_sriov_vf(adev)) { 1931 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1932 mes_v11_0_kiq_clear(adev); 1933 } 1934 1935 mes_v11_0_enable(adev, false); 1936 1937 return 0; 1938 } 1939 1940 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1941 { 1942 int r; 1943 struct amdgpu_device *adev = ip_block->adev; 1944 1945 if (adev->mes.ring[0].sched.ready) 1946 goto out; 1947 1948 if (!adev->enable_mes_kiq) { 1949 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1950 r = mes_v11_0_load_microcode(adev, 1951 AMDGPU_MES_SCHED_PIPE, true); 1952 if (r) { 1953 DRM_ERROR("failed to MES fw, r=%d\n", r); 1954 return r; 1955 } 1956 } 1957 1958 mes_v11_0_enable(adev, true); 1959 } 1960 1961 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1962 if (r) 1963 goto failure; 1964 1965 /* Allocate GPU buffer for array size query results */ 1966 r = amdgpu_mes_rs64mem_init(&adev->mes); 1967 if (r) 1968 dev_warn(adev->dev, 1969 "RS64 local memory init failed (%d)," 1970 "falling back to system memory path\n", r); 1971 1972 r = mes_v11_0_set_hw_resources(&adev->mes); 1973 1974 if (r) 1975 goto failure; 1976 1977 /* 1978 * QUERY_SCHEDULER_STATUS to get array sizes (N, M). 1979 * MES writes the sizes to the GPU buffer, then we allocate bitmaps. 1980 */ 1981 if (adev->mes.use_rs64mem) { 1982 r = mes_v11_0_query_ctx_array_sizes(&adev->mes); 1983 if (r) { 1984 dev_warn(adev->dev, 1985 "Failed to query ctx array sizes (%d)," 1986 "disabling RS64 local memory\n", r); 1987 /* Continue without optimization - not fatal */ 1988 } 1989 } 1990 1991 1992 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1993 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1994 if (r) { 1995 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1996 goto failure; 1997 } 1998 } 1999 2000 r = mes_v11_0_query_sched_status(&adev->mes); 2001 if (r) { 2002 DRM_ERROR("MES is busy\n"); 2003 goto failure; 2004 } 2005 2006 r = amdgpu_mes_update_enforce_isolation(adev); 2007 if (r) 2008 goto failure; 2009 2010 amdgpu_mes_validate_fw_version(adev); 2011 out: 2012 /* 2013 * Disable KIQ ring usage from the driver once MES is enabled. 2014 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 2015 * with MES enabled. 2016 */ 2017 adev->gfx.kiq[0].ring.sched.ready = false; 2018 adev->mes.ring[0].sched.ready = true; 2019 2020 return 0; 2021 2022 failure: 2023 mes_v11_0_hw_fini(ip_block); 2024 return r; 2025 } 2026 2027 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 2028 { 2029 struct amdgpu_device *adev = ip_block->adev; 2030 2031 if (adev->mes.use_rs64mem) 2032 amdgpu_mes_rs64mem_fini(&adev->mes); 2033 return 0; 2034 } 2035 2036 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 2037 { 2038 return mes_v11_0_hw_fini(ip_block); 2039 } 2040 2041 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 2042 { 2043 return mes_v11_0_hw_init(ip_block); 2044 } 2045 2046 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 2047 { 2048 struct amdgpu_device *adev = ip_block->adev; 2049 int pipe, r; 2050 2051 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 2052 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 2053 2054 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 2055 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 2056 continue; 2057 r = amdgpu_mes_init_microcode(adev, pipe); 2058 if (r) 2059 return r; 2060 } 2061 2062 return 0; 2063 } 2064 2065 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 2066 .name = "mes_v11_0", 2067 .early_init = mes_v11_0_early_init, 2068 .late_init = NULL, 2069 .sw_init = mes_v11_0_sw_init, 2070 .sw_fini = mes_v11_0_sw_fini, 2071 .hw_init = mes_v11_0_hw_init, 2072 .hw_fini = mes_v11_0_hw_fini, 2073 .suspend = mes_v11_0_suspend, 2074 .resume = mes_v11_0_resume, 2075 }; 2076 2077 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 2078 .type = AMD_IP_BLOCK_TYPE_MES, 2079 .major = 11, 2080 .minor = 0, 2081 .rev = 0, 2082 .funcs = &mes_v11_0_ip_funcs, 2083 }; 2084