1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin"); 67 68 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 69 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 72 73 #define MES_EOP_SIZE 2048 74 #define GFX_MES_DRAM_SIZE 0x80000 75 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 76 77 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 78 #define MES11_HUNG_HQD_INFO_OFFSET 4 79 80 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 81 { 82 struct amdgpu_device *adev = ring->adev; 83 84 if (ring->use_doorbell) { 85 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 86 ring->wptr); 87 WDOORBELL64(ring->doorbell_index, ring->wptr); 88 } else { 89 BUG(); 90 } 91 } 92 93 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 94 { 95 return *ring->rptr_cpu_addr; 96 } 97 98 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 99 { 100 u64 wptr; 101 102 if (ring->use_doorbell) 103 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 104 else 105 BUG(); 106 return wptr; 107 } 108 109 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 110 .type = AMDGPU_RING_TYPE_MES, 111 .align_mask = 1, 112 .nop = 0, 113 .support_64bit_ptrs = true, 114 .get_rptr = mes_v11_0_ring_get_rptr, 115 .get_wptr = mes_v11_0_ring_get_wptr, 116 .set_wptr = mes_v11_0_ring_set_wptr, 117 .insert_nop = amdgpu_ring_insert_nop, 118 }; 119 120 static const char *mes_v11_0_opcodes[] = { 121 "SET_HW_RSRC", 122 "SET_SCHEDULING_CONFIG", 123 "ADD_QUEUE", 124 "REMOVE_QUEUE", 125 "PERFORM_YIELD", 126 "SET_GANG_PRIORITY_LEVEL", 127 "SUSPEND", 128 "RESUME", 129 "RESET", 130 "SET_LOG_BUFFER", 131 "CHANGE_GANG_PRORITY", 132 "QUERY_SCHEDULER_STATUS", 133 "PROGRAM_GDS", 134 "SET_DEBUG_VMID", 135 "MISC", 136 "UPDATE_ROOT_PAGE_TABLE", 137 "AMD_LOG", 138 "unused", 139 "unused", 140 "SET_HW_RSRC_1", 141 }; 142 143 static const char *mes_v11_0_misc_opcodes[] = { 144 "WRITE_REG", 145 "INV_GART", 146 "QUERY_STATUS", 147 "READ_REG", 148 "WAIT_REG_MEM", 149 "SET_SHADER_DEBUGGER", 150 }; 151 152 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 153 { 154 const char *op_str = NULL; 155 156 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 157 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 158 159 return op_str; 160 } 161 162 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 163 { 164 const char *op_str = NULL; 165 166 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 167 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 168 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 169 170 return op_str; 171 } 172 173 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 174 void *pkt, int size, 175 int api_status_off) 176 { 177 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 178 signed long timeout = 2100000; /* 2100 ms */ 179 struct amdgpu_device *adev = mes->adev; 180 struct amdgpu_ring *ring = &mes->ring[0]; 181 struct MES_API_STATUS *api_status; 182 union MESAPI__MISC *x_pkt = pkt; 183 const char *op_str, *misc_op_str; 184 unsigned long flags; 185 u64 status_gpu_addr; 186 u32 seq, status_offset; 187 u64 *status_ptr; 188 signed long r; 189 int ret; 190 191 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 192 return -EINVAL; 193 194 if (amdgpu_emu_mode) { 195 timeout *= 100; 196 } else if (amdgpu_sriov_vf(adev)) { 197 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 198 timeout = 15 * 600 * 1000; 199 } 200 201 ret = amdgpu_wb_get(adev, &status_offset); 202 if (ret) 203 return ret; 204 205 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 206 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 207 *status_ptr = 0; 208 209 spin_lock_irqsave(&mes->ring_lock[0], flags); 210 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 211 if (r) 212 goto error_unlock_free; 213 214 seq = ++ring->fence_drv.sync_seq; 215 r = amdgpu_fence_wait_polling(ring, 216 seq - ring->fence_drv.num_fences_mask, 217 timeout); 218 if (r < 1) 219 goto error_undo; 220 221 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 222 api_status->api_completion_fence_addr = status_gpu_addr; 223 api_status->api_completion_fence_value = 1; 224 225 amdgpu_ring_write_multiple(ring, pkt, size / 4); 226 227 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 228 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 229 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 230 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 231 mes_status_pkt.api_status.api_completion_fence_addr = 232 ring->fence_drv.gpu_addr; 233 mes_status_pkt.api_status.api_completion_fence_value = seq; 234 235 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 236 sizeof(mes_status_pkt) / 4); 237 238 amdgpu_ring_commit(ring); 239 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 240 241 op_str = mes_v11_0_get_op_string(x_pkt); 242 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 243 244 if (misc_op_str) 245 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 246 misc_op_str); 247 else if (op_str) 248 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 249 else 250 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 251 x_pkt->header.opcode); 252 253 r = amdgpu_fence_wait_polling(ring, seq, timeout); 254 if (r < 1 || !*status_ptr) { 255 256 if (misc_op_str) 257 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 258 op_str, misc_op_str); 259 else if (op_str) 260 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 261 op_str); 262 else 263 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 264 x_pkt->header.opcode); 265 266 while (halt_if_hws_hang) 267 schedule(); 268 269 r = -ETIMEDOUT; 270 goto error_wb_free; 271 } 272 273 amdgpu_wb_free(adev, status_offset); 274 return 0; 275 276 error_undo: 277 dev_err(adev->dev, "MES ring buffer is full.\n"); 278 amdgpu_ring_undo(ring); 279 280 error_unlock_free: 281 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 282 283 error_wb_free: 284 amdgpu_wb_free(adev, status_offset); 285 return r; 286 } 287 288 static int convert_to_mes_queue_type(int queue_type) 289 { 290 if (queue_type == AMDGPU_RING_TYPE_GFX) 291 return MES_QUEUE_TYPE_GFX; 292 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 293 return MES_QUEUE_TYPE_COMPUTE; 294 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 295 return MES_QUEUE_TYPE_SDMA; 296 else 297 BUG(); 298 return -1; 299 } 300 301 static int convert_to_mes_priority_level(int priority_level) 302 { 303 switch (priority_level) { 304 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 305 return AMD_PRIORITY_LEVEL_LOW; 306 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 307 default: 308 return AMD_PRIORITY_LEVEL_NORMAL; 309 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 310 return AMD_PRIORITY_LEVEL_MEDIUM; 311 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 312 return AMD_PRIORITY_LEVEL_HIGH; 313 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 314 return AMD_PRIORITY_LEVEL_REALTIME; 315 } 316 } 317 318 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 319 struct mes_add_queue_input *input) 320 { 321 struct amdgpu_device *adev = mes->adev; 322 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 323 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 324 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 325 326 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 327 328 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 329 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 330 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 331 332 mes_add_queue_pkt.process_id = input->process_id; 333 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 334 mes_add_queue_pkt.process_va_start = input->process_va_start; 335 mes_add_queue_pkt.process_va_end = input->process_va_end; 336 mes_add_queue_pkt.process_quantum = input->process_quantum; 337 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 338 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 339 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 340 mes_add_queue_pkt.inprocess_gang_priority = 341 convert_to_mes_priority_level(input->inprocess_gang_priority); 342 mes_add_queue_pkt.gang_global_priority_level = 343 convert_to_mes_priority_level(input->gang_global_priority_level); 344 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 345 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 346 347 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 348 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 349 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 350 else 351 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 352 353 mes_add_queue_pkt.queue_type = 354 convert_to_mes_queue_type(input->queue_type); 355 mes_add_queue_pkt.paging = input->paging; 356 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 357 mes_add_queue_pkt.gws_base = input->gws_base; 358 mes_add_queue_pkt.gws_size = input->gws_size; 359 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 360 mes_add_queue_pkt.tma_addr = input->tma_addr; 361 mes_add_queue_pkt.trap_en = input->trap_en; 362 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 363 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 364 365 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 366 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 367 mes_add_queue_pkt.gds_size = input->queue_size; 368 369 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 370 371 return mes_v11_0_submit_pkt_and_poll_completion(mes, 372 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 373 offsetof(union MESAPI__ADD_QUEUE, api_status)); 374 } 375 376 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 377 struct mes_remove_queue_input *input) 378 { 379 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 380 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 381 382 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 383 384 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 385 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 386 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 387 388 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 389 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 390 mes_remove_queue_pkt.queue_type = 391 convert_to_mes_queue_type(input->queue_type); 392 393 if (mes_rev >= 0x60) 394 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 395 396 return mes_v11_0_submit_pkt_and_poll_completion(mes, 397 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 398 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 399 } 400 401 static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev) 402 { 403 /* Disable the pipe reset until the CPFW fully support it.*/ 404 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 405 return false; 406 } 407 static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 408 u32 me, u32 pipe, u32 queue) 409 { 410 uint32_t reset_pipe = 0, clean_pipe = 0; 411 int r; 412 413 if (!mes_v11_0_pipe_reset_support(adev)) 414 return -EOPNOTSUPP; 415 416 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 417 mutex_lock(&adev->srbm_mutex); 418 soc21_grbm_select(adev, me, pipe, queue, 0); 419 420 switch (pipe) { 421 case 0: 422 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 423 PFP_PIPE0_RESET, 1); 424 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 425 ME_PIPE0_RESET, 1); 426 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 427 PFP_PIPE0_RESET, 0); 428 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 429 ME_PIPE0_RESET, 0); 430 break; 431 case 1: 432 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 433 PFP_PIPE1_RESET, 1); 434 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 435 ME_PIPE1_RESET, 1); 436 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 437 PFP_PIPE1_RESET, 0); 438 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 439 ME_PIPE1_RESET, 0); 440 break; 441 default: 442 break; 443 } 444 445 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 446 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 447 448 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 449 RS64_FW_UC_START_ADDR_LO; 450 soc21_grbm_select(adev, 0, 0, 0, 0); 451 mutex_unlock(&adev->srbm_mutex); 452 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 453 454 dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n", 455 r == 0 ? "successfully" : "failed"); 456 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 457 * so the pipe reset status relies on the later gfx ring test result. 458 */ 459 return 0; 460 } 461 462 /* 463 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 464 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 465 * asserted; only then clear the pipe reset bit. 466 * Caller must hold adev->srbm_mutex. 467 */ 468 static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 469 u32 pipe) 470 { 471 unsigned int q; 472 473 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 474 soc21_grbm_select(adev, me, pipe, q, 0); 475 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 476 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 477 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 478 } 479 } 480 481 static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 482 u32 me, u32 pipe, u32 queue) 483 { 484 uint32_t reset_val, clean_val; 485 int r; 486 487 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 488 mutex_lock(&adev->srbm_mutex); 489 soc21_grbm_select(adev, me, pipe, queue, 0); 490 491 if (adev->gfx.rs64_enable) { 492 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 493 clean_val = reset_val; 494 495 switch (pipe) { 496 case 0: 497 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 498 MEC_PIPE0_RESET, 1); 499 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 500 MEC_PIPE0_RESET, 0); 501 break; 502 case 1: 503 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 504 MEC_PIPE1_RESET, 1); 505 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 506 MEC_PIPE1_RESET, 0); 507 break; 508 case 2: 509 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 510 MEC_PIPE2_RESET, 1); 511 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 512 MEC_PIPE2_RESET, 0); 513 break; 514 case 3: 515 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 516 MEC_PIPE3_RESET, 1); 517 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 518 MEC_PIPE3_RESET, 0); 519 break; 520 default: 521 break; 522 } 523 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 524 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 525 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 526 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 527 RS64_FW_UC_START_ADDR_LO; 528 } else { 529 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 530 clean_val = reset_val; 531 532 if (me == 1) { 533 switch (pipe) { 534 case 0: 535 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 536 MEC_ME1_PIPE0_RESET, 1); 537 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 538 MEC_ME1_PIPE0_RESET, 0); 539 break; 540 case 1: 541 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 542 MEC_ME1_PIPE1_RESET, 1); 543 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 544 MEC_ME1_PIPE1_RESET, 0); 545 break; 546 case 2: 547 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 548 MEC_ME1_PIPE2_RESET, 1); 549 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 550 MEC_ME1_PIPE2_RESET, 0); 551 break; 552 case 3: 553 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 554 MEC_ME1_PIPE3_RESET, 1); 555 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 556 MEC_ME1_PIPE3_RESET, 0); 557 break; 558 default: 559 break; 560 } 561 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 562 } else { 563 switch (pipe) { 564 case 0: 565 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 566 MEC_ME2_PIPE0_RESET, 1); 567 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 568 MEC_ME2_PIPE0_RESET, 0); 569 break; 570 case 1: 571 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 572 MEC_ME2_PIPE1_RESET, 1); 573 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 574 MEC_ME2_PIPE1_RESET, 0); 575 break; 576 case 2: 577 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 578 MEC_ME2_PIPE2_RESET, 1); 579 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 580 MEC_ME2_PIPE2_RESET, 0); 581 break; 582 case 3: 583 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 584 MEC_ME2_PIPE3_RESET, 1); 585 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 586 MEC_ME2_PIPE3_RESET, 0); 587 break; 588 default: 589 break; 590 } 591 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 592 } 593 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 594 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 595 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 596 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 597 } 598 599 soc21_grbm_select(adev, 0, 0, 0, 0); 600 mutex_unlock(&adev->srbm_mutex); 601 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 602 603 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 604 me, pipe, queue, r == 0 ? "successfully" : "failed"); 605 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 606 * reset status relies on the compute ring test result. 607 */ 608 return 0; 609 } 610 611 static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 612 uint32_t me_id, uint32_t pipe_id, 613 uint32_t queue_id, uint32_t vmid) 614 { 615 struct amdgpu_device *adev = mes->adev; 616 617 if (queue_type == AMDGPU_RING_TYPE_GFX) 618 return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 619 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 620 return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 621 else 622 return -EOPNOTSUPP; 623 } 624 625 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 626 uint32_t me_id, uint32_t pipe_id, 627 uint32_t queue_id, uint32_t vmid) 628 { 629 struct amdgpu_device *adev = mes->adev; 630 uint32_t value, reg; 631 int i, r = 0; 632 633 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 634 635 if (queue_type == AMDGPU_RING_TYPE_GFX) { 636 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 637 me_id, pipe_id, queue_id, vmid); 638 639 mutex_lock(&adev->gfx.reset_sem_mutex); 640 gfx_v11_0_request_gfx_index_mutex(adev, true); 641 /* all se allow writes */ 642 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 643 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 644 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 645 if (pipe_id == 0) 646 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 647 else 648 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 649 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 650 gfx_v11_0_request_gfx_index_mutex(adev, false); 651 mutex_unlock(&adev->gfx.reset_sem_mutex); 652 653 mutex_lock(&adev->srbm_mutex); 654 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 655 /* wait till dequeue take effects */ 656 for (i = 0; i < adev->usec_timeout; i++) { 657 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 658 break; 659 udelay(1); 660 } 661 if (i >= adev->usec_timeout) { 662 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 663 r = -ETIMEDOUT; 664 } 665 666 soc21_grbm_select(adev, 0, 0, 0, 0); 667 mutex_unlock(&adev->srbm_mutex); 668 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 669 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 670 me_id, pipe_id, queue_id); 671 mutex_lock(&adev->srbm_mutex); 672 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 673 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 674 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 675 676 /* wait till dequeue take effects */ 677 for (i = 0; i < adev->usec_timeout; i++) { 678 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 679 break; 680 udelay(1); 681 } 682 if (i >= adev->usec_timeout) { 683 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 684 r = -ETIMEDOUT; 685 } 686 soc21_grbm_select(adev, 0, 0, 0, 0); 687 mutex_unlock(&adev->srbm_mutex); 688 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 689 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 690 me_id, pipe_id, queue_id); 691 switch (me_id) { 692 case 1: 693 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 694 break; 695 case 0: 696 default: 697 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 698 break; 699 } 700 701 value = 1 << queue_id; 702 WREG32(reg, value); 703 /* wait for queue reset done */ 704 for (i = 0; i < adev->usec_timeout; i++) { 705 if (!(RREG32(reg) & value)) 706 break; 707 udelay(1); 708 } 709 if (i >= adev->usec_timeout) { 710 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 711 r = -ETIMEDOUT; 712 } 713 } 714 715 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 716 return r; 717 } 718 719 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 720 struct mes_map_legacy_queue_input *input) 721 { 722 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 723 724 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 725 726 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 727 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 728 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 729 730 mes_add_queue_pkt.pipe_id = input->pipe_id; 731 mes_add_queue_pkt.queue_id = input->queue_id; 732 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 733 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 734 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 735 mes_add_queue_pkt.queue_type = 736 convert_to_mes_queue_type(input->queue_type); 737 mes_add_queue_pkt.map_legacy_kq = 1; 738 739 return mes_v11_0_submit_pkt_and_poll_completion(mes, 740 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 741 offsetof(union MESAPI__ADD_QUEUE, api_status)); 742 } 743 744 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 745 struct mes_unmap_legacy_queue_input *input) 746 { 747 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 748 749 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 750 751 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 752 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 753 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 754 755 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 756 mes_remove_queue_pkt.gang_context_addr = 0; 757 758 mes_remove_queue_pkt.pipe_id = input->pipe_id; 759 mes_remove_queue_pkt.queue_id = input->queue_id; 760 761 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 762 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 763 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 764 mes_remove_queue_pkt.tf_data = 765 lower_32_bits(input->trail_fence_data); 766 } else { 767 mes_remove_queue_pkt.unmap_legacy_queue = 1; 768 mes_remove_queue_pkt.queue_type = 769 convert_to_mes_queue_type(input->queue_type); 770 } 771 772 return mes_v11_0_submit_pkt_and_poll_completion(mes, 773 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 774 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 775 } 776 777 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 778 struct mes_suspend_gang_input *input) 779 { 780 union MESAPI__SUSPEND mes_suspend_gang_pkt; 781 782 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 783 784 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 785 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 786 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 787 788 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 789 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 790 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 791 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 792 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 793 794 return mes_v11_0_submit_pkt_and_poll_completion(mes, 795 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 796 offsetof(union MESAPI__SUSPEND, api_status)); 797 } 798 799 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 800 struct mes_resume_gang_input *input) 801 { 802 union MESAPI__RESUME mes_resume_gang_pkt; 803 804 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 805 806 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 807 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 808 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 809 810 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 811 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 812 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 813 814 return mes_v11_0_submit_pkt_and_poll_completion(mes, 815 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 816 offsetof(union MESAPI__RESUME, api_status)); 817 } 818 819 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 820 { 821 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 822 823 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 824 825 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 826 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 827 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 828 829 return mes_v11_0_submit_pkt_and_poll_completion(mes, 830 &mes_status_pkt, sizeof(mes_status_pkt), 831 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 832 } 833 834 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 835 struct mes_misc_op_input *input) 836 { 837 union MESAPI__MISC misc_pkt; 838 839 memset(&misc_pkt, 0, sizeof(misc_pkt)); 840 841 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 842 misc_pkt.header.opcode = MES_SCH_API_MISC; 843 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 844 845 switch (input->op) { 846 case MES_MISC_OP_READ_REG: 847 misc_pkt.opcode = MESAPI_MISC__READ_REG; 848 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 849 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 850 break; 851 case MES_MISC_OP_WRITE_REG: 852 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 853 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 854 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 855 break; 856 case MES_MISC_OP_WRM_REG_WAIT: 857 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 858 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 859 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 860 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 861 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 862 misc_pkt.wait_reg_mem.reg_offset2 = 0; 863 break; 864 case MES_MISC_OP_WRM_REG_WR_WAIT: 865 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 866 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 867 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 868 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 869 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 870 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 871 break; 872 case MES_MISC_OP_SET_SHADER_DEBUGGER: 873 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 874 misc_pkt.set_shader_debugger.process_context_addr = 875 input->set_shader_debugger.process_context_addr; 876 misc_pkt.set_shader_debugger.flags.u32all = 877 input->set_shader_debugger.flags.u32all; 878 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 879 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 880 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 881 input->set_shader_debugger.tcp_watch_cntl, 882 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 883 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 884 break; 885 case MES_MISC_OP_CHANGE_CONFIG: 886 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 887 dev_warn_once(mes->adev->dev, 888 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 889 return 0; 890 } 891 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 892 misc_pkt.change_config.opcode = 893 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 894 misc_pkt.change_config.option.bits.limit_single_process = 895 input->change_config.option.limit_single_process; 896 break; 897 898 default: 899 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 900 return -EINVAL; 901 } 902 903 return mes_v11_0_submit_pkt_and_poll_completion(mes, 904 &misc_pkt, sizeof(misc_pkt), 905 offsetof(union MESAPI__MISC, api_status)); 906 } 907 908 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 909 { 910 int i; 911 struct amdgpu_device *adev = mes->adev; 912 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 913 914 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 915 916 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 917 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 918 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 919 920 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 921 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 922 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 923 mes_set_hw_res_pkt.paging_vmid = 0; 924 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 925 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 926 mes->query_status_fence_gpu_addr[0]; 927 928 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 929 mes_set_hw_res_pkt.compute_hqd_mask[i] = 930 mes->compute_hqd_mask[i]; 931 932 for (i = 0; i < MAX_GFX_PIPES; i++) 933 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 934 mes->gfx_hqd_mask[i]; 935 936 for (i = 0; i < MAX_SDMA_PIPES; i++) 937 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 938 939 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 940 mes_set_hw_res_pkt.aggregated_doorbells[i] = 941 mes->aggregated_doorbells[i]; 942 943 for (i = 0; i < 5; i++) { 944 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 945 mes_set_hw_res_pkt.mmhub_base[i] = 946 adev->reg_offset[MMHUB_HWIP][0][i]; 947 mes_set_hw_res_pkt.osssys_base[i] = 948 adev->reg_offset[OSSSYS_HWIP][0][i]; 949 } 950 951 mes_set_hw_res_pkt.disable_reset = 1; 952 mes_set_hw_res_pkt.disable_mes_log = 1; 953 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 954 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 955 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 956 mes_set_hw_res_pkt.oversubscription_timer = 50; 957 958 if (amdgpu_mes_log_enable) { 959 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 960 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 961 mes->event_log_gpu_addr; 962 } 963 964 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 965 mes_set_hw_res_pkt.limit_single_process = 1; 966 967 return mes_v11_0_submit_pkt_and_poll_completion(mes, 968 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 969 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 970 } 971 972 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 973 { 974 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 975 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 976 977 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 978 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 979 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 980 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 981 982 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 983 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 984 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 985 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 986 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 987 } 988 989 return mes_v11_0_submit_pkt_and_poll_completion(mes, 990 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 991 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 992 } 993 994 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 995 struct mes_reset_queue_input *input) 996 { 997 union MESAPI__RESET mes_reset_queue_pkt; 998 999 if (input->use_mmio) { 1000 int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type, 1001 input->me_id, input->pipe_id, 1002 input->queue_id, input->vmid); 1003 if (r) 1004 return mes_v11_0_reset_pipe_mmio(mes, input->queue_type, 1005 input->me_id, input->pipe_id, 1006 input->queue_id, input->vmid); 1007 return 0; 1008 } 1009 1010 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1011 1012 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1013 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1014 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1015 1016 mes_reset_queue_pkt.queue_type = 1017 convert_to_mes_queue_type(input->queue_type); 1018 1019 if (input->legacy_gfx) { 1020 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1021 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1022 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1023 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1024 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1025 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1026 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1027 } else { 1028 mes_reset_queue_pkt.reset_queue_only = 1; 1029 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1030 } 1031 1032 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1033 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1034 offsetof(union MESAPI__RESET, api_status)); 1035 } 1036 1037 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1038 struct mes_detect_and_reset_queue_input *input) 1039 { 1040 union MESAPI__RESET mes_reset_queue_pkt; 1041 1042 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1043 1044 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1045 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1046 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1047 1048 mes_reset_queue_pkt.queue_type = 1049 convert_to_mes_queue_type(input->queue_type); 1050 mes_reset_queue_pkt.doorbell_offset_addr = 1051 mes->hung_queue_db_array_gpu_addr[0]; 1052 1053 if (input->detect_only) 1054 mes_reset_queue_pkt.hang_detect_only = 1; 1055 else 1056 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1057 1058 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1059 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1060 offsetof(union MESAPI__RESET, api_status)); 1061 } 1062 1063 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 1064 .add_hw_queue = mes_v11_0_add_hw_queue, 1065 .remove_hw_queue = mes_v11_0_remove_hw_queue, 1066 .map_legacy_queue = mes_v11_0_map_legacy_queue, 1067 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 1068 .suspend_gang = mes_v11_0_suspend_gang, 1069 .resume_gang = mes_v11_0_resume_gang, 1070 .misc_op = mes_v11_0_misc_op, 1071 .reset_hw_queue = mes_v11_0_reset_hw_queue, 1072 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 1073 }; 1074 1075 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1076 enum amdgpu_mes_pipe pipe) 1077 { 1078 int r; 1079 const struct mes_firmware_header_v1_0 *mes_hdr; 1080 const __le32 *fw_data; 1081 unsigned fw_size; 1082 1083 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1084 adev->mes.fw[pipe]->data; 1085 1086 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1087 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1088 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1089 1090 r = amdgpu_bo_create_reserved(adev, fw_size, 1091 PAGE_SIZE, 1092 AMDGPU_GEM_DOMAIN_VRAM | 1093 AMDGPU_GEM_DOMAIN_GTT, 1094 &adev->mes.ucode_fw_obj[pipe], 1095 &adev->mes.ucode_fw_gpu_addr[pipe], 1096 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1097 if (r) { 1098 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1099 return r; 1100 } 1101 1102 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1103 1104 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1105 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1106 1107 return 0; 1108 } 1109 1110 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1111 enum amdgpu_mes_pipe pipe) 1112 { 1113 int r; 1114 const struct mes_firmware_header_v1_0 *mes_hdr; 1115 const __le32 *fw_data; 1116 unsigned fw_size; 1117 1118 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1119 adev->mes.fw[pipe]->data; 1120 1121 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1122 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1123 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1124 1125 if (fw_size > GFX_MES_DRAM_SIZE) { 1126 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 1127 pipe, fw_size, GFX_MES_DRAM_SIZE); 1128 return -EINVAL; 1129 } 1130 1131 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 1132 64 * 1024, 1133 AMDGPU_GEM_DOMAIN_VRAM | 1134 AMDGPU_GEM_DOMAIN_GTT, 1135 &adev->mes.data_fw_obj[pipe], 1136 &adev->mes.data_fw_gpu_addr[pipe], 1137 (void **)&adev->mes.data_fw_ptr[pipe]); 1138 if (r) { 1139 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1140 return r; 1141 } 1142 1143 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1144 1145 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1146 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1147 1148 return 0; 1149 } 1150 1151 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 1152 enum amdgpu_mes_pipe pipe) 1153 { 1154 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1155 &adev->mes.data_fw_gpu_addr[pipe], 1156 (void **)&adev->mes.data_fw_ptr[pipe]); 1157 1158 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1159 &adev->mes.ucode_fw_gpu_addr[pipe], 1160 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1161 } 1162 1163 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 1164 { 1165 int pipe; 1166 1167 /* return early if we have already fetched these */ 1168 if (adev->mes.sched_version && adev->mes.kiq_version) 1169 return; 1170 1171 /* get MES scheduler/KIQ versions */ 1172 mutex_lock(&adev->srbm_mutex); 1173 1174 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1175 soc21_grbm_select(adev, 3, pipe, 0, 0); 1176 1177 if (pipe == AMDGPU_MES_SCHED_PIPE) 1178 adev->mes.sched_version = 1179 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1180 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1181 adev->mes.kiq_version = 1182 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1183 } 1184 1185 soc21_grbm_select(adev, 0, 0, 0, 0); 1186 mutex_unlock(&adev->srbm_mutex); 1187 } 1188 1189 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 1190 { 1191 uint64_t ucode_addr; 1192 uint32_t pipe, data = 0; 1193 1194 if (enable) { 1195 if (amdgpu_mes_log_enable) { 1196 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1197 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1198 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1199 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1200 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1201 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1202 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1203 } 1204 1205 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1206 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1207 data = REG_SET_FIELD(data, CP_MES_CNTL, 1208 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 1209 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1210 1211 mutex_lock(&adev->srbm_mutex); 1212 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1213 if (!adev->enable_mes_kiq && 1214 pipe == AMDGPU_MES_KIQ_PIPE) 1215 continue; 1216 1217 soc21_grbm_select(adev, 3, pipe, 0, 0); 1218 1219 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1220 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1221 lower_32_bits(ucode_addr)); 1222 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1223 upper_32_bits(ucode_addr)); 1224 } 1225 soc21_grbm_select(adev, 0, 0, 0, 0); 1226 mutex_unlock(&adev->srbm_mutex); 1227 1228 /* unhalt MES and activate pipe0 */ 1229 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1230 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1231 adev->enable_mes_kiq ? 1 : 0); 1232 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1233 1234 if (amdgpu_emu_mode) 1235 msleep(100); 1236 else 1237 udelay(500); 1238 } else { 1239 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1240 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1241 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1242 data = REG_SET_FIELD(data, CP_MES_CNTL, 1243 MES_INVALIDATE_ICACHE, 1); 1244 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1245 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1246 adev->enable_mes_kiq ? 1 : 0); 1247 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1248 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1249 } 1250 } 1251 1252 /* This function is for backdoor MES firmware */ 1253 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1254 enum amdgpu_mes_pipe pipe, bool prime_icache) 1255 { 1256 int r; 1257 uint32_t data; 1258 uint64_t ucode_addr; 1259 1260 mes_v11_0_enable(adev, false); 1261 1262 if (!adev->mes.fw[pipe]) 1263 return -EINVAL; 1264 1265 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1266 if (r) 1267 return r; 1268 1269 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1270 if (r) { 1271 mes_v11_0_free_ucode_buffers(adev, pipe); 1272 return r; 1273 } 1274 1275 mutex_lock(&adev->srbm_mutex); 1276 /* me=3, pipe=0, queue=0 */ 1277 soc21_grbm_select(adev, 3, pipe, 0, 0); 1278 1279 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1280 1281 /* set ucode start address */ 1282 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1283 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1284 lower_32_bits(ucode_addr)); 1285 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1286 upper_32_bits(ucode_addr)); 1287 1288 /* set ucode fimrware address */ 1289 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1290 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1291 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1292 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1293 1294 /* set ucode instruction cache boundary to 2M-1 */ 1295 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1296 1297 /* set ucode data firmware address */ 1298 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1299 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1300 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1301 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1302 1303 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1304 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1305 1306 if (prime_icache) { 1307 /* invalidate ICACHE */ 1308 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1309 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1310 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1311 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1312 1313 /* prime the ICACHE. */ 1314 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1315 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1316 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1317 } 1318 1319 soc21_grbm_select(adev, 0, 0, 0, 0); 1320 mutex_unlock(&adev->srbm_mutex); 1321 1322 return 0; 1323 } 1324 1325 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1326 enum amdgpu_mes_pipe pipe) 1327 { 1328 int r; 1329 u32 *eop; 1330 1331 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1332 AMDGPU_GEM_DOMAIN_GTT, 1333 &adev->mes.eop_gpu_obj[pipe], 1334 &adev->mes.eop_gpu_addr[pipe], 1335 (void **)&eop); 1336 if (r) { 1337 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1338 return r; 1339 } 1340 1341 memset(eop, 0, 1342 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1343 1344 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1345 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1346 1347 return 0; 1348 } 1349 1350 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1351 { 1352 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1353 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1354 uint32_t tmp; 1355 1356 memset(mqd, 0, sizeof(*mqd)); 1357 1358 mqd->header = 0xC0310800; 1359 mqd->compute_pipelinestat_enable = 0x00000001; 1360 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1361 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1362 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1363 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1364 mqd->compute_misc_reserved = 0x00000007; 1365 1366 eop_base_addr = ring->eop_gpu_addr >> 8; 1367 1368 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1369 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1370 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1371 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1372 1373 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1374 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1375 mqd->cp_hqd_eop_control = tmp; 1376 1377 /* disable the queue if it's active */ 1378 ring->wptr = 0; 1379 mqd->cp_hqd_pq_rptr = 0; 1380 mqd->cp_hqd_pq_wptr_lo = 0; 1381 mqd->cp_hqd_pq_wptr_hi = 0; 1382 1383 /* set the pointer to the MQD */ 1384 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1385 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1386 1387 /* set MQD vmid to 0 */ 1388 tmp = regCP_MQD_CONTROL_DEFAULT; 1389 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1390 mqd->cp_mqd_control = tmp; 1391 1392 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1393 hqd_gpu_addr = ring->gpu_addr >> 8; 1394 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1395 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1396 1397 /* set the wb address whether it's enabled or not */ 1398 wb_gpu_addr = ring->rptr_gpu_addr; 1399 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1400 mqd->cp_hqd_pq_rptr_report_addr_hi = 1401 upper_32_bits(wb_gpu_addr) & 0xffff; 1402 1403 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1404 wb_gpu_addr = ring->wptr_gpu_addr; 1405 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1406 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1407 1408 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1409 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1410 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1411 (order_base_2(ring->ring_size / 4) - 1)); 1412 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1413 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1414 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1415 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1416 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1417 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1418 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1419 mqd->cp_hqd_pq_control = tmp; 1420 1421 /* enable doorbell */ 1422 tmp = 0; 1423 if (ring->use_doorbell) { 1424 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1425 DOORBELL_OFFSET, ring->doorbell_index); 1426 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1427 DOORBELL_EN, 1); 1428 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1429 DOORBELL_SOURCE, 0); 1430 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1431 DOORBELL_HIT, 0); 1432 } else 1433 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1434 DOORBELL_EN, 0); 1435 mqd->cp_hqd_pq_doorbell_control = tmp; 1436 1437 mqd->cp_hqd_vmid = 0; 1438 /* activate the queue */ 1439 mqd->cp_hqd_active = 1; 1440 1441 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1442 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1443 PRELOAD_SIZE, 0x55); 1444 mqd->cp_hqd_persistent_state = tmp; 1445 1446 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1447 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1448 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1449 1450 amdgpu_device_flush_hdp(ring->adev, NULL); 1451 return 0; 1452 } 1453 1454 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1455 { 1456 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1457 struct amdgpu_device *adev = ring->adev; 1458 uint32_t data = 0; 1459 1460 mutex_lock(&adev->srbm_mutex); 1461 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1462 1463 /* set CP_HQD_VMID.VMID = 0. */ 1464 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1465 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1466 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1467 1468 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1469 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1470 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1471 DOORBELL_EN, 0); 1472 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1473 1474 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1475 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1476 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1477 1478 /* set CP_MQD_CONTROL.VMID=0 */ 1479 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1480 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1481 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1482 1483 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1484 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1485 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1486 1487 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1488 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1489 mqd->cp_hqd_pq_rptr_report_addr_lo); 1490 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1491 mqd->cp_hqd_pq_rptr_report_addr_hi); 1492 1493 /* set CP_HQD_PQ_CONTROL */ 1494 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1495 1496 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1497 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1498 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1499 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1500 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1501 1502 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1503 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1504 mqd->cp_hqd_pq_doorbell_control); 1505 1506 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1507 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1508 1509 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1510 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1511 1512 soc21_grbm_select(adev, 0, 0, 0, 0); 1513 mutex_unlock(&adev->srbm_mutex); 1514 } 1515 1516 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1517 { 1518 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1519 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1520 int r; 1521 1522 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1523 return -EINVAL; 1524 1525 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1526 if (r) { 1527 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1528 return r; 1529 } 1530 1531 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1532 1533 return amdgpu_ring_test_helper(kiq_ring); 1534 } 1535 1536 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1537 enum amdgpu_mes_pipe pipe) 1538 { 1539 struct amdgpu_ring *ring; 1540 int r; 1541 1542 if (pipe == AMDGPU_MES_KIQ_PIPE) 1543 ring = &adev->gfx.kiq[0].ring; 1544 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1545 ring = &adev->mes.ring[0]; 1546 else 1547 BUG(); 1548 1549 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1550 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1551 *(ring->wptr_cpu_addr) = 0; 1552 *(ring->rptr_cpu_addr) = 0; 1553 amdgpu_ring_clear_ring(ring); 1554 } 1555 1556 r = mes_v11_0_mqd_init(ring); 1557 if (r) 1558 return r; 1559 1560 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1561 r = mes_v11_0_kiq_enable_queue(adev); 1562 if (r) 1563 return r; 1564 } else { 1565 mes_v11_0_queue_init_register(ring); 1566 } 1567 1568 return 0; 1569 } 1570 1571 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1572 { 1573 struct amdgpu_ring *ring; 1574 1575 ring = &adev->mes.ring[0]; 1576 1577 ring->funcs = &mes_v11_0_ring_funcs; 1578 1579 ring->me = 3; 1580 ring->pipe = 0; 1581 ring->queue = 0; 1582 1583 ring->ring_obj = NULL; 1584 ring->use_doorbell = true; 1585 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1586 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1587 ring->no_scheduler = true; 1588 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1589 1590 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1591 AMDGPU_RING_PRIO_DEFAULT, NULL); 1592 } 1593 1594 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1595 { 1596 struct amdgpu_ring *ring; 1597 1598 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1599 1600 ring = &adev->gfx.kiq[0].ring; 1601 1602 ring->me = 3; 1603 ring->pipe = 1; 1604 ring->queue = 0; 1605 1606 ring->adev = NULL; 1607 ring->ring_obj = NULL; 1608 ring->use_doorbell = true; 1609 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1610 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1611 ring->no_scheduler = true; 1612 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1613 ring->me, ring->pipe, ring->queue); 1614 1615 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1616 AMDGPU_RING_PRIO_DEFAULT, NULL); 1617 } 1618 1619 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1620 enum amdgpu_mes_pipe pipe) 1621 { 1622 int r, mqd_size = sizeof(struct v11_compute_mqd); 1623 struct amdgpu_ring *ring; 1624 1625 if (pipe == AMDGPU_MES_KIQ_PIPE) 1626 ring = &adev->gfx.kiq[0].ring; 1627 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1628 ring = &adev->mes.ring[0]; 1629 else 1630 BUG(); 1631 1632 if (ring->mqd_obj) 1633 return 0; 1634 1635 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1636 AMDGPU_GEM_DOMAIN_VRAM | 1637 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1638 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1639 if (r) { 1640 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1641 return r; 1642 } 1643 1644 memset(ring->mqd_ptr, 0, mqd_size); 1645 1646 /* prepare MQD backup */ 1647 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1648 if (!adev->mes.mqd_backup[pipe]) { 1649 dev_warn(adev->dev, 1650 "no memory to create MQD backup for ring %s\n", 1651 ring->name); 1652 return -ENOMEM; 1653 } 1654 1655 return 0; 1656 } 1657 1658 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1659 { 1660 struct amdgpu_device *adev = ip_block->adev; 1661 int pipe, r, bo_size; 1662 1663 adev->mes.funcs = &mes_v11_0_funcs; 1664 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1665 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1666 1667 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1668 1669 r = amdgpu_mes_init(adev); 1670 if (r) 1671 return r; 1672 1673 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1674 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1675 continue; 1676 1677 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1678 if (r) 1679 return r; 1680 1681 r = mes_v11_0_mqd_sw_init(adev, pipe); 1682 if (r) 1683 return r; 1684 } 1685 1686 if (adev->enable_mes_kiq) { 1687 r = mes_v11_0_kiq_ring_init(adev); 1688 if (r) 1689 return r; 1690 } 1691 1692 r = mes_v11_0_ring_init(adev); 1693 if (r) 1694 return r; 1695 1696 bo_size = AMDGPU_GPU_PAGE_SIZE; 1697 if (amdgpu_sriov_is_mes_info_enable(adev)) 1698 bo_size += MES11_HW_RESOURCE_1_SIZE; 1699 1700 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1701 r = amdgpu_bo_create_kernel(adev, 1702 bo_size, 1703 PAGE_SIZE, 1704 AMDGPU_GEM_DOMAIN_VRAM, 1705 &adev->mes.resource_1[0], 1706 &adev->mes.resource_1_gpu_addr[0], 1707 &adev->mes.resource_1_addr[0]); 1708 if (r) { 1709 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1710 return r; 1711 } 1712 1713 return 0; 1714 } 1715 1716 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1717 { 1718 struct amdgpu_device *adev = ip_block->adev; 1719 int pipe; 1720 1721 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1722 &adev->mes.resource_1_addr[0]); 1723 1724 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1725 kfree(adev->mes.mqd_backup[pipe]); 1726 1727 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1728 &adev->mes.eop_gpu_addr[pipe], 1729 NULL); 1730 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1731 } 1732 1733 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1734 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1735 &adev->gfx.kiq[0].ring.mqd_ptr); 1736 1737 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1738 &adev->mes.ring[0].mqd_gpu_addr, 1739 &adev->mes.ring[0].mqd_ptr); 1740 1741 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1742 amdgpu_ring_fini(&adev->mes.ring[0]); 1743 1744 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1745 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1746 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1747 } 1748 1749 amdgpu_mes_fini(adev); 1750 return 0; 1751 } 1752 1753 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1754 { 1755 uint32_t data; 1756 int i; 1757 struct amdgpu_device *adev = ring->adev; 1758 1759 mutex_lock(&adev->srbm_mutex); 1760 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1761 1762 /* disable the queue if it's active */ 1763 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1764 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1765 for (i = 0; i < adev->usec_timeout; i++) { 1766 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1767 break; 1768 udelay(1); 1769 } 1770 } 1771 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1772 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1773 DOORBELL_EN, 0); 1774 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1775 DOORBELL_HIT, 1); 1776 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1777 1778 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1779 1780 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1781 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1782 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1783 1784 soc21_grbm_select(adev, 0, 0, 0, 0); 1785 mutex_unlock(&adev->srbm_mutex); 1786 } 1787 1788 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1789 { 1790 uint32_t tmp; 1791 struct amdgpu_device *adev = ring->adev; 1792 1793 /* tell RLC which is KIQ queue */ 1794 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1795 tmp &= 0xffffff00; 1796 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1797 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1798 } 1799 1800 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1801 { 1802 uint32_t tmp; 1803 1804 /* tell RLC which is KIQ dequeue */ 1805 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1806 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1807 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1808 } 1809 1810 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1811 { 1812 int r = 0; 1813 struct amdgpu_ip_block *ip_block; 1814 1815 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1816 1817 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1818 if (r) { 1819 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1820 return r; 1821 } 1822 1823 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1824 if (r) { 1825 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1826 return r; 1827 } 1828 1829 } 1830 1831 mes_v11_0_enable(adev, true); 1832 1833 mes_v11_0_get_fw_version(adev); 1834 1835 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1836 1837 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1838 if (unlikely(!ip_block)) { 1839 dev_err(adev->dev, "Failed to get MES handle\n"); 1840 return -EINVAL; 1841 } 1842 1843 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1844 if (r) 1845 goto failure; 1846 1847 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1848 adev->mes.enable_legacy_queue_map = true; 1849 else 1850 adev->mes.enable_legacy_queue_map = false; 1851 1852 if (adev->mes.enable_legacy_queue_map) { 1853 r = mes_v11_0_hw_init(ip_block); 1854 if (r) 1855 goto failure; 1856 } 1857 1858 return r; 1859 1860 failure: 1861 mes_v11_0_hw_fini(ip_block); 1862 return r; 1863 } 1864 1865 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1866 { 1867 if (adev->mes.ring[0].sched.ready) { 1868 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1869 adev->mes.ring[0].sched.ready = false; 1870 } 1871 1872 if (amdgpu_sriov_vf(adev)) { 1873 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1874 mes_v11_0_kiq_clear(adev); 1875 } 1876 1877 mes_v11_0_enable(adev, false); 1878 1879 return 0; 1880 } 1881 1882 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1883 { 1884 int r; 1885 struct amdgpu_device *adev = ip_block->adev; 1886 1887 if (adev->mes.ring[0].sched.ready) 1888 goto out; 1889 1890 if (!adev->enable_mes_kiq) { 1891 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1892 r = mes_v11_0_load_microcode(adev, 1893 AMDGPU_MES_SCHED_PIPE, true); 1894 if (r) { 1895 DRM_ERROR("failed to MES fw, r=%d\n", r); 1896 return r; 1897 } 1898 } 1899 1900 mes_v11_0_enable(adev, true); 1901 } 1902 1903 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1904 if (r) 1905 goto failure; 1906 1907 r = mes_v11_0_set_hw_resources(&adev->mes); 1908 if (r) 1909 goto failure; 1910 1911 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1912 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1913 if (r) { 1914 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1915 goto failure; 1916 } 1917 } 1918 1919 r = mes_v11_0_query_sched_status(&adev->mes); 1920 if (r) { 1921 DRM_ERROR("MES is busy\n"); 1922 goto failure; 1923 } 1924 1925 r = amdgpu_mes_update_enforce_isolation(adev); 1926 if (r) 1927 goto failure; 1928 1929 amdgpu_mes_validate_fw_version(adev); 1930 out: 1931 /* 1932 * Disable KIQ ring usage from the driver once MES is enabled. 1933 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1934 * with MES enabled. 1935 */ 1936 adev->gfx.kiq[0].ring.sched.ready = false; 1937 adev->mes.ring[0].sched.ready = true; 1938 1939 return 0; 1940 1941 failure: 1942 mes_v11_0_hw_fini(ip_block); 1943 return r; 1944 } 1945 1946 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1947 { 1948 return 0; 1949 } 1950 1951 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1952 { 1953 return mes_v11_0_hw_fini(ip_block); 1954 } 1955 1956 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1957 { 1958 return mes_v11_0_hw_init(ip_block); 1959 } 1960 1961 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1962 { 1963 struct amdgpu_device *adev = ip_block->adev; 1964 int pipe, r; 1965 1966 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1967 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1968 1969 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1970 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1971 continue; 1972 r = amdgpu_mes_init_microcode(adev, pipe); 1973 if (r) 1974 return r; 1975 } 1976 1977 return 0; 1978 } 1979 1980 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1981 .name = "mes_v11_0", 1982 .early_init = mes_v11_0_early_init, 1983 .late_init = NULL, 1984 .sw_init = mes_v11_0_sw_init, 1985 .sw_fini = mes_v11_0_sw_fini, 1986 .hw_init = mes_v11_0_hw_init, 1987 .hw_fini = mes_v11_0_hw_fini, 1988 .suspend = mes_v11_0_suspend, 1989 .resume = mes_v11_0_resume, 1990 }; 1991 1992 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1993 .type = AMD_IP_BLOCK_TYPE_MES, 1994 .major = 11, 1995 .minor = 0, 1996 .rev = 0, 1997 .funcs = &mes_v11_0_ip_funcs, 1998 }; 1999