1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 64 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 65 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 66 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 67 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 68 69 #define MES_EOP_SIZE 2048 70 #define GFX_MES_DRAM_SIZE 0x80000 71 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 72 73 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 74 #define MES11_HUNG_HQD_INFO_OFFSET 4 75 76 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 77 { 78 struct amdgpu_device *adev = ring->adev; 79 80 if (ring->use_doorbell) { 81 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 82 ring->wptr); 83 WDOORBELL64(ring->doorbell_index, ring->wptr); 84 } else { 85 BUG(); 86 } 87 } 88 89 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 90 { 91 return *ring->rptr_cpu_addr; 92 } 93 94 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 95 { 96 u64 wptr; 97 98 if (ring->use_doorbell) 99 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 100 else 101 BUG(); 102 return wptr; 103 } 104 105 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 106 .type = AMDGPU_RING_TYPE_MES, 107 .align_mask = 1, 108 .nop = 0, 109 .support_64bit_ptrs = true, 110 .get_rptr = mes_v11_0_ring_get_rptr, 111 .get_wptr = mes_v11_0_ring_get_wptr, 112 .set_wptr = mes_v11_0_ring_set_wptr, 113 .insert_nop = amdgpu_ring_insert_nop, 114 }; 115 116 static const char *mes_v11_0_opcodes[] = { 117 "SET_HW_RSRC", 118 "SET_SCHEDULING_CONFIG", 119 "ADD_QUEUE", 120 "REMOVE_QUEUE", 121 "PERFORM_YIELD", 122 "SET_GANG_PRIORITY_LEVEL", 123 "SUSPEND", 124 "RESUME", 125 "RESET", 126 "SET_LOG_BUFFER", 127 "CHANGE_GANG_PRORITY", 128 "QUERY_SCHEDULER_STATUS", 129 "PROGRAM_GDS", 130 "SET_DEBUG_VMID", 131 "MISC", 132 "UPDATE_ROOT_PAGE_TABLE", 133 "AMD_LOG", 134 "unused", 135 "unused", 136 "SET_HW_RSRC_1", 137 }; 138 139 static const char *mes_v11_0_misc_opcodes[] = { 140 "WRITE_REG", 141 "INV_GART", 142 "QUERY_STATUS", 143 "READ_REG", 144 "WAIT_REG_MEM", 145 "SET_SHADER_DEBUGGER", 146 }; 147 148 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 149 { 150 const char *op_str = NULL; 151 152 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 153 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 154 155 return op_str; 156 } 157 158 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 159 { 160 const char *op_str = NULL; 161 162 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 163 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 164 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 165 166 return op_str; 167 } 168 169 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 170 void *pkt, int size, 171 int api_status_off) 172 { 173 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 174 signed long timeout = 2100000; /* 2100 ms */ 175 struct amdgpu_device *adev = mes->adev; 176 struct amdgpu_ring *ring = &mes->ring[0]; 177 struct MES_API_STATUS *api_status; 178 union MESAPI__MISC *x_pkt = pkt; 179 const char *op_str, *misc_op_str; 180 unsigned long flags; 181 u64 status_gpu_addr; 182 u32 seq, status_offset; 183 u64 *status_ptr; 184 signed long r; 185 int ret; 186 187 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 188 return -EINVAL; 189 190 if (amdgpu_emu_mode) { 191 timeout *= 100; 192 } else if (amdgpu_sriov_vf(adev)) { 193 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 194 timeout = 15 * 600 * 1000; 195 } 196 197 ret = amdgpu_device_wb_get(adev, &status_offset); 198 if (ret) 199 return ret; 200 201 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 202 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 203 *status_ptr = 0; 204 205 spin_lock_irqsave(&mes->ring_lock[0], flags); 206 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 207 if (r) 208 goto error_unlock_free; 209 210 seq = ++ring->fence_drv.sync_seq; 211 r = amdgpu_fence_wait_polling(ring, 212 seq - ring->fence_drv.num_fences_mask, 213 timeout); 214 if (r < 1) 215 goto error_undo; 216 217 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 218 api_status->api_completion_fence_addr = status_gpu_addr; 219 api_status->api_completion_fence_value = 1; 220 221 amdgpu_ring_write_multiple(ring, pkt, size / 4); 222 223 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 224 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 225 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 226 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 227 mes_status_pkt.api_status.api_completion_fence_addr = 228 ring->fence_drv.gpu_addr; 229 mes_status_pkt.api_status.api_completion_fence_value = seq; 230 231 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 232 sizeof(mes_status_pkt) / 4); 233 234 amdgpu_ring_commit(ring); 235 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 236 237 op_str = mes_v11_0_get_op_string(x_pkt); 238 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 239 240 if (misc_op_str) 241 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 242 misc_op_str); 243 else if (op_str) 244 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 245 else 246 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 247 x_pkt->header.opcode); 248 249 r = amdgpu_fence_wait_polling(ring, seq, timeout); 250 if (r < 1 || !*status_ptr) { 251 252 if (misc_op_str) 253 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 254 op_str, misc_op_str); 255 else if (op_str) 256 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 257 op_str); 258 else 259 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 260 x_pkt->header.opcode); 261 262 while (halt_if_hws_hang) 263 schedule(); 264 265 r = -ETIMEDOUT; 266 goto error_wb_free; 267 } 268 269 amdgpu_device_wb_free(adev, status_offset); 270 return 0; 271 272 error_undo: 273 dev_err(adev->dev, "MES ring buffer is full.\n"); 274 amdgpu_ring_undo(ring); 275 276 error_unlock_free: 277 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 278 279 error_wb_free: 280 amdgpu_device_wb_free(adev, status_offset); 281 return r; 282 } 283 284 static int convert_to_mes_queue_type(int queue_type) 285 { 286 if (queue_type == AMDGPU_RING_TYPE_GFX) 287 return MES_QUEUE_TYPE_GFX; 288 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 289 return MES_QUEUE_TYPE_COMPUTE; 290 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 291 return MES_QUEUE_TYPE_SDMA; 292 else 293 BUG(); 294 return -1; 295 } 296 297 static int convert_to_mes_priority_level(int priority_level) 298 { 299 switch (priority_level) { 300 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 301 return AMD_PRIORITY_LEVEL_LOW; 302 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 303 default: 304 return AMD_PRIORITY_LEVEL_NORMAL; 305 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 306 return AMD_PRIORITY_LEVEL_MEDIUM; 307 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 308 return AMD_PRIORITY_LEVEL_HIGH; 309 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 310 return AMD_PRIORITY_LEVEL_REALTIME; 311 } 312 } 313 314 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 315 struct mes_add_queue_input *input) 316 { 317 struct amdgpu_device *adev = mes->adev; 318 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 319 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 320 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 321 322 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 323 324 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 325 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 326 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 327 328 mes_add_queue_pkt.process_id = input->process_id; 329 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 330 mes_add_queue_pkt.process_va_start = input->process_va_start; 331 mes_add_queue_pkt.process_va_end = input->process_va_end; 332 mes_add_queue_pkt.process_quantum = input->process_quantum; 333 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 334 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 335 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 336 mes_add_queue_pkt.inprocess_gang_priority = 337 convert_to_mes_priority_level(input->inprocess_gang_priority); 338 mes_add_queue_pkt.gang_global_priority_level = 339 convert_to_mes_priority_level(input->gang_global_priority_level); 340 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 341 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 342 343 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 344 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 345 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 346 else 347 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 348 349 mes_add_queue_pkt.queue_type = 350 convert_to_mes_queue_type(input->queue_type); 351 mes_add_queue_pkt.paging = input->paging; 352 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 353 mes_add_queue_pkt.gws_base = input->gws_base; 354 mes_add_queue_pkt.gws_size = input->gws_size; 355 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 356 mes_add_queue_pkt.tma_addr = input->tma_addr; 357 mes_add_queue_pkt.trap_en = input->trap_en; 358 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 359 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 360 361 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 362 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 363 mes_add_queue_pkt.gds_size = input->queue_size; 364 365 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 366 367 return mes_v11_0_submit_pkt_and_poll_completion(mes, 368 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 369 offsetof(union MESAPI__ADD_QUEUE, api_status)); 370 } 371 372 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 373 struct mes_remove_queue_input *input) 374 { 375 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 376 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 377 378 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 379 380 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 381 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 382 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 383 384 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 385 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 386 387 if (mes_rev >= 0x60) 388 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 389 390 return mes_v11_0_submit_pkt_and_poll_completion(mes, 391 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 392 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 393 } 394 395 static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev) 396 { 397 /* Disable the pipe reset until the CPFW fully support it.*/ 398 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 399 return false; 400 } 401 static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 402 u32 me, u32 pipe, u32 queue) 403 { 404 uint32_t reset_pipe = 0, clean_pipe = 0; 405 int r; 406 407 if (!mes_v11_0_pipe_reset_support(adev)) 408 return -EOPNOTSUPP; 409 410 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 411 mutex_lock(&adev->srbm_mutex); 412 soc21_grbm_select(adev, me, pipe, queue, 0); 413 414 switch (pipe) { 415 case 0: 416 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 417 PFP_PIPE0_RESET, 1); 418 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 419 ME_PIPE0_RESET, 1); 420 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 421 PFP_PIPE0_RESET, 0); 422 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 423 ME_PIPE0_RESET, 0); 424 break; 425 case 1: 426 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 427 PFP_PIPE1_RESET, 1); 428 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 429 ME_PIPE1_RESET, 1); 430 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 431 PFP_PIPE1_RESET, 0); 432 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 433 ME_PIPE1_RESET, 0); 434 break; 435 default: 436 break; 437 } 438 439 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 440 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 441 442 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 443 RS64_FW_UC_START_ADDR_LO; 444 soc21_grbm_select(adev, 0, 0, 0, 0); 445 mutex_unlock(&adev->srbm_mutex); 446 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 447 448 dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n", 449 r == 0 ? "successfully" : "failed"); 450 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 451 * so the pipe reset status relies on the later gfx ring test result. 452 */ 453 return 0; 454 } 455 456 /* 457 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 458 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 459 * asserted; only then clear the pipe reset bit. 460 * Caller must hold adev->srbm_mutex. 461 */ 462 static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 463 u32 pipe) 464 { 465 unsigned int q; 466 467 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 468 soc21_grbm_select(adev, me, pipe, q, 0); 469 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 470 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 471 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 472 } 473 } 474 475 static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 476 u32 me, u32 pipe, u32 queue) 477 { 478 uint32_t reset_val, clean_val; 479 int r; 480 481 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 482 mutex_lock(&adev->srbm_mutex); 483 soc21_grbm_select(adev, me, pipe, queue, 0); 484 485 if (adev->gfx.rs64_enable) { 486 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 487 clean_val = reset_val; 488 489 switch (pipe) { 490 case 0: 491 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 492 MEC_PIPE0_RESET, 1); 493 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 494 MEC_PIPE0_RESET, 0); 495 break; 496 case 1: 497 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 498 MEC_PIPE1_RESET, 1); 499 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 500 MEC_PIPE1_RESET, 0); 501 break; 502 case 2: 503 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 504 MEC_PIPE2_RESET, 1); 505 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 506 MEC_PIPE2_RESET, 0); 507 break; 508 case 3: 509 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 510 MEC_PIPE3_RESET, 1); 511 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 512 MEC_PIPE3_RESET, 0); 513 break; 514 default: 515 break; 516 } 517 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 518 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 519 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 520 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 521 RS64_FW_UC_START_ADDR_LO; 522 } else { 523 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 524 clean_val = reset_val; 525 526 if (me == 1) { 527 switch (pipe) { 528 case 0: 529 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 530 MEC_ME1_PIPE0_RESET, 1); 531 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 532 MEC_ME1_PIPE0_RESET, 0); 533 break; 534 case 1: 535 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 536 MEC_ME1_PIPE1_RESET, 1); 537 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 538 MEC_ME1_PIPE1_RESET, 0); 539 break; 540 case 2: 541 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 542 MEC_ME1_PIPE2_RESET, 1); 543 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 544 MEC_ME1_PIPE2_RESET, 0); 545 break; 546 case 3: 547 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 548 MEC_ME1_PIPE3_RESET, 1); 549 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 550 MEC_ME1_PIPE3_RESET, 0); 551 break; 552 default: 553 break; 554 } 555 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 556 } else { 557 switch (pipe) { 558 case 0: 559 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 560 MEC_ME2_PIPE0_RESET, 1); 561 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 562 MEC_ME2_PIPE0_RESET, 0); 563 break; 564 case 1: 565 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 566 MEC_ME2_PIPE1_RESET, 1); 567 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 568 MEC_ME2_PIPE1_RESET, 0); 569 break; 570 case 2: 571 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 572 MEC_ME2_PIPE2_RESET, 1); 573 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 574 MEC_ME2_PIPE2_RESET, 0); 575 break; 576 case 3: 577 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 578 MEC_ME2_PIPE3_RESET, 1); 579 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 580 MEC_ME2_PIPE3_RESET, 0); 581 break; 582 default: 583 break; 584 } 585 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 586 } 587 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 588 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 589 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 590 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 591 } 592 593 soc21_grbm_select(adev, 0, 0, 0, 0); 594 mutex_unlock(&adev->srbm_mutex); 595 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 596 597 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 598 me, pipe, queue, r == 0 ? "successfully" : "failed"); 599 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 600 * reset status relies on the compute ring test result. 601 */ 602 return 0; 603 } 604 605 static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 606 uint32_t me_id, uint32_t pipe_id, 607 uint32_t queue_id, uint32_t vmid) 608 { 609 struct amdgpu_device *adev = mes->adev; 610 611 if (queue_type == AMDGPU_RING_TYPE_GFX) 612 return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 613 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 614 return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 615 else 616 return -EOPNOTSUPP; 617 } 618 619 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 620 uint32_t me_id, uint32_t pipe_id, 621 uint32_t queue_id, uint32_t vmid) 622 { 623 struct amdgpu_device *adev = mes->adev; 624 uint32_t value, reg; 625 int i, r = 0; 626 627 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 628 629 if (queue_type == AMDGPU_RING_TYPE_GFX) { 630 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 631 me_id, pipe_id, queue_id, vmid); 632 633 mutex_lock(&adev->gfx.reset_sem_mutex); 634 gfx_v11_0_request_gfx_index_mutex(adev, true); 635 /* all se allow writes */ 636 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 637 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 638 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 639 if (pipe_id == 0) 640 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 641 else 642 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 643 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 644 gfx_v11_0_request_gfx_index_mutex(adev, false); 645 mutex_unlock(&adev->gfx.reset_sem_mutex); 646 647 mutex_lock(&adev->srbm_mutex); 648 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 649 /* wait till dequeue take effects */ 650 for (i = 0; i < adev->usec_timeout; i++) { 651 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 652 break; 653 udelay(1); 654 } 655 if (i >= adev->usec_timeout) { 656 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 657 r = -ETIMEDOUT; 658 } 659 660 soc21_grbm_select(adev, 0, 0, 0, 0); 661 mutex_unlock(&adev->srbm_mutex); 662 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 663 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 664 me_id, pipe_id, queue_id); 665 mutex_lock(&adev->srbm_mutex); 666 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 667 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 668 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 669 670 /* wait till dequeue take effects */ 671 for (i = 0; i < adev->usec_timeout; i++) { 672 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 673 break; 674 udelay(1); 675 } 676 if (i >= adev->usec_timeout) { 677 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 678 r = -ETIMEDOUT; 679 } 680 soc21_grbm_select(adev, 0, 0, 0, 0); 681 mutex_unlock(&adev->srbm_mutex); 682 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 683 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 684 me_id, pipe_id, queue_id); 685 switch (me_id) { 686 case 1: 687 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 688 break; 689 case 0: 690 default: 691 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 692 break; 693 } 694 695 value = 1 << queue_id; 696 WREG32(reg, value); 697 /* wait for queue reset done */ 698 for (i = 0; i < adev->usec_timeout; i++) { 699 if (!(RREG32(reg) & value)) 700 break; 701 udelay(1); 702 } 703 if (i >= adev->usec_timeout) { 704 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 705 r = -ETIMEDOUT; 706 } 707 } 708 709 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 710 return r; 711 } 712 713 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 714 struct mes_map_legacy_queue_input *input) 715 { 716 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 717 718 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 719 720 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 721 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 722 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 723 724 mes_add_queue_pkt.pipe_id = input->pipe_id; 725 mes_add_queue_pkt.queue_id = input->queue_id; 726 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 727 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 728 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 729 mes_add_queue_pkt.queue_type = 730 convert_to_mes_queue_type(input->queue_type); 731 mes_add_queue_pkt.map_legacy_kq = 1; 732 733 return mes_v11_0_submit_pkt_and_poll_completion(mes, 734 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 735 offsetof(union MESAPI__ADD_QUEUE, api_status)); 736 } 737 738 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 739 struct mes_unmap_legacy_queue_input *input) 740 { 741 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 742 743 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 744 745 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 746 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 747 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 748 749 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 750 mes_remove_queue_pkt.gang_context_addr = 0; 751 752 mes_remove_queue_pkt.pipe_id = input->pipe_id; 753 mes_remove_queue_pkt.queue_id = input->queue_id; 754 755 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 756 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 757 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 758 mes_remove_queue_pkt.tf_data = 759 lower_32_bits(input->trail_fence_data); 760 } else { 761 mes_remove_queue_pkt.unmap_legacy_queue = 1; 762 mes_remove_queue_pkt.queue_type = 763 convert_to_mes_queue_type(input->queue_type); 764 } 765 766 return mes_v11_0_submit_pkt_and_poll_completion(mes, 767 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 768 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 769 } 770 771 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 772 struct mes_suspend_gang_input *input) 773 { 774 union MESAPI__SUSPEND mes_suspend_gang_pkt; 775 776 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 777 778 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 779 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 780 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 781 782 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 783 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 784 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 785 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 786 787 return mes_v11_0_submit_pkt_and_poll_completion(mes, 788 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 789 offsetof(union MESAPI__SUSPEND, api_status)); 790 } 791 792 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 793 struct mes_resume_gang_input *input) 794 { 795 union MESAPI__RESUME mes_resume_gang_pkt; 796 797 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 798 799 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 800 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 801 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 802 803 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 804 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 805 806 return mes_v11_0_submit_pkt_and_poll_completion(mes, 807 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 808 offsetof(union MESAPI__RESUME, api_status)); 809 } 810 811 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 812 { 813 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 814 815 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 816 817 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 818 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 819 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 820 821 return mes_v11_0_submit_pkt_and_poll_completion(mes, 822 &mes_status_pkt, sizeof(mes_status_pkt), 823 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 824 } 825 826 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 827 struct mes_misc_op_input *input) 828 { 829 union MESAPI__MISC misc_pkt; 830 831 memset(&misc_pkt, 0, sizeof(misc_pkt)); 832 833 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 834 misc_pkt.header.opcode = MES_SCH_API_MISC; 835 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 836 837 switch (input->op) { 838 case MES_MISC_OP_READ_REG: 839 misc_pkt.opcode = MESAPI_MISC__READ_REG; 840 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 841 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 842 break; 843 case MES_MISC_OP_WRITE_REG: 844 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 845 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 846 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 847 break; 848 case MES_MISC_OP_WRM_REG_WAIT: 849 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 850 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 851 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 852 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 853 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 854 misc_pkt.wait_reg_mem.reg_offset2 = 0; 855 break; 856 case MES_MISC_OP_WRM_REG_WR_WAIT: 857 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 858 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 859 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 860 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 861 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 862 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 863 break; 864 case MES_MISC_OP_SET_SHADER_DEBUGGER: 865 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 866 misc_pkt.set_shader_debugger.process_context_addr = 867 input->set_shader_debugger.process_context_addr; 868 misc_pkt.set_shader_debugger.flags.u32all = 869 input->set_shader_debugger.flags.u32all; 870 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 871 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 872 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 873 input->set_shader_debugger.tcp_watch_cntl, 874 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 875 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 876 break; 877 case MES_MISC_OP_CHANGE_CONFIG: 878 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 879 dev_warn_once(mes->adev->dev, 880 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 881 return 0; 882 } 883 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 884 misc_pkt.change_config.opcode = 885 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 886 misc_pkt.change_config.option.bits.limit_single_process = 887 input->change_config.option.limit_single_process; 888 break; 889 890 default: 891 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 892 return -EINVAL; 893 } 894 895 return mes_v11_0_submit_pkt_and_poll_completion(mes, 896 &misc_pkt, sizeof(misc_pkt), 897 offsetof(union MESAPI__MISC, api_status)); 898 } 899 900 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 901 { 902 int i; 903 struct amdgpu_device *adev = mes->adev; 904 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 905 906 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 907 908 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 909 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 910 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 911 912 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 913 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 914 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 915 mes_set_hw_res_pkt.paging_vmid = 0; 916 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 917 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 918 mes->query_status_fence_gpu_addr[0]; 919 920 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 921 mes_set_hw_res_pkt.compute_hqd_mask[i] = 922 mes->compute_hqd_mask[i]; 923 924 for (i = 0; i < MAX_GFX_PIPES; i++) 925 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 926 mes->gfx_hqd_mask[i]; 927 928 for (i = 0; i < MAX_SDMA_PIPES; i++) 929 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 930 931 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 932 mes_set_hw_res_pkt.aggregated_doorbells[i] = 933 mes->aggregated_doorbells[i]; 934 935 for (i = 0; i < 5; i++) { 936 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 937 mes_set_hw_res_pkt.mmhub_base[i] = 938 adev->reg_offset[MMHUB_HWIP][0][i]; 939 mes_set_hw_res_pkt.osssys_base[i] = 940 adev->reg_offset[OSSSYS_HWIP][0][i]; 941 } 942 943 mes_set_hw_res_pkt.disable_reset = 1; 944 mes_set_hw_res_pkt.disable_mes_log = 1; 945 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 946 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 947 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 948 mes_set_hw_res_pkt.oversubscription_timer = 50; 949 950 if (amdgpu_mes_log_enable) { 951 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 952 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 953 mes->event_log_gpu_addr; 954 } 955 956 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 957 mes_set_hw_res_pkt.limit_single_process = 1; 958 959 return mes_v11_0_submit_pkt_and_poll_completion(mes, 960 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 961 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 962 } 963 964 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 965 { 966 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 967 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 968 969 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 970 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 971 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 972 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 973 974 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 975 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 976 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 977 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 978 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 979 } 980 981 return mes_v11_0_submit_pkt_and_poll_completion(mes, 982 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 983 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 984 } 985 986 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 987 struct mes_reset_queue_input *input) 988 { 989 union MESAPI__RESET mes_reset_queue_pkt; 990 991 if (input->use_mmio) { 992 int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type, 993 input->me_id, input->pipe_id, 994 input->queue_id, input->vmid); 995 if (r) 996 return mes_v11_0_reset_pipe_mmio(mes, input->queue_type, 997 input->me_id, input->pipe_id, 998 input->queue_id, input->vmid); 999 return 0; 1000 } 1001 1002 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1003 1004 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1005 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1006 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1007 1008 mes_reset_queue_pkt.queue_type = 1009 convert_to_mes_queue_type(input->queue_type); 1010 1011 if (input->legacy_gfx) { 1012 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1013 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1014 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1015 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1016 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1017 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1018 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1019 } else { 1020 mes_reset_queue_pkt.reset_queue_only = 1; 1021 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1022 } 1023 1024 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1025 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1026 offsetof(union MESAPI__RESET, api_status)); 1027 } 1028 1029 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1030 struct mes_detect_and_reset_queue_input *input) 1031 { 1032 union MESAPI__RESET mes_reset_queue_pkt; 1033 1034 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1035 1036 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1037 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1038 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1039 1040 mes_reset_queue_pkt.queue_type = 1041 convert_to_mes_queue_type(input->queue_type); 1042 mes_reset_queue_pkt.doorbell_offset_addr = 1043 mes->hung_queue_db_array_gpu_addr[0]; 1044 1045 if (input->detect_only) 1046 mes_reset_queue_pkt.hang_detect_only = 1; 1047 else 1048 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1049 1050 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1051 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1052 offsetof(union MESAPI__RESET, api_status)); 1053 } 1054 1055 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 1056 .add_hw_queue = mes_v11_0_add_hw_queue, 1057 .remove_hw_queue = mes_v11_0_remove_hw_queue, 1058 .map_legacy_queue = mes_v11_0_map_legacy_queue, 1059 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 1060 .suspend_gang = mes_v11_0_suspend_gang, 1061 .resume_gang = mes_v11_0_resume_gang, 1062 .misc_op = mes_v11_0_misc_op, 1063 .reset_hw_queue = mes_v11_0_reset_hw_queue, 1064 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 1065 }; 1066 1067 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1068 enum amdgpu_mes_pipe pipe) 1069 { 1070 int r; 1071 const struct mes_firmware_header_v1_0 *mes_hdr; 1072 const __le32 *fw_data; 1073 unsigned fw_size; 1074 1075 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1076 adev->mes.fw[pipe]->data; 1077 1078 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1079 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1080 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1081 1082 r = amdgpu_bo_create_reserved(adev, fw_size, 1083 PAGE_SIZE, 1084 AMDGPU_GEM_DOMAIN_VRAM | 1085 AMDGPU_GEM_DOMAIN_GTT, 1086 &adev->mes.ucode_fw_obj[pipe], 1087 &adev->mes.ucode_fw_gpu_addr[pipe], 1088 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1089 if (r) { 1090 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1091 return r; 1092 } 1093 1094 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1095 1096 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1097 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1098 1099 return 0; 1100 } 1101 1102 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1103 enum amdgpu_mes_pipe pipe) 1104 { 1105 int r; 1106 const struct mes_firmware_header_v1_0 *mes_hdr; 1107 const __le32 *fw_data; 1108 unsigned fw_size; 1109 1110 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1111 adev->mes.fw[pipe]->data; 1112 1113 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1114 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1115 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1116 1117 if (fw_size > GFX_MES_DRAM_SIZE) { 1118 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 1119 pipe, fw_size, GFX_MES_DRAM_SIZE); 1120 return -EINVAL; 1121 } 1122 1123 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 1124 64 * 1024, 1125 AMDGPU_GEM_DOMAIN_VRAM | 1126 AMDGPU_GEM_DOMAIN_GTT, 1127 &adev->mes.data_fw_obj[pipe], 1128 &adev->mes.data_fw_gpu_addr[pipe], 1129 (void **)&adev->mes.data_fw_ptr[pipe]); 1130 if (r) { 1131 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1132 return r; 1133 } 1134 1135 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1136 1137 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1138 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1139 1140 return 0; 1141 } 1142 1143 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 1144 enum amdgpu_mes_pipe pipe) 1145 { 1146 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1147 &adev->mes.data_fw_gpu_addr[pipe], 1148 (void **)&adev->mes.data_fw_ptr[pipe]); 1149 1150 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1151 &adev->mes.ucode_fw_gpu_addr[pipe], 1152 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1153 } 1154 1155 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 1156 { 1157 int pipe; 1158 1159 /* return early if we have already fetched these */ 1160 if (adev->mes.sched_version && adev->mes.kiq_version) 1161 return; 1162 1163 /* get MES scheduler/KIQ versions */ 1164 mutex_lock(&adev->srbm_mutex); 1165 1166 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1167 soc21_grbm_select(adev, 3, pipe, 0, 0); 1168 1169 if (pipe == AMDGPU_MES_SCHED_PIPE) 1170 adev->mes.sched_version = 1171 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1172 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1173 adev->mes.kiq_version = 1174 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1175 } 1176 1177 soc21_grbm_select(adev, 0, 0, 0, 0); 1178 mutex_unlock(&adev->srbm_mutex); 1179 } 1180 1181 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 1182 { 1183 uint64_t ucode_addr; 1184 uint32_t pipe, data = 0; 1185 1186 if (enable) { 1187 if (amdgpu_mes_log_enable) { 1188 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1189 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1190 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1191 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1192 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1193 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1194 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1195 } 1196 1197 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1198 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1199 data = REG_SET_FIELD(data, CP_MES_CNTL, 1200 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 1201 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1202 1203 mutex_lock(&adev->srbm_mutex); 1204 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1205 if (!adev->enable_mes_kiq && 1206 pipe == AMDGPU_MES_KIQ_PIPE) 1207 continue; 1208 1209 soc21_grbm_select(adev, 3, pipe, 0, 0); 1210 1211 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1212 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1213 lower_32_bits(ucode_addr)); 1214 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1215 upper_32_bits(ucode_addr)); 1216 } 1217 soc21_grbm_select(adev, 0, 0, 0, 0); 1218 mutex_unlock(&adev->srbm_mutex); 1219 1220 /* unhalt MES and activate pipe0 */ 1221 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1222 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1223 adev->enable_mes_kiq ? 1 : 0); 1224 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1225 1226 if (amdgpu_emu_mode) 1227 msleep(100); 1228 else 1229 udelay(500); 1230 } else { 1231 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1232 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1233 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1234 data = REG_SET_FIELD(data, CP_MES_CNTL, 1235 MES_INVALIDATE_ICACHE, 1); 1236 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1237 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1238 adev->enable_mes_kiq ? 1 : 0); 1239 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1240 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1241 } 1242 } 1243 1244 /* This function is for backdoor MES firmware */ 1245 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1246 enum amdgpu_mes_pipe pipe, bool prime_icache) 1247 { 1248 int r; 1249 uint32_t data; 1250 uint64_t ucode_addr; 1251 1252 mes_v11_0_enable(adev, false); 1253 1254 if (!adev->mes.fw[pipe]) 1255 return -EINVAL; 1256 1257 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1258 if (r) 1259 return r; 1260 1261 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1262 if (r) { 1263 mes_v11_0_free_ucode_buffers(adev, pipe); 1264 return r; 1265 } 1266 1267 mutex_lock(&adev->srbm_mutex); 1268 /* me=3, pipe=0, queue=0 */ 1269 soc21_grbm_select(adev, 3, pipe, 0, 0); 1270 1271 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1272 1273 /* set ucode start address */ 1274 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1275 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1276 lower_32_bits(ucode_addr)); 1277 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1278 upper_32_bits(ucode_addr)); 1279 1280 /* set ucode fimrware address */ 1281 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1282 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1283 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1284 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1285 1286 /* set ucode instruction cache boundary to 2M-1 */ 1287 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1288 1289 /* set ucode data firmware address */ 1290 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1291 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1292 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1293 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1294 1295 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1296 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1297 1298 if (prime_icache) { 1299 /* invalidate ICACHE */ 1300 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1301 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1302 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1303 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1304 1305 /* prime the ICACHE. */ 1306 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1307 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1308 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1309 } 1310 1311 soc21_grbm_select(adev, 0, 0, 0, 0); 1312 mutex_unlock(&adev->srbm_mutex); 1313 1314 return 0; 1315 } 1316 1317 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1318 enum amdgpu_mes_pipe pipe) 1319 { 1320 int r; 1321 u32 *eop; 1322 1323 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1324 AMDGPU_GEM_DOMAIN_GTT, 1325 &adev->mes.eop_gpu_obj[pipe], 1326 &adev->mes.eop_gpu_addr[pipe], 1327 (void **)&eop); 1328 if (r) { 1329 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1330 return r; 1331 } 1332 1333 memset(eop, 0, 1334 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1335 1336 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1337 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1338 1339 return 0; 1340 } 1341 1342 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1343 { 1344 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1345 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1346 uint32_t tmp; 1347 1348 memset(mqd, 0, sizeof(*mqd)); 1349 1350 mqd->header = 0xC0310800; 1351 mqd->compute_pipelinestat_enable = 0x00000001; 1352 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1353 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1354 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1355 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1356 mqd->compute_misc_reserved = 0x00000007; 1357 1358 eop_base_addr = ring->eop_gpu_addr >> 8; 1359 1360 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1361 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1362 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1363 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1364 1365 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1366 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1367 mqd->cp_hqd_eop_control = tmp; 1368 1369 /* disable the queue if it's active */ 1370 ring->wptr = 0; 1371 mqd->cp_hqd_pq_rptr = 0; 1372 mqd->cp_hqd_pq_wptr_lo = 0; 1373 mqd->cp_hqd_pq_wptr_hi = 0; 1374 1375 /* set the pointer to the MQD */ 1376 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1377 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1378 1379 /* set MQD vmid to 0 */ 1380 tmp = regCP_MQD_CONTROL_DEFAULT; 1381 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1382 mqd->cp_mqd_control = tmp; 1383 1384 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1385 hqd_gpu_addr = ring->gpu_addr >> 8; 1386 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1387 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1388 1389 /* set the wb address whether it's enabled or not */ 1390 wb_gpu_addr = ring->rptr_gpu_addr; 1391 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1392 mqd->cp_hqd_pq_rptr_report_addr_hi = 1393 upper_32_bits(wb_gpu_addr) & 0xffff; 1394 1395 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1396 wb_gpu_addr = ring->wptr_gpu_addr; 1397 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1398 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1399 1400 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1401 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1402 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1403 (order_base_2(ring->ring_size / 4) - 1)); 1404 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1405 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1406 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1407 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1408 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1409 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1410 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1411 mqd->cp_hqd_pq_control = tmp; 1412 1413 /* enable doorbell */ 1414 tmp = 0; 1415 if (ring->use_doorbell) { 1416 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1417 DOORBELL_OFFSET, ring->doorbell_index); 1418 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1419 DOORBELL_EN, 1); 1420 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1421 DOORBELL_SOURCE, 0); 1422 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1423 DOORBELL_HIT, 0); 1424 } else 1425 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1426 DOORBELL_EN, 0); 1427 mqd->cp_hqd_pq_doorbell_control = tmp; 1428 1429 mqd->cp_hqd_vmid = 0; 1430 /* activate the queue */ 1431 mqd->cp_hqd_active = 1; 1432 1433 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1434 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1435 PRELOAD_SIZE, 0x55); 1436 mqd->cp_hqd_persistent_state = tmp; 1437 1438 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1439 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1440 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1441 1442 amdgpu_device_flush_hdp(ring->adev, NULL); 1443 return 0; 1444 } 1445 1446 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1447 { 1448 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1449 struct amdgpu_device *adev = ring->adev; 1450 uint32_t data = 0; 1451 1452 mutex_lock(&adev->srbm_mutex); 1453 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1454 1455 /* set CP_HQD_VMID.VMID = 0. */ 1456 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1457 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1458 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1459 1460 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1461 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1462 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1463 DOORBELL_EN, 0); 1464 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1465 1466 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1467 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1468 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1469 1470 /* set CP_MQD_CONTROL.VMID=0 */ 1471 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1472 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1473 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1474 1475 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1476 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1477 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1478 1479 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1480 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1481 mqd->cp_hqd_pq_rptr_report_addr_lo); 1482 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1483 mqd->cp_hqd_pq_rptr_report_addr_hi); 1484 1485 /* set CP_HQD_PQ_CONTROL */ 1486 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1487 1488 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1489 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1490 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1491 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1492 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1493 1494 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1495 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1496 mqd->cp_hqd_pq_doorbell_control); 1497 1498 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1499 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1500 1501 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1502 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1503 1504 soc21_grbm_select(adev, 0, 0, 0, 0); 1505 mutex_unlock(&adev->srbm_mutex); 1506 } 1507 1508 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1509 { 1510 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1511 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1512 int r; 1513 1514 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1515 return -EINVAL; 1516 1517 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1518 if (r) { 1519 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1520 return r; 1521 } 1522 1523 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1524 1525 return amdgpu_ring_test_helper(kiq_ring); 1526 } 1527 1528 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1529 enum amdgpu_mes_pipe pipe) 1530 { 1531 struct amdgpu_ring *ring; 1532 int r; 1533 1534 if (pipe == AMDGPU_MES_KIQ_PIPE) 1535 ring = &adev->gfx.kiq[0].ring; 1536 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1537 ring = &adev->mes.ring[0]; 1538 else 1539 BUG(); 1540 1541 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1542 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1543 *(ring->wptr_cpu_addr) = 0; 1544 *(ring->rptr_cpu_addr) = 0; 1545 amdgpu_ring_clear_ring(ring); 1546 } 1547 1548 r = mes_v11_0_mqd_init(ring); 1549 if (r) 1550 return r; 1551 1552 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1553 r = mes_v11_0_kiq_enable_queue(adev); 1554 if (r) 1555 return r; 1556 } else { 1557 mes_v11_0_queue_init_register(ring); 1558 } 1559 1560 return 0; 1561 } 1562 1563 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1564 { 1565 struct amdgpu_ring *ring; 1566 1567 ring = &adev->mes.ring[0]; 1568 1569 ring->funcs = &mes_v11_0_ring_funcs; 1570 1571 ring->me = 3; 1572 ring->pipe = 0; 1573 ring->queue = 0; 1574 1575 ring->ring_obj = NULL; 1576 ring->use_doorbell = true; 1577 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1578 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1579 ring->no_scheduler = true; 1580 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1581 1582 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1583 AMDGPU_RING_PRIO_DEFAULT, NULL); 1584 } 1585 1586 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1587 { 1588 struct amdgpu_ring *ring; 1589 1590 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1591 1592 ring = &adev->gfx.kiq[0].ring; 1593 1594 ring->me = 3; 1595 ring->pipe = 1; 1596 ring->queue = 0; 1597 1598 ring->adev = NULL; 1599 ring->ring_obj = NULL; 1600 ring->use_doorbell = true; 1601 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1602 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1603 ring->no_scheduler = true; 1604 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1605 ring->me, ring->pipe, ring->queue); 1606 1607 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1608 AMDGPU_RING_PRIO_DEFAULT, NULL); 1609 } 1610 1611 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1612 enum amdgpu_mes_pipe pipe) 1613 { 1614 int r, mqd_size = sizeof(struct v11_compute_mqd); 1615 struct amdgpu_ring *ring; 1616 1617 if (pipe == AMDGPU_MES_KIQ_PIPE) 1618 ring = &adev->gfx.kiq[0].ring; 1619 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1620 ring = &adev->mes.ring[0]; 1621 else 1622 BUG(); 1623 1624 if (ring->mqd_obj) 1625 return 0; 1626 1627 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1628 AMDGPU_GEM_DOMAIN_VRAM | 1629 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1630 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1631 if (r) { 1632 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1633 return r; 1634 } 1635 1636 memset(ring->mqd_ptr, 0, mqd_size); 1637 1638 /* prepare MQD backup */ 1639 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1640 if (!adev->mes.mqd_backup[pipe]) { 1641 dev_warn(adev->dev, 1642 "no memory to create MQD backup for ring %s\n", 1643 ring->name); 1644 return -ENOMEM; 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1651 { 1652 struct amdgpu_device *adev = ip_block->adev; 1653 int pipe, r, bo_size; 1654 1655 adev->mes.funcs = &mes_v11_0_funcs; 1656 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1657 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1658 1659 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1660 1661 r = amdgpu_mes_init(adev); 1662 if (r) 1663 return r; 1664 1665 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1666 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1667 continue; 1668 1669 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1670 if (r) 1671 return r; 1672 1673 r = mes_v11_0_mqd_sw_init(adev, pipe); 1674 if (r) 1675 return r; 1676 } 1677 1678 if (adev->enable_mes_kiq) { 1679 r = mes_v11_0_kiq_ring_init(adev); 1680 if (r) 1681 return r; 1682 } 1683 1684 r = mes_v11_0_ring_init(adev); 1685 if (r) 1686 return r; 1687 1688 bo_size = AMDGPU_GPU_PAGE_SIZE; 1689 if (amdgpu_sriov_is_mes_info_enable(adev)) 1690 bo_size += MES11_HW_RESOURCE_1_SIZE; 1691 1692 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1693 r = amdgpu_bo_create_kernel(adev, 1694 bo_size, 1695 PAGE_SIZE, 1696 AMDGPU_GEM_DOMAIN_VRAM, 1697 &adev->mes.resource_1[0], 1698 &adev->mes.resource_1_gpu_addr[0], 1699 &adev->mes.resource_1_addr[0]); 1700 if (r) { 1701 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1702 return r; 1703 } 1704 1705 return 0; 1706 } 1707 1708 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1709 { 1710 struct amdgpu_device *adev = ip_block->adev; 1711 int pipe; 1712 1713 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1714 &adev->mes.resource_1_addr[0]); 1715 1716 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1717 kfree(adev->mes.mqd_backup[pipe]); 1718 1719 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1720 &adev->mes.eop_gpu_addr[pipe], 1721 NULL); 1722 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1723 } 1724 1725 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1726 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1727 &adev->gfx.kiq[0].ring.mqd_ptr); 1728 1729 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1730 &adev->mes.ring[0].mqd_gpu_addr, 1731 &adev->mes.ring[0].mqd_ptr); 1732 1733 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1734 amdgpu_ring_fini(&adev->mes.ring[0]); 1735 1736 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1737 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1738 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1739 } 1740 1741 amdgpu_mes_fini(adev); 1742 return 0; 1743 } 1744 1745 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1746 { 1747 uint32_t data; 1748 int i; 1749 struct amdgpu_device *adev = ring->adev; 1750 1751 mutex_lock(&adev->srbm_mutex); 1752 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1753 1754 /* disable the queue if it's active */ 1755 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1756 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1757 for (i = 0; i < adev->usec_timeout; i++) { 1758 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1759 break; 1760 udelay(1); 1761 } 1762 } 1763 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1764 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1765 DOORBELL_EN, 0); 1766 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1767 DOORBELL_HIT, 1); 1768 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1769 1770 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1771 1772 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1773 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1774 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1775 1776 soc21_grbm_select(adev, 0, 0, 0, 0); 1777 mutex_unlock(&adev->srbm_mutex); 1778 } 1779 1780 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1781 { 1782 uint32_t tmp; 1783 struct amdgpu_device *adev = ring->adev; 1784 1785 /* tell RLC which is KIQ queue */ 1786 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1787 tmp &= 0xffffff00; 1788 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1789 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1790 } 1791 1792 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1793 { 1794 uint32_t tmp; 1795 1796 /* tell RLC which is KIQ dequeue */ 1797 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1798 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1799 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1800 } 1801 1802 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1803 { 1804 int r = 0; 1805 struct amdgpu_ip_block *ip_block; 1806 1807 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1808 1809 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1810 if (r) { 1811 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1812 return r; 1813 } 1814 1815 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1816 if (r) { 1817 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1818 return r; 1819 } 1820 1821 } 1822 1823 mes_v11_0_enable(adev, true); 1824 1825 mes_v11_0_get_fw_version(adev); 1826 1827 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1828 1829 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1830 if (unlikely(!ip_block)) { 1831 dev_err(adev->dev, "Failed to get MES handle\n"); 1832 return -EINVAL; 1833 } 1834 1835 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1836 if (r) 1837 goto failure; 1838 1839 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1840 adev->mes.enable_legacy_queue_map = true; 1841 else 1842 adev->mes.enable_legacy_queue_map = false; 1843 1844 if (adev->mes.enable_legacy_queue_map) { 1845 r = mes_v11_0_hw_init(ip_block); 1846 if (r) 1847 goto failure; 1848 } 1849 1850 return r; 1851 1852 failure: 1853 mes_v11_0_hw_fini(ip_block); 1854 return r; 1855 } 1856 1857 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1858 { 1859 if (adev->mes.ring[0].sched.ready) { 1860 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1861 adev->mes.ring[0].sched.ready = false; 1862 } 1863 1864 if (amdgpu_sriov_vf(adev)) { 1865 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1866 mes_v11_0_kiq_clear(adev); 1867 } 1868 1869 mes_v11_0_enable(adev, false); 1870 1871 return 0; 1872 } 1873 1874 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1875 { 1876 int r; 1877 struct amdgpu_device *adev = ip_block->adev; 1878 1879 if (adev->mes.ring[0].sched.ready) 1880 goto out; 1881 1882 if (!adev->enable_mes_kiq) { 1883 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1884 r = mes_v11_0_load_microcode(adev, 1885 AMDGPU_MES_SCHED_PIPE, true); 1886 if (r) { 1887 DRM_ERROR("failed to MES fw, r=%d\n", r); 1888 return r; 1889 } 1890 } 1891 1892 mes_v11_0_enable(adev, true); 1893 } 1894 1895 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1896 if (r) 1897 goto failure; 1898 1899 r = mes_v11_0_set_hw_resources(&adev->mes); 1900 if (r) 1901 goto failure; 1902 1903 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1904 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1905 if (r) { 1906 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1907 goto failure; 1908 } 1909 } 1910 1911 r = mes_v11_0_query_sched_status(&adev->mes); 1912 if (r) { 1913 DRM_ERROR("MES is busy\n"); 1914 goto failure; 1915 } 1916 1917 r = amdgpu_mes_update_enforce_isolation(adev); 1918 if (r) 1919 goto failure; 1920 1921 amdgpu_mes_validate_fw_version(adev); 1922 out: 1923 /* 1924 * Disable KIQ ring usage from the driver once MES is enabled. 1925 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1926 * with MES enabled. 1927 */ 1928 adev->gfx.kiq[0].ring.sched.ready = false; 1929 adev->mes.ring[0].sched.ready = true; 1930 1931 return 0; 1932 1933 failure: 1934 mes_v11_0_hw_fini(ip_block); 1935 return r; 1936 } 1937 1938 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1939 { 1940 return 0; 1941 } 1942 1943 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1944 { 1945 return mes_v11_0_hw_fini(ip_block); 1946 } 1947 1948 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1949 { 1950 return mes_v11_0_hw_init(ip_block); 1951 } 1952 1953 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1954 { 1955 struct amdgpu_device *adev = ip_block->adev; 1956 int pipe, r; 1957 1958 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1959 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1960 1961 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1962 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1963 continue; 1964 r = amdgpu_mes_init_microcode(adev, pipe); 1965 if (r) 1966 return r; 1967 } 1968 1969 return 0; 1970 } 1971 1972 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1973 .name = "mes_v11_0", 1974 .early_init = mes_v11_0_early_init, 1975 .late_init = NULL, 1976 .sw_init = mes_v11_0_sw_init, 1977 .sw_fini = mes_v11_0_sw_fini, 1978 .hw_init = mes_v11_0_hw_init, 1979 .hw_fini = mes_v11_0_hw_fini, 1980 .suspend = mes_v11_0_suspend, 1981 .resume = mes_v11_0_resume, 1982 }; 1983 1984 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1985 .type = AMD_IP_BLOCK_TYPE_MES, 1986 .major = 11, 1987 .minor = 0, 1988 .rev = 0, 1989 .funcs = &mes_v11_0_ip_funcs, 1990 }; 1991