1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 55 56 static int mes_v11_0_hw_fini(void *handle); 57 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 58 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 59 60 #define MES_EOP_SIZE 2048 61 #define GFX_MES_DRAM_SIZE 0x80000 62 63 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 if (ring->use_doorbell) { 68 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 69 ring->wptr); 70 WDOORBELL64(ring->doorbell_index, ring->wptr); 71 } else { 72 BUG(); 73 } 74 } 75 76 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 77 { 78 return *ring->rptr_cpu_addr; 79 } 80 81 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 82 { 83 u64 wptr; 84 85 if (ring->use_doorbell) 86 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 87 else 88 BUG(); 89 return wptr; 90 } 91 92 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 93 .type = AMDGPU_RING_TYPE_MES, 94 .align_mask = 1, 95 .nop = 0, 96 .support_64bit_ptrs = true, 97 .get_rptr = mes_v11_0_ring_get_rptr, 98 .get_wptr = mes_v11_0_ring_get_wptr, 99 .set_wptr = mes_v11_0_ring_set_wptr, 100 .insert_nop = amdgpu_ring_insert_nop, 101 }; 102 103 static const char *mes_v11_0_opcodes[] = { 104 "SET_HW_RSRC", 105 "SET_SCHEDULING_CONFIG", 106 "ADD_QUEUE", 107 "REMOVE_QUEUE", 108 "PERFORM_YIELD", 109 "SET_GANG_PRIORITY_LEVEL", 110 "SUSPEND", 111 "RESUME", 112 "RESET", 113 "SET_LOG_BUFFER", 114 "CHANGE_GANG_PRORITY", 115 "QUERY_SCHEDULER_STATUS", 116 "PROGRAM_GDS", 117 "SET_DEBUG_VMID", 118 "MISC", 119 "UPDATE_ROOT_PAGE_TABLE", 120 "AMD_LOG", 121 }; 122 123 static const char *mes_v11_0_misc_opcodes[] = { 124 "WRITE_REG", 125 "INV_GART", 126 "QUERY_STATUS", 127 "READ_REG", 128 "WAIT_REG_MEM", 129 "SET_SHADER_DEBUGGER", 130 }; 131 132 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 133 { 134 const char *op_str = NULL; 135 136 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 137 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 138 139 return op_str; 140 } 141 142 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 143 { 144 const char *op_str = NULL; 145 146 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 147 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 148 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 149 150 return op_str; 151 } 152 153 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 154 void *pkt, int size, 155 int api_status_off) 156 { 157 int ndw = size / 4; 158 signed long r; 159 union MESAPI__MISC *x_pkt = pkt; 160 struct MES_API_STATUS *api_status; 161 struct amdgpu_device *adev = mes->adev; 162 struct amdgpu_ring *ring = &mes->ring; 163 unsigned long flags; 164 signed long timeout = 3000000; /* 3000 ms */ 165 const char *op_str, *misc_op_str; 166 167 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 168 return -EINVAL; 169 170 if (amdgpu_emu_mode) { 171 timeout *= 100; 172 } else if (amdgpu_sriov_vf(adev)) { 173 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 174 timeout = 15 * 600 * 1000; 175 } 176 BUG_ON(size % 4 != 0); 177 178 spin_lock_irqsave(&mes->ring_lock, flags); 179 if (amdgpu_ring_alloc(ring, ndw)) { 180 spin_unlock_irqrestore(&mes->ring_lock, flags); 181 return -ENOMEM; 182 } 183 184 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 185 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 186 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 187 188 amdgpu_ring_write_multiple(ring, pkt, ndw); 189 amdgpu_ring_commit(ring); 190 spin_unlock_irqrestore(&mes->ring_lock, flags); 191 192 op_str = mes_v11_0_get_op_string(x_pkt); 193 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 194 195 if (misc_op_str) 196 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, misc_op_str); 197 else if (op_str) 198 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 199 else 200 dev_dbg(adev->dev, "MES msg=%d was emitted\n", x_pkt->header.opcode); 201 202 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 203 timeout); 204 if (r < 1) { 205 206 if (misc_op_str) 207 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 208 op_str, misc_op_str); 209 else if (op_str) 210 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 211 op_str); 212 else 213 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 214 x_pkt->header.opcode); 215 216 while (halt_if_hws_hang) 217 schedule(); 218 219 return -ETIMEDOUT; 220 } 221 222 return 0; 223 } 224 225 static int convert_to_mes_queue_type(int queue_type) 226 { 227 if (queue_type == AMDGPU_RING_TYPE_GFX) 228 return MES_QUEUE_TYPE_GFX; 229 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 230 return MES_QUEUE_TYPE_COMPUTE; 231 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 232 return MES_QUEUE_TYPE_SDMA; 233 else 234 BUG(); 235 return -1; 236 } 237 238 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 239 struct mes_add_queue_input *input) 240 { 241 struct amdgpu_device *adev = mes->adev; 242 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 243 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 244 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 245 246 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 247 248 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 249 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 250 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 251 252 mes_add_queue_pkt.process_id = input->process_id; 253 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 254 mes_add_queue_pkt.process_va_start = input->process_va_start; 255 mes_add_queue_pkt.process_va_end = input->process_va_end; 256 mes_add_queue_pkt.process_quantum = input->process_quantum; 257 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 258 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 259 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 260 mes_add_queue_pkt.inprocess_gang_priority = 261 input->inprocess_gang_priority; 262 mes_add_queue_pkt.gang_global_priority_level = 263 input->gang_global_priority_level; 264 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 265 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 266 267 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 268 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 269 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 270 else 271 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 272 273 mes_add_queue_pkt.queue_type = 274 convert_to_mes_queue_type(input->queue_type); 275 mes_add_queue_pkt.paging = input->paging; 276 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 277 mes_add_queue_pkt.gws_base = input->gws_base; 278 mes_add_queue_pkt.gws_size = input->gws_size; 279 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 280 mes_add_queue_pkt.tma_addr = input->tma_addr; 281 mes_add_queue_pkt.trap_en = input->trap_en; 282 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 283 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 284 285 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 286 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 287 mes_add_queue_pkt.gds_size = input->queue_size; 288 289 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 290 291 return mes_v11_0_submit_pkt_and_poll_completion(mes, 292 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 293 offsetof(union MESAPI__ADD_QUEUE, api_status)); 294 } 295 296 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 297 struct mes_remove_queue_input *input) 298 { 299 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 300 301 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 302 303 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 304 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 305 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 306 307 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 308 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 309 310 return mes_v11_0_submit_pkt_and_poll_completion(mes, 311 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 312 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 313 } 314 315 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 316 struct mes_unmap_legacy_queue_input *input) 317 { 318 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 319 320 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 321 322 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 323 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 324 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 325 326 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 327 mes_remove_queue_pkt.gang_context_addr = 0; 328 329 mes_remove_queue_pkt.pipe_id = input->pipe_id; 330 mes_remove_queue_pkt.queue_id = input->queue_id; 331 332 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 333 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 334 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 335 mes_remove_queue_pkt.tf_data = 336 lower_32_bits(input->trail_fence_data); 337 } else { 338 mes_remove_queue_pkt.unmap_legacy_queue = 1; 339 mes_remove_queue_pkt.queue_type = 340 convert_to_mes_queue_type(input->queue_type); 341 } 342 343 return mes_v11_0_submit_pkt_and_poll_completion(mes, 344 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 345 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 346 } 347 348 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 349 struct mes_suspend_gang_input *input) 350 { 351 return 0; 352 } 353 354 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 355 struct mes_resume_gang_input *input) 356 { 357 return 0; 358 } 359 360 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 361 { 362 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 363 364 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 365 366 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 367 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 368 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 369 370 return mes_v11_0_submit_pkt_and_poll_completion(mes, 371 &mes_status_pkt, sizeof(mes_status_pkt), 372 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 373 } 374 375 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 376 struct mes_misc_op_input *input) 377 { 378 union MESAPI__MISC misc_pkt; 379 380 memset(&misc_pkt, 0, sizeof(misc_pkt)); 381 382 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 383 misc_pkt.header.opcode = MES_SCH_API_MISC; 384 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 385 386 switch (input->op) { 387 case MES_MISC_OP_READ_REG: 388 misc_pkt.opcode = MESAPI_MISC__READ_REG; 389 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 390 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 391 break; 392 case MES_MISC_OP_WRITE_REG: 393 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 394 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 395 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 396 break; 397 case MES_MISC_OP_WRM_REG_WAIT: 398 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 399 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 400 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 401 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 402 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 403 misc_pkt.wait_reg_mem.reg_offset2 = 0; 404 break; 405 case MES_MISC_OP_WRM_REG_WR_WAIT: 406 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 407 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 408 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 409 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 410 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 411 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 412 break; 413 case MES_MISC_OP_SET_SHADER_DEBUGGER: 414 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 415 misc_pkt.set_shader_debugger.process_context_addr = 416 input->set_shader_debugger.process_context_addr; 417 misc_pkt.set_shader_debugger.flags.u32all = 418 input->set_shader_debugger.flags.u32all; 419 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 420 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 421 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 422 input->set_shader_debugger.tcp_watch_cntl, 423 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 424 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 425 break; 426 default: 427 DRM_ERROR("unsupported misc op (%d) \n", input->op); 428 return -EINVAL; 429 } 430 431 return mes_v11_0_submit_pkt_and_poll_completion(mes, 432 &misc_pkt, sizeof(misc_pkt), 433 offsetof(union MESAPI__MISC, api_status)); 434 } 435 436 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 437 { 438 int i; 439 struct amdgpu_device *adev = mes->adev; 440 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 441 442 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 443 444 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 445 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 446 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 447 448 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 449 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 450 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 451 mes_set_hw_res_pkt.paging_vmid = 0; 452 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 453 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 454 mes->query_status_fence_gpu_addr; 455 456 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 457 mes_set_hw_res_pkt.compute_hqd_mask[i] = 458 mes->compute_hqd_mask[i]; 459 460 for (i = 0; i < MAX_GFX_PIPES; i++) 461 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 462 463 for (i = 0; i < MAX_SDMA_PIPES; i++) 464 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 465 466 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 467 mes_set_hw_res_pkt.aggregated_doorbells[i] = 468 mes->aggregated_doorbells[i]; 469 470 for (i = 0; i < 5; i++) { 471 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 472 mes_set_hw_res_pkt.mmhub_base[i] = 473 adev->reg_offset[MMHUB_HWIP][0][i]; 474 mes_set_hw_res_pkt.osssys_base[i] = 475 adev->reg_offset[OSSSYS_HWIP][0][i]; 476 } 477 478 mes_set_hw_res_pkt.disable_reset = 1; 479 mes_set_hw_res_pkt.disable_mes_log = 1; 480 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 481 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 482 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 483 mes_set_hw_res_pkt.oversubscription_timer = 50; 484 if (amdgpu_mes_log_enable) { 485 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 486 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 487 mes->event_log_gpu_addr; 488 } 489 490 return mes_v11_0_submit_pkt_and_poll_completion(mes, 491 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 492 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 493 } 494 495 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 496 { 497 int size = 128 * PAGE_SIZE; 498 int ret = 0; 499 struct amdgpu_device *adev = mes->adev; 500 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 501 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 502 503 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 504 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 505 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 506 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 507 508 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 509 AMDGPU_GEM_DOMAIN_VRAM, 510 &mes->resource_1, 511 &mes->resource_1_gpu_addr, 512 &mes->resource_1_addr); 513 if (ret) { 514 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 515 return ret; 516 } 517 518 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 519 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 520 return mes_v11_0_submit_pkt_and_poll_completion(mes, 521 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 522 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 523 } 524 525 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 526 .add_hw_queue = mes_v11_0_add_hw_queue, 527 .remove_hw_queue = mes_v11_0_remove_hw_queue, 528 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 529 .suspend_gang = mes_v11_0_suspend_gang, 530 .resume_gang = mes_v11_0_resume_gang, 531 .misc_op = mes_v11_0_misc_op, 532 }; 533 534 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 535 enum admgpu_mes_pipe pipe) 536 { 537 int r; 538 const struct mes_firmware_header_v1_0 *mes_hdr; 539 const __le32 *fw_data; 540 unsigned fw_size; 541 542 mes_hdr = (const struct mes_firmware_header_v1_0 *) 543 adev->mes.fw[pipe]->data; 544 545 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 546 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 547 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 548 549 r = amdgpu_bo_create_reserved(adev, fw_size, 550 PAGE_SIZE, 551 AMDGPU_GEM_DOMAIN_VRAM | 552 AMDGPU_GEM_DOMAIN_GTT, 553 &adev->mes.ucode_fw_obj[pipe], 554 &adev->mes.ucode_fw_gpu_addr[pipe], 555 (void **)&adev->mes.ucode_fw_ptr[pipe]); 556 if (r) { 557 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 558 return r; 559 } 560 561 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 562 563 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 564 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 565 566 return 0; 567 } 568 569 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 570 enum admgpu_mes_pipe pipe) 571 { 572 int r; 573 const struct mes_firmware_header_v1_0 *mes_hdr; 574 const __le32 *fw_data; 575 unsigned fw_size; 576 577 mes_hdr = (const struct mes_firmware_header_v1_0 *) 578 adev->mes.fw[pipe]->data; 579 580 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 581 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 582 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 583 584 if (fw_size > GFX_MES_DRAM_SIZE) { 585 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 586 pipe, fw_size, GFX_MES_DRAM_SIZE); 587 return -EINVAL; 588 } 589 590 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 591 64 * 1024, 592 AMDGPU_GEM_DOMAIN_VRAM | 593 AMDGPU_GEM_DOMAIN_GTT, 594 &adev->mes.data_fw_obj[pipe], 595 &adev->mes.data_fw_gpu_addr[pipe], 596 (void **)&adev->mes.data_fw_ptr[pipe]); 597 if (r) { 598 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 599 return r; 600 } 601 602 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 603 604 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 605 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 606 607 return 0; 608 } 609 610 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 611 enum admgpu_mes_pipe pipe) 612 { 613 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 614 &adev->mes.data_fw_gpu_addr[pipe], 615 (void **)&adev->mes.data_fw_ptr[pipe]); 616 617 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 618 &adev->mes.ucode_fw_gpu_addr[pipe], 619 (void **)&adev->mes.ucode_fw_ptr[pipe]); 620 } 621 622 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 623 { 624 uint64_t ucode_addr; 625 uint32_t pipe, data = 0; 626 627 if (enable) { 628 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 629 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 630 data = REG_SET_FIELD(data, CP_MES_CNTL, 631 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 632 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 633 634 mutex_lock(&adev->srbm_mutex); 635 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 636 if (!adev->enable_mes_kiq && 637 pipe == AMDGPU_MES_KIQ_PIPE) 638 continue; 639 640 soc21_grbm_select(adev, 3, pipe, 0, 0); 641 642 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 643 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 644 lower_32_bits(ucode_addr)); 645 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 646 upper_32_bits(ucode_addr)); 647 } 648 soc21_grbm_select(adev, 0, 0, 0, 0); 649 mutex_unlock(&adev->srbm_mutex); 650 651 /* unhalt MES and activate pipe0 */ 652 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 653 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 654 adev->enable_mes_kiq ? 1 : 0); 655 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 656 657 if (amdgpu_emu_mode) 658 msleep(100); 659 else 660 udelay(50); 661 } else { 662 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 663 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 664 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 665 data = REG_SET_FIELD(data, CP_MES_CNTL, 666 MES_INVALIDATE_ICACHE, 1); 667 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 668 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 669 adev->enable_mes_kiq ? 1 : 0); 670 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 671 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 672 } 673 } 674 675 /* This function is for backdoor MES firmware */ 676 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 677 enum admgpu_mes_pipe pipe, bool prime_icache) 678 { 679 int r; 680 uint32_t data; 681 uint64_t ucode_addr; 682 683 mes_v11_0_enable(adev, false); 684 685 if (!adev->mes.fw[pipe]) 686 return -EINVAL; 687 688 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 689 if (r) 690 return r; 691 692 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 693 if (r) { 694 mes_v11_0_free_ucode_buffers(adev, pipe); 695 return r; 696 } 697 698 mutex_lock(&adev->srbm_mutex); 699 /* me=3, pipe=0, queue=0 */ 700 soc21_grbm_select(adev, 3, pipe, 0, 0); 701 702 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 703 704 /* set ucode start address */ 705 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 706 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 707 lower_32_bits(ucode_addr)); 708 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 709 upper_32_bits(ucode_addr)); 710 711 /* set ucode fimrware address */ 712 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 713 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 714 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 715 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 716 717 /* set ucode instruction cache boundary to 2M-1 */ 718 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 719 720 /* set ucode data firmware address */ 721 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 722 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 723 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 724 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 725 726 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 727 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 728 729 if (prime_icache) { 730 /* invalidate ICACHE */ 731 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 732 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 733 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 734 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 735 736 /* prime the ICACHE. */ 737 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 738 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 739 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 740 } 741 742 soc21_grbm_select(adev, 0, 0, 0, 0); 743 mutex_unlock(&adev->srbm_mutex); 744 745 return 0; 746 } 747 748 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 749 enum admgpu_mes_pipe pipe) 750 { 751 int r; 752 u32 *eop; 753 754 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 755 AMDGPU_GEM_DOMAIN_GTT, 756 &adev->mes.eop_gpu_obj[pipe], 757 &adev->mes.eop_gpu_addr[pipe], 758 (void **)&eop); 759 if (r) { 760 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 761 return r; 762 } 763 764 memset(eop, 0, 765 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 766 767 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 768 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 769 770 return 0; 771 } 772 773 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 774 { 775 struct v11_compute_mqd *mqd = ring->mqd_ptr; 776 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 777 uint32_t tmp; 778 779 memset(mqd, 0, sizeof(*mqd)); 780 781 mqd->header = 0xC0310800; 782 mqd->compute_pipelinestat_enable = 0x00000001; 783 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 784 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 785 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 786 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 787 mqd->compute_misc_reserved = 0x00000007; 788 789 eop_base_addr = ring->eop_gpu_addr >> 8; 790 791 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 792 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 793 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 794 (order_base_2(MES_EOP_SIZE / 4) - 1)); 795 796 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 797 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 798 mqd->cp_hqd_eop_control = tmp; 799 800 /* disable the queue if it's active */ 801 ring->wptr = 0; 802 mqd->cp_hqd_pq_rptr = 0; 803 mqd->cp_hqd_pq_wptr_lo = 0; 804 mqd->cp_hqd_pq_wptr_hi = 0; 805 806 /* set the pointer to the MQD */ 807 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 808 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 809 810 /* set MQD vmid to 0 */ 811 tmp = regCP_MQD_CONTROL_DEFAULT; 812 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 813 mqd->cp_mqd_control = tmp; 814 815 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 816 hqd_gpu_addr = ring->gpu_addr >> 8; 817 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 818 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 819 820 /* set the wb address whether it's enabled or not */ 821 wb_gpu_addr = ring->rptr_gpu_addr; 822 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 823 mqd->cp_hqd_pq_rptr_report_addr_hi = 824 upper_32_bits(wb_gpu_addr) & 0xffff; 825 826 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 827 wb_gpu_addr = ring->wptr_gpu_addr; 828 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 829 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 830 831 /* set up the HQD, this is similar to CP_RB0_CNTL */ 832 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 833 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 834 (order_base_2(ring->ring_size / 4) - 1)); 835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 836 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 839 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 841 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 842 mqd->cp_hqd_pq_control = tmp; 843 844 /* enable doorbell */ 845 tmp = 0; 846 if (ring->use_doorbell) { 847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 848 DOORBELL_OFFSET, ring->doorbell_index); 849 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 850 DOORBELL_EN, 1); 851 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 852 DOORBELL_SOURCE, 0); 853 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 854 DOORBELL_HIT, 0); 855 } else 856 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 857 DOORBELL_EN, 0); 858 mqd->cp_hqd_pq_doorbell_control = tmp; 859 860 mqd->cp_hqd_vmid = 0; 861 /* activate the queue */ 862 mqd->cp_hqd_active = 1; 863 864 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 865 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 866 PRELOAD_SIZE, 0x55); 867 mqd->cp_hqd_persistent_state = tmp; 868 869 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 870 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 871 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 872 873 amdgpu_device_flush_hdp(ring->adev, NULL); 874 return 0; 875 } 876 877 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 878 { 879 struct v11_compute_mqd *mqd = ring->mqd_ptr; 880 struct amdgpu_device *adev = ring->adev; 881 uint32_t data = 0; 882 883 mutex_lock(&adev->srbm_mutex); 884 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 885 886 /* set CP_HQD_VMID.VMID = 0. */ 887 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 888 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 889 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 890 891 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 892 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 893 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 894 DOORBELL_EN, 0); 895 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 896 897 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 898 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 899 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 900 901 /* set CP_MQD_CONTROL.VMID=0 */ 902 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 903 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 904 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 905 906 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 907 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 908 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 909 910 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 911 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 912 mqd->cp_hqd_pq_rptr_report_addr_lo); 913 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 914 mqd->cp_hqd_pq_rptr_report_addr_hi); 915 916 /* set CP_HQD_PQ_CONTROL */ 917 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 918 919 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 920 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 921 mqd->cp_hqd_pq_wptr_poll_addr_lo); 922 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 923 mqd->cp_hqd_pq_wptr_poll_addr_hi); 924 925 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 926 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 927 mqd->cp_hqd_pq_doorbell_control); 928 929 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 930 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 931 932 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 933 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 934 935 soc21_grbm_select(adev, 0, 0, 0, 0); 936 mutex_unlock(&adev->srbm_mutex); 937 } 938 939 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 940 { 941 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 942 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 943 int r; 944 945 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 946 return -EINVAL; 947 948 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 949 if (r) { 950 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 951 return r; 952 } 953 954 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 955 956 return amdgpu_ring_test_helper(kiq_ring); 957 } 958 959 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 960 enum admgpu_mes_pipe pipe) 961 { 962 struct amdgpu_ring *ring; 963 int r; 964 965 if (pipe == AMDGPU_MES_KIQ_PIPE) 966 ring = &adev->gfx.kiq[0].ring; 967 else if (pipe == AMDGPU_MES_SCHED_PIPE) 968 ring = &adev->mes.ring; 969 else 970 BUG(); 971 972 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 973 (amdgpu_in_reset(adev) || adev->in_suspend)) { 974 *(ring->wptr_cpu_addr) = 0; 975 *(ring->rptr_cpu_addr) = 0; 976 amdgpu_ring_clear_ring(ring); 977 } 978 979 r = mes_v11_0_mqd_init(ring); 980 if (r) 981 return r; 982 983 if (pipe == AMDGPU_MES_SCHED_PIPE) { 984 r = mes_v11_0_kiq_enable_queue(adev); 985 if (r) 986 return r; 987 } else { 988 mes_v11_0_queue_init_register(ring); 989 } 990 991 /* get MES scheduler/KIQ versions */ 992 mutex_lock(&adev->srbm_mutex); 993 soc21_grbm_select(adev, 3, pipe, 0, 0); 994 995 if (pipe == AMDGPU_MES_SCHED_PIPE) 996 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 997 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 998 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 999 1000 soc21_grbm_select(adev, 0, 0, 0, 0); 1001 mutex_unlock(&adev->srbm_mutex); 1002 1003 return 0; 1004 } 1005 1006 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1007 { 1008 struct amdgpu_ring *ring; 1009 1010 ring = &adev->mes.ring; 1011 1012 ring->funcs = &mes_v11_0_ring_funcs; 1013 1014 ring->me = 3; 1015 ring->pipe = 0; 1016 ring->queue = 0; 1017 1018 ring->ring_obj = NULL; 1019 ring->use_doorbell = true; 1020 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1021 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1022 ring->no_scheduler = true; 1023 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1024 1025 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1026 AMDGPU_RING_PRIO_DEFAULT, NULL); 1027 } 1028 1029 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1030 { 1031 struct amdgpu_ring *ring; 1032 1033 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1034 1035 ring = &adev->gfx.kiq[0].ring; 1036 1037 ring->me = 3; 1038 ring->pipe = 1; 1039 ring->queue = 0; 1040 1041 ring->adev = NULL; 1042 ring->ring_obj = NULL; 1043 ring->use_doorbell = true; 1044 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1045 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1046 ring->no_scheduler = true; 1047 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1048 ring->me, ring->pipe, ring->queue); 1049 1050 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1051 AMDGPU_RING_PRIO_DEFAULT, NULL); 1052 } 1053 1054 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1055 enum admgpu_mes_pipe pipe) 1056 { 1057 int r, mqd_size = sizeof(struct v11_compute_mqd); 1058 struct amdgpu_ring *ring; 1059 1060 if (pipe == AMDGPU_MES_KIQ_PIPE) 1061 ring = &adev->gfx.kiq[0].ring; 1062 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1063 ring = &adev->mes.ring; 1064 else 1065 BUG(); 1066 1067 if (ring->mqd_obj) 1068 return 0; 1069 1070 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1071 AMDGPU_GEM_DOMAIN_VRAM | 1072 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1073 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1074 if (r) { 1075 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1076 return r; 1077 } 1078 1079 memset(ring->mqd_ptr, 0, mqd_size); 1080 1081 /* prepare MQD backup */ 1082 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1083 if (!adev->mes.mqd_backup[pipe]) { 1084 dev_warn(adev->dev, 1085 "no memory to create MQD backup for ring %s\n", 1086 ring->name); 1087 return -ENOMEM; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static int mes_v11_0_sw_init(void *handle) 1094 { 1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1096 int pipe, r; 1097 1098 adev->mes.funcs = &mes_v11_0_funcs; 1099 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1100 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1101 1102 r = amdgpu_mes_init(adev); 1103 if (r) 1104 return r; 1105 1106 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1107 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1108 continue; 1109 1110 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1111 if (r) 1112 return r; 1113 1114 r = mes_v11_0_mqd_sw_init(adev, pipe); 1115 if (r) 1116 return r; 1117 } 1118 1119 if (adev->enable_mes_kiq) { 1120 r = mes_v11_0_kiq_ring_init(adev); 1121 if (r) 1122 return r; 1123 } 1124 1125 r = mes_v11_0_ring_init(adev); 1126 if (r) 1127 return r; 1128 1129 return 0; 1130 } 1131 1132 static int mes_v11_0_sw_fini(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 int pipe; 1136 1137 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1138 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1139 1140 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1141 kfree(adev->mes.mqd_backup[pipe]); 1142 1143 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1144 &adev->mes.eop_gpu_addr[pipe], 1145 NULL); 1146 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1147 } 1148 1149 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1150 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1151 &adev->gfx.kiq[0].ring.mqd_ptr); 1152 1153 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1154 &adev->mes.ring.mqd_gpu_addr, 1155 &adev->mes.ring.mqd_ptr); 1156 1157 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1158 amdgpu_ring_fini(&adev->mes.ring); 1159 1160 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1161 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1162 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1163 } 1164 1165 amdgpu_mes_fini(adev); 1166 return 0; 1167 } 1168 1169 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1170 { 1171 uint32_t data; 1172 int i; 1173 struct amdgpu_device *adev = ring->adev; 1174 1175 mutex_lock(&adev->srbm_mutex); 1176 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1177 1178 /* disable the queue if it's active */ 1179 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1180 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1181 for (i = 0; i < adev->usec_timeout; i++) { 1182 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1183 break; 1184 udelay(1); 1185 } 1186 } 1187 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1188 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1189 DOORBELL_EN, 0); 1190 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1191 DOORBELL_HIT, 1); 1192 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1193 1194 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1195 1196 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1197 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1198 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1199 1200 soc21_grbm_select(adev, 0, 0, 0, 0); 1201 mutex_unlock(&adev->srbm_mutex); 1202 } 1203 1204 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1205 { 1206 uint32_t tmp; 1207 struct amdgpu_device *adev = ring->adev; 1208 1209 /* tell RLC which is KIQ queue */ 1210 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1211 tmp &= 0xffffff00; 1212 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1213 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1214 tmp |= 0x80; 1215 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1216 } 1217 1218 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1219 { 1220 uint32_t tmp; 1221 1222 /* tell RLC which is KIQ dequeue */ 1223 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1224 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1225 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1226 } 1227 1228 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1229 { 1230 int r = 0; 1231 1232 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1233 1234 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1235 if (r) { 1236 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1237 return r; 1238 } 1239 1240 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1241 if (r) { 1242 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1243 return r; 1244 } 1245 1246 } 1247 1248 mes_v11_0_enable(adev, true); 1249 1250 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1251 1252 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1253 if (r) 1254 goto failure; 1255 1256 return r; 1257 1258 failure: 1259 mes_v11_0_hw_fini(adev); 1260 return r; 1261 } 1262 1263 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1264 { 1265 if (adev->mes.ring.sched.ready) { 1266 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1267 adev->mes.ring.sched.ready = false; 1268 } 1269 1270 if (amdgpu_sriov_vf(adev)) { 1271 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1272 mes_v11_0_kiq_clear(adev); 1273 } 1274 1275 mes_v11_0_enable(adev, false); 1276 1277 return 0; 1278 } 1279 1280 static int mes_v11_0_hw_init(void *handle) 1281 { 1282 int r; 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 1285 if (!adev->enable_mes_kiq) { 1286 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1287 r = mes_v11_0_load_microcode(adev, 1288 AMDGPU_MES_SCHED_PIPE, true); 1289 if (r) { 1290 DRM_ERROR("failed to MES fw, r=%d\n", r); 1291 return r; 1292 } 1293 } 1294 1295 mes_v11_0_enable(adev, true); 1296 } 1297 1298 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1299 if (r) 1300 goto failure; 1301 1302 r = mes_v11_0_set_hw_resources(&adev->mes); 1303 if (r) 1304 goto failure; 1305 1306 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1307 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1308 if (r) { 1309 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1310 goto failure; 1311 } 1312 } 1313 1314 r = mes_v11_0_query_sched_status(&adev->mes); 1315 if (r) { 1316 DRM_ERROR("MES is busy\n"); 1317 goto failure; 1318 } 1319 1320 /* 1321 * Disable KIQ ring usage from the driver once MES is enabled. 1322 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1323 * with MES enabled. 1324 */ 1325 adev->gfx.kiq[0].ring.sched.ready = false; 1326 adev->mes.ring.sched.ready = true; 1327 1328 return 0; 1329 1330 failure: 1331 mes_v11_0_hw_fini(adev); 1332 return r; 1333 } 1334 1335 static int mes_v11_0_hw_fini(void *handle) 1336 { 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1339 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1340 &adev->mes.resource_1_addr); 1341 } 1342 return 0; 1343 } 1344 1345 static int mes_v11_0_suspend(void *handle) 1346 { 1347 int r; 1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1349 1350 r = amdgpu_mes_suspend(adev); 1351 if (r) 1352 return r; 1353 1354 return mes_v11_0_hw_fini(adev); 1355 } 1356 1357 static int mes_v11_0_resume(void *handle) 1358 { 1359 int r; 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1361 1362 r = mes_v11_0_hw_init(adev); 1363 if (r) 1364 return r; 1365 1366 return amdgpu_mes_resume(adev); 1367 } 1368 1369 static int mes_v11_0_early_init(void *handle) 1370 { 1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1372 int pipe, r; 1373 1374 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1375 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1376 continue; 1377 r = amdgpu_mes_init_microcode(adev, pipe); 1378 if (r) 1379 return r; 1380 } 1381 1382 return 0; 1383 } 1384 1385 static int mes_v11_0_late_init(void *handle) 1386 { 1387 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1388 1389 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1390 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1391 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1392 amdgpu_mes_self_test(adev); 1393 1394 return 0; 1395 } 1396 1397 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1398 .name = "mes_v11_0", 1399 .early_init = mes_v11_0_early_init, 1400 .late_init = mes_v11_0_late_init, 1401 .sw_init = mes_v11_0_sw_init, 1402 .sw_fini = mes_v11_0_sw_fini, 1403 .hw_init = mes_v11_0_hw_init, 1404 .hw_fini = mes_v11_0_hw_fini, 1405 .suspend = mes_v11_0_suspend, 1406 .resume = mes_v11_0_resume, 1407 }; 1408 1409 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1410 .type = AMD_IP_BLOCK_TYPE_MES, 1411 .major = 11, 1412 .minor = 0, 1413 .rev = 0, 1414 .funcs = &mes_v11_0_ip_funcs, 1415 }; 1416