1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 56 57 static int mes_v11_0_hw_init(void *handle); 58 static int mes_v11_0_hw_fini(void *handle); 59 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 60 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 61 62 #define MES_EOP_SIZE 2048 63 #define GFX_MES_DRAM_SIZE 0x80000 64 65 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 66 { 67 struct amdgpu_device *adev = ring->adev; 68 69 if (ring->use_doorbell) { 70 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 71 ring->wptr); 72 WDOORBELL64(ring->doorbell_index, ring->wptr); 73 } else { 74 BUG(); 75 } 76 } 77 78 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 79 { 80 return *ring->rptr_cpu_addr; 81 } 82 83 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 84 { 85 u64 wptr; 86 87 if (ring->use_doorbell) 88 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 89 else 90 BUG(); 91 return wptr; 92 } 93 94 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 95 .type = AMDGPU_RING_TYPE_MES, 96 .align_mask = 1, 97 .nop = 0, 98 .support_64bit_ptrs = true, 99 .get_rptr = mes_v11_0_ring_get_rptr, 100 .get_wptr = mes_v11_0_ring_get_wptr, 101 .set_wptr = mes_v11_0_ring_set_wptr, 102 .insert_nop = amdgpu_ring_insert_nop, 103 }; 104 105 static const char *mes_v11_0_opcodes[] = { 106 "SET_HW_RSRC", 107 "SET_SCHEDULING_CONFIG", 108 "ADD_QUEUE", 109 "REMOVE_QUEUE", 110 "PERFORM_YIELD", 111 "SET_GANG_PRIORITY_LEVEL", 112 "SUSPEND", 113 "RESUME", 114 "RESET", 115 "SET_LOG_BUFFER", 116 "CHANGE_GANG_PRORITY", 117 "QUERY_SCHEDULER_STATUS", 118 "PROGRAM_GDS", 119 "SET_DEBUG_VMID", 120 "MISC", 121 "UPDATE_ROOT_PAGE_TABLE", 122 "AMD_LOG", 123 "unused", 124 "unused", 125 "SET_HW_RSRC_1", 126 }; 127 128 static const char *mes_v11_0_misc_opcodes[] = { 129 "WRITE_REG", 130 "INV_GART", 131 "QUERY_STATUS", 132 "READ_REG", 133 "WAIT_REG_MEM", 134 "SET_SHADER_DEBUGGER", 135 }; 136 137 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 138 { 139 const char *op_str = NULL; 140 141 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 142 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 143 144 return op_str; 145 } 146 147 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 148 { 149 const char *op_str = NULL; 150 151 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 152 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 153 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 154 155 return op_str; 156 } 157 158 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 159 void *pkt, int size, 160 int api_status_off) 161 { 162 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 163 signed long timeout = 3000000; /* 3000 ms */ 164 struct amdgpu_device *adev = mes->adev; 165 struct amdgpu_ring *ring = &mes->ring[0]; 166 struct MES_API_STATUS *api_status; 167 union MESAPI__MISC *x_pkt = pkt; 168 const char *op_str, *misc_op_str; 169 unsigned long flags; 170 u64 status_gpu_addr; 171 u32 seq, status_offset; 172 u64 *status_ptr; 173 signed long r; 174 int ret; 175 176 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 177 return -EINVAL; 178 179 if (amdgpu_emu_mode) { 180 timeout *= 100; 181 } else if (amdgpu_sriov_vf(adev)) { 182 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 183 timeout = 15 * 600 * 1000; 184 } 185 186 ret = amdgpu_device_wb_get(adev, &status_offset); 187 if (ret) 188 return ret; 189 190 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 191 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 192 *status_ptr = 0; 193 194 spin_lock_irqsave(&mes->ring_lock[0], flags); 195 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 196 if (r) 197 goto error_unlock_free; 198 199 seq = ++ring->fence_drv.sync_seq; 200 r = amdgpu_fence_wait_polling(ring, 201 seq - ring->fence_drv.num_fences_mask, 202 timeout); 203 if (r < 1) 204 goto error_undo; 205 206 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 207 api_status->api_completion_fence_addr = status_gpu_addr; 208 api_status->api_completion_fence_value = 1; 209 210 amdgpu_ring_write_multiple(ring, pkt, size / 4); 211 212 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 213 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 214 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 215 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 216 mes_status_pkt.api_status.api_completion_fence_addr = 217 ring->fence_drv.gpu_addr; 218 mes_status_pkt.api_status.api_completion_fence_value = seq; 219 220 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 221 sizeof(mes_status_pkt) / 4); 222 223 amdgpu_ring_commit(ring); 224 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 225 226 op_str = mes_v11_0_get_op_string(x_pkt); 227 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 228 229 if (misc_op_str) 230 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 231 misc_op_str); 232 else if (op_str) 233 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 234 else 235 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 236 x_pkt->header.opcode); 237 238 r = amdgpu_fence_wait_polling(ring, seq, timeout); 239 if (r < 1 || !*status_ptr) { 240 241 if (misc_op_str) 242 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 243 op_str, misc_op_str); 244 else if (op_str) 245 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 246 op_str); 247 else 248 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 249 x_pkt->header.opcode); 250 251 while (halt_if_hws_hang) 252 schedule(); 253 254 r = -ETIMEDOUT; 255 goto error_wb_free; 256 } 257 258 amdgpu_device_wb_free(adev, status_offset); 259 return 0; 260 261 error_undo: 262 dev_err(adev->dev, "MES ring buffer is full.\n"); 263 amdgpu_ring_undo(ring); 264 265 error_unlock_free: 266 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 267 268 error_wb_free: 269 amdgpu_device_wb_free(adev, status_offset); 270 return r; 271 } 272 273 static int convert_to_mes_queue_type(int queue_type) 274 { 275 if (queue_type == AMDGPU_RING_TYPE_GFX) 276 return MES_QUEUE_TYPE_GFX; 277 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 278 return MES_QUEUE_TYPE_COMPUTE; 279 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 280 return MES_QUEUE_TYPE_SDMA; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 287 struct mes_add_queue_input *input) 288 { 289 struct amdgpu_device *adev = mes->adev; 290 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 291 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 292 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 293 294 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 295 296 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 297 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 298 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 299 300 mes_add_queue_pkt.process_id = input->process_id; 301 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 302 mes_add_queue_pkt.process_va_start = input->process_va_start; 303 mes_add_queue_pkt.process_va_end = input->process_va_end; 304 mes_add_queue_pkt.process_quantum = input->process_quantum; 305 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 306 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 307 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 308 mes_add_queue_pkt.inprocess_gang_priority = 309 input->inprocess_gang_priority; 310 mes_add_queue_pkt.gang_global_priority_level = 311 input->gang_global_priority_level; 312 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 313 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 314 315 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 316 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 317 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 318 else 319 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 320 321 mes_add_queue_pkt.queue_type = 322 convert_to_mes_queue_type(input->queue_type); 323 mes_add_queue_pkt.paging = input->paging; 324 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 325 mes_add_queue_pkt.gws_base = input->gws_base; 326 mes_add_queue_pkt.gws_size = input->gws_size; 327 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 328 mes_add_queue_pkt.tma_addr = input->tma_addr; 329 mes_add_queue_pkt.trap_en = input->trap_en; 330 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 331 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 332 333 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 334 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 335 mes_add_queue_pkt.gds_size = input->queue_size; 336 337 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 338 339 return mes_v11_0_submit_pkt_and_poll_completion(mes, 340 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 341 offsetof(union MESAPI__ADD_QUEUE, api_status)); 342 } 343 344 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 345 struct mes_remove_queue_input *input) 346 { 347 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 348 349 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 350 351 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 352 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 353 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 354 355 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 356 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 357 358 return mes_v11_0_submit_pkt_and_poll_completion(mes, 359 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 360 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 361 } 362 363 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 364 struct mes_map_legacy_queue_input *input) 365 { 366 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 367 368 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 369 370 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 371 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 372 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 373 374 mes_add_queue_pkt.pipe_id = input->pipe_id; 375 mes_add_queue_pkt.queue_id = input->queue_id; 376 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 377 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 378 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 379 mes_add_queue_pkt.queue_type = 380 convert_to_mes_queue_type(input->queue_type); 381 mes_add_queue_pkt.map_legacy_kq = 1; 382 383 return mes_v11_0_submit_pkt_and_poll_completion(mes, 384 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 385 offsetof(union MESAPI__ADD_QUEUE, api_status)); 386 } 387 388 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 389 struct mes_unmap_legacy_queue_input *input) 390 { 391 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 392 393 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 394 395 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 396 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 397 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 398 399 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 400 mes_remove_queue_pkt.gang_context_addr = 0; 401 402 mes_remove_queue_pkt.pipe_id = input->pipe_id; 403 mes_remove_queue_pkt.queue_id = input->queue_id; 404 405 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 406 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 407 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 408 mes_remove_queue_pkt.tf_data = 409 lower_32_bits(input->trail_fence_data); 410 } else { 411 mes_remove_queue_pkt.unmap_legacy_queue = 1; 412 mes_remove_queue_pkt.queue_type = 413 convert_to_mes_queue_type(input->queue_type); 414 } 415 416 return mes_v11_0_submit_pkt_and_poll_completion(mes, 417 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 418 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 419 } 420 421 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 422 struct mes_suspend_gang_input *input) 423 { 424 return 0; 425 } 426 427 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 428 struct mes_resume_gang_input *input) 429 { 430 return 0; 431 } 432 433 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 434 { 435 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 436 437 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 438 439 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 440 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 441 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 442 443 return mes_v11_0_submit_pkt_and_poll_completion(mes, 444 &mes_status_pkt, sizeof(mes_status_pkt), 445 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 446 } 447 448 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 449 struct mes_misc_op_input *input) 450 { 451 union MESAPI__MISC misc_pkt; 452 453 memset(&misc_pkt, 0, sizeof(misc_pkt)); 454 455 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 456 misc_pkt.header.opcode = MES_SCH_API_MISC; 457 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 458 459 switch (input->op) { 460 case MES_MISC_OP_READ_REG: 461 misc_pkt.opcode = MESAPI_MISC__READ_REG; 462 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 463 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 464 break; 465 case MES_MISC_OP_WRITE_REG: 466 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 467 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 468 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 469 break; 470 case MES_MISC_OP_WRM_REG_WAIT: 471 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 472 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 473 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 474 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 475 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 476 misc_pkt.wait_reg_mem.reg_offset2 = 0; 477 break; 478 case MES_MISC_OP_WRM_REG_WR_WAIT: 479 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 480 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 481 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 482 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 483 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 484 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 485 break; 486 case MES_MISC_OP_SET_SHADER_DEBUGGER: 487 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 488 misc_pkt.set_shader_debugger.process_context_addr = 489 input->set_shader_debugger.process_context_addr; 490 misc_pkt.set_shader_debugger.flags.u32all = 491 input->set_shader_debugger.flags.u32all; 492 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 493 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 494 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 495 input->set_shader_debugger.tcp_watch_cntl, 496 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 497 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 498 break; 499 default: 500 DRM_ERROR("unsupported misc op (%d) \n", input->op); 501 return -EINVAL; 502 } 503 504 return mes_v11_0_submit_pkt_and_poll_completion(mes, 505 &misc_pkt, sizeof(misc_pkt), 506 offsetof(union MESAPI__MISC, api_status)); 507 } 508 509 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 510 { 511 int i; 512 struct amdgpu_device *adev = mes->adev; 513 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 514 515 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 516 517 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 518 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 519 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 520 521 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 522 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 523 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 524 mes_set_hw_res_pkt.paging_vmid = 0; 525 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 526 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 527 mes->query_status_fence_gpu_addr[0]; 528 529 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 530 mes_set_hw_res_pkt.compute_hqd_mask[i] = 531 mes->compute_hqd_mask[i]; 532 533 for (i = 0; i < MAX_GFX_PIPES; i++) 534 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 535 536 for (i = 0; i < MAX_SDMA_PIPES; i++) 537 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 538 539 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 540 mes_set_hw_res_pkt.aggregated_doorbells[i] = 541 mes->aggregated_doorbells[i]; 542 543 for (i = 0; i < 5; i++) { 544 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 545 mes_set_hw_res_pkt.mmhub_base[i] = 546 adev->reg_offset[MMHUB_HWIP][0][i]; 547 mes_set_hw_res_pkt.osssys_base[i] = 548 adev->reg_offset[OSSSYS_HWIP][0][i]; 549 } 550 551 mes_set_hw_res_pkt.disable_reset = 1; 552 mes_set_hw_res_pkt.disable_mes_log = 1; 553 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 554 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 555 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 556 mes_set_hw_res_pkt.oversubscription_timer = 50; 557 if (amdgpu_mes_log_enable) { 558 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 559 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 560 mes->event_log_gpu_addr; 561 } 562 563 return mes_v11_0_submit_pkt_and_poll_completion(mes, 564 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 565 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 566 } 567 568 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 569 { 570 int size = 128 * PAGE_SIZE; 571 int ret = 0; 572 struct amdgpu_device *adev = mes->adev; 573 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 574 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 575 576 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 577 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 578 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 579 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 580 581 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 582 AMDGPU_GEM_DOMAIN_VRAM, 583 &mes->resource_1, 584 &mes->resource_1_gpu_addr, 585 &mes->resource_1_addr); 586 if (ret) { 587 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 588 return ret; 589 } 590 591 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 592 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 593 return mes_v11_0_submit_pkt_and_poll_completion(mes, 594 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 595 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 596 } 597 598 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 599 .add_hw_queue = mes_v11_0_add_hw_queue, 600 .remove_hw_queue = mes_v11_0_remove_hw_queue, 601 .map_legacy_queue = mes_v11_0_map_legacy_queue, 602 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 603 .suspend_gang = mes_v11_0_suspend_gang, 604 .resume_gang = mes_v11_0_resume_gang, 605 .misc_op = mes_v11_0_misc_op, 606 }; 607 608 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 609 enum admgpu_mes_pipe pipe) 610 { 611 int r; 612 const struct mes_firmware_header_v1_0 *mes_hdr; 613 const __le32 *fw_data; 614 unsigned fw_size; 615 616 mes_hdr = (const struct mes_firmware_header_v1_0 *) 617 adev->mes.fw[pipe]->data; 618 619 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 620 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 621 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 622 623 r = amdgpu_bo_create_reserved(adev, fw_size, 624 PAGE_SIZE, 625 AMDGPU_GEM_DOMAIN_VRAM | 626 AMDGPU_GEM_DOMAIN_GTT, 627 &adev->mes.ucode_fw_obj[pipe], 628 &adev->mes.ucode_fw_gpu_addr[pipe], 629 (void **)&adev->mes.ucode_fw_ptr[pipe]); 630 if (r) { 631 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 632 return r; 633 } 634 635 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 636 637 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 638 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 639 640 return 0; 641 } 642 643 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 644 enum admgpu_mes_pipe pipe) 645 { 646 int r; 647 const struct mes_firmware_header_v1_0 *mes_hdr; 648 const __le32 *fw_data; 649 unsigned fw_size; 650 651 mes_hdr = (const struct mes_firmware_header_v1_0 *) 652 adev->mes.fw[pipe]->data; 653 654 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 655 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 656 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 657 658 if (fw_size > GFX_MES_DRAM_SIZE) { 659 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 660 pipe, fw_size, GFX_MES_DRAM_SIZE); 661 return -EINVAL; 662 } 663 664 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 665 64 * 1024, 666 AMDGPU_GEM_DOMAIN_VRAM | 667 AMDGPU_GEM_DOMAIN_GTT, 668 &adev->mes.data_fw_obj[pipe], 669 &adev->mes.data_fw_gpu_addr[pipe], 670 (void **)&adev->mes.data_fw_ptr[pipe]); 671 if (r) { 672 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 673 return r; 674 } 675 676 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 677 678 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 679 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 680 681 return 0; 682 } 683 684 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 685 enum admgpu_mes_pipe pipe) 686 { 687 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 688 &adev->mes.data_fw_gpu_addr[pipe], 689 (void **)&adev->mes.data_fw_ptr[pipe]); 690 691 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 692 &adev->mes.ucode_fw_gpu_addr[pipe], 693 (void **)&adev->mes.ucode_fw_ptr[pipe]); 694 } 695 696 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 697 { 698 int pipe; 699 700 /* get MES scheduler/KIQ versions */ 701 mutex_lock(&adev->srbm_mutex); 702 703 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 704 soc21_grbm_select(adev, 3, pipe, 0, 0); 705 706 if (pipe == AMDGPU_MES_SCHED_PIPE) 707 adev->mes.sched_version = 708 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 709 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 710 adev->mes.kiq_version = 711 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 712 } 713 714 soc21_grbm_select(adev, 0, 0, 0, 0); 715 mutex_unlock(&adev->srbm_mutex); 716 } 717 718 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 719 { 720 uint64_t ucode_addr; 721 uint32_t pipe, data = 0; 722 723 if (enable) { 724 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 725 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 726 data = REG_SET_FIELD(data, CP_MES_CNTL, 727 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 728 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 729 730 mutex_lock(&adev->srbm_mutex); 731 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 732 if (!adev->enable_mes_kiq && 733 pipe == AMDGPU_MES_KIQ_PIPE) 734 continue; 735 736 soc21_grbm_select(adev, 3, pipe, 0, 0); 737 738 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 739 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 740 lower_32_bits(ucode_addr)); 741 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 742 upper_32_bits(ucode_addr)); 743 } 744 soc21_grbm_select(adev, 0, 0, 0, 0); 745 mutex_unlock(&adev->srbm_mutex); 746 747 /* unhalt MES and activate pipe0 */ 748 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 749 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 750 adev->enable_mes_kiq ? 1 : 0); 751 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 752 753 if (amdgpu_emu_mode) 754 msleep(100); 755 else 756 udelay(500); 757 } else { 758 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 759 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 760 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 761 data = REG_SET_FIELD(data, CP_MES_CNTL, 762 MES_INVALIDATE_ICACHE, 1); 763 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 764 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 765 adev->enable_mes_kiq ? 1 : 0); 766 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 767 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 768 } 769 } 770 771 /* This function is for backdoor MES firmware */ 772 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 773 enum admgpu_mes_pipe pipe, bool prime_icache) 774 { 775 int r; 776 uint32_t data; 777 uint64_t ucode_addr; 778 779 mes_v11_0_enable(adev, false); 780 781 if (!adev->mes.fw[pipe]) 782 return -EINVAL; 783 784 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 785 if (r) 786 return r; 787 788 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 789 if (r) { 790 mes_v11_0_free_ucode_buffers(adev, pipe); 791 return r; 792 } 793 794 mutex_lock(&adev->srbm_mutex); 795 /* me=3, pipe=0, queue=0 */ 796 soc21_grbm_select(adev, 3, pipe, 0, 0); 797 798 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 799 800 /* set ucode start address */ 801 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 802 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 803 lower_32_bits(ucode_addr)); 804 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 805 upper_32_bits(ucode_addr)); 806 807 /* set ucode fimrware address */ 808 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 809 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 810 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 811 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 812 813 /* set ucode instruction cache boundary to 2M-1 */ 814 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 815 816 /* set ucode data firmware address */ 817 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 818 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 819 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 820 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 821 822 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 823 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 824 825 if (prime_icache) { 826 /* invalidate ICACHE */ 827 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 828 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 829 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 830 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 831 832 /* prime the ICACHE. */ 833 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 834 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 835 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 836 } 837 838 soc21_grbm_select(adev, 0, 0, 0, 0); 839 mutex_unlock(&adev->srbm_mutex); 840 841 return 0; 842 } 843 844 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 845 enum admgpu_mes_pipe pipe) 846 { 847 int r; 848 u32 *eop; 849 850 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 851 AMDGPU_GEM_DOMAIN_GTT, 852 &adev->mes.eop_gpu_obj[pipe], 853 &adev->mes.eop_gpu_addr[pipe], 854 (void **)&eop); 855 if (r) { 856 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 857 return r; 858 } 859 860 memset(eop, 0, 861 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 862 863 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 864 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 865 866 return 0; 867 } 868 869 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 870 { 871 struct v11_compute_mqd *mqd = ring->mqd_ptr; 872 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 873 uint32_t tmp; 874 875 memset(mqd, 0, sizeof(*mqd)); 876 877 mqd->header = 0xC0310800; 878 mqd->compute_pipelinestat_enable = 0x00000001; 879 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 880 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 881 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 882 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 883 mqd->compute_misc_reserved = 0x00000007; 884 885 eop_base_addr = ring->eop_gpu_addr >> 8; 886 887 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 888 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 889 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 890 (order_base_2(MES_EOP_SIZE / 4) - 1)); 891 892 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 893 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 894 mqd->cp_hqd_eop_control = tmp; 895 896 /* disable the queue if it's active */ 897 ring->wptr = 0; 898 mqd->cp_hqd_pq_rptr = 0; 899 mqd->cp_hqd_pq_wptr_lo = 0; 900 mqd->cp_hqd_pq_wptr_hi = 0; 901 902 /* set the pointer to the MQD */ 903 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 904 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 905 906 /* set MQD vmid to 0 */ 907 tmp = regCP_MQD_CONTROL_DEFAULT; 908 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 909 mqd->cp_mqd_control = tmp; 910 911 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 912 hqd_gpu_addr = ring->gpu_addr >> 8; 913 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 914 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 915 916 /* set the wb address whether it's enabled or not */ 917 wb_gpu_addr = ring->rptr_gpu_addr; 918 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 919 mqd->cp_hqd_pq_rptr_report_addr_hi = 920 upper_32_bits(wb_gpu_addr) & 0xffff; 921 922 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 923 wb_gpu_addr = ring->wptr_gpu_addr; 924 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 925 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 926 927 /* set up the HQD, this is similar to CP_RB0_CNTL */ 928 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 929 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 930 (order_base_2(ring->ring_size / 4) - 1)); 931 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 932 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 933 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 934 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 935 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 936 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 937 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 938 mqd->cp_hqd_pq_control = tmp; 939 940 /* enable doorbell */ 941 tmp = 0; 942 if (ring->use_doorbell) { 943 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 944 DOORBELL_OFFSET, ring->doorbell_index); 945 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 946 DOORBELL_EN, 1); 947 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 948 DOORBELL_SOURCE, 0); 949 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 950 DOORBELL_HIT, 0); 951 } else 952 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 953 DOORBELL_EN, 0); 954 mqd->cp_hqd_pq_doorbell_control = tmp; 955 956 mqd->cp_hqd_vmid = 0; 957 /* activate the queue */ 958 mqd->cp_hqd_active = 1; 959 960 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 961 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 962 PRELOAD_SIZE, 0x55); 963 mqd->cp_hqd_persistent_state = tmp; 964 965 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 966 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 967 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 968 969 amdgpu_device_flush_hdp(ring->adev, NULL); 970 return 0; 971 } 972 973 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 974 { 975 struct v11_compute_mqd *mqd = ring->mqd_ptr; 976 struct amdgpu_device *adev = ring->adev; 977 uint32_t data = 0; 978 979 mutex_lock(&adev->srbm_mutex); 980 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 981 982 /* set CP_HQD_VMID.VMID = 0. */ 983 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 984 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 985 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 986 987 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 988 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 989 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 990 DOORBELL_EN, 0); 991 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 992 993 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 994 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 995 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 996 997 /* set CP_MQD_CONTROL.VMID=0 */ 998 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 999 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1000 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1001 1002 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1003 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1004 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1005 1006 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1007 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1008 mqd->cp_hqd_pq_rptr_report_addr_lo); 1009 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1010 mqd->cp_hqd_pq_rptr_report_addr_hi); 1011 1012 /* set CP_HQD_PQ_CONTROL */ 1013 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1014 1015 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1016 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1017 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1018 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1019 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1020 1021 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1022 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1023 mqd->cp_hqd_pq_doorbell_control); 1024 1025 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1026 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1027 1028 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1029 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1030 1031 soc21_grbm_select(adev, 0, 0, 0, 0); 1032 mutex_unlock(&adev->srbm_mutex); 1033 } 1034 1035 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1036 { 1037 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1038 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1039 int r; 1040 1041 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1042 return -EINVAL; 1043 1044 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1045 if (r) { 1046 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1047 return r; 1048 } 1049 1050 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1051 1052 return amdgpu_ring_test_helper(kiq_ring); 1053 } 1054 1055 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1056 enum admgpu_mes_pipe pipe) 1057 { 1058 struct amdgpu_ring *ring; 1059 int r; 1060 1061 if (pipe == AMDGPU_MES_KIQ_PIPE) 1062 ring = &adev->gfx.kiq[0].ring; 1063 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1064 ring = &adev->mes.ring[0]; 1065 else 1066 BUG(); 1067 1068 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1069 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1070 *(ring->wptr_cpu_addr) = 0; 1071 *(ring->rptr_cpu_addr) = 0; 1072 amdgpu_ring_clear_ring(ring); 1073 } 1074 1075 r = mes_v11_0_mqd_init(ring); 1076 if (r) 1077 return r; 1078 1079 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1080 r = mes_v11_0_kiq_enable_queue(adev); 1081 if (r) 1082 return r; 1083 } else { 1084 mes_v11_0_queue_init_register(ring); 1085 } 1086 1087 return 0; 1088 } 1089 1090 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1091 { 1092 struct amdgpu_ring *ring; 1093 1094 ring = &adev->mes.ring[0]; 1095 1096 ring->funcs = &mes_v11_0_ring_funcs; 1097 1098 ring->me = 3; 1099 ring->pipe = 0; 1100 ring->queue = 0; 1101 1102 ring->ring_obj = NULL; 1103 ring->use_doorbell = true; 1104 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1105 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1106 ring->no_scheduler = true; 1107 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1108 1109 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1110 AMDGPU_RING_PRIO_DEFAULT, NULL); 1111 } 1112 1113 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1114 { 1115 struct amdgpu_ring *ring; 1116 1117 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1118 1119 ring = &adev->gfx.kiq[0].ring; 1120 1121 ring->me = 3; 1122 ring->pipe = 1; 1123 ring->queue = 0; 1124 1125 ring->adev = NULL; 1126 ring->ring_obj = NULL; 1127 ring->use_doorbell = true; 1128 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1129 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1130 ring->no_scheduler = true; 1131 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1132 ring->me, ring->pipe, ring->queue); 1133 1134 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1135 AMDGPU_RING_PRIO_DEFAULT, NULL); 1136 } 1137 1138 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1139 enum admgpu_mes_pipe pipe) 1140 { 1141 int r, mqd_size = sizeof(struct v11_compute_mqd); 1142 struct amdgpu_ring *ring; 1143 1144 if (pipe == AMDGPU_MES_KIQ_PIPE) 1145 ring = &adev->gfx.kiq[0].ring; 1146 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1147 ring = &adev->mes.ring[0]; 1148 else 1149 BUG(); 1150 1151 if (ring->mqd_obj) 1152 return 0; 1153 1154 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1155 AMDGPU_GEM_DOMAIN_VRAM | 1156 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1157 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1158 if (r) { 1159 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1160 return r; 1161 } 1162 1163 memset(ring->mqd_ptr, 0, mqd_size); 1164 1165 /* prepare MQD backup */ 1166 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1167 if (!adev->mes.mqd_backup[pipe]) { 1168 dev_warn(adev->dev, 1169 "no memory to create MQD backup for ring %s\n", 1170 ring->name); 1171 return -ENOMEM; 1172 } 1173 1174 return 0; 1175 } 1176 1177 static int mes_v11_0_sw_init(void *handle) 1178 { 1179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1180 int pipe, r; 1181 1182 adev->mes.funcs = &mes_v11_0_funcs; 1183 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1184 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1185 1186 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; 1187 1188 r = amdgpu_mes_init(adev); 1189 if (r) 1190 return r; 1191 1192 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1193 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1194 continue; 1195 1196 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1197 if (r) 1198 return r; 1199 1200 r = mes_v11_0_mqd_sw_init(adev, pipe); 1201 if (r) 1202 return r; 1203 } 1204 1205 if (adev->enable_mes_kiq) { 1206 r = mes_v11_0_kiq_ring_init(adev); 1207 if (r) 1208 return r; 1209 } 1210 1211 r = mes_v11_0_ring_init(adev); 1212 if (r) 1213 return r; 1214 1215 return 0; 1216 } 1217 1218 static int mes_v11_0_sw_fini(void *handle) 1219 { 1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1221 int pipe; 1222 1223 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1224 kfree(adev->mes.mqd_backup[pipe]); 1225 1226 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1227 &adev->mes.eop_gpu_addr[pipe], 1228 NULL); 1229 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1230 } 1231 1232 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1233 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1234 &adev->gfx.kiq[0].ring.mqd_ptr); 1235 1236 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1237 &adev->mes.ring[0].mqd_gpu_addr, 1238 &adev->mes.ring[0].mqd_ptr); 1239 1240 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1241 amdgpu_ring_fini(&adev->mes.ring[0]); 1242 1243 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1244 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1245 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1246 } 1247 1248 amdgpu_mes_fini(adev); 1249 return 0; 1250 } 1251 1252 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1253 { 1254 uint32_t data; 1255 int i; 1256 struct amdgpu_device *adev = ring->adev; 1257 1258 mutex_lock(&adev->srbm_mutex); 1259 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1260 1261 /* disable the queue if it's active */ 1262 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1263 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1264 for (i = 0; i < adev->usec_timeout; i++) { 1265 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1266 break; 1267 udelay(1); 1268 } 1269 } 1270 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1271 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1272 DOORBELL_EN, 0); 1273 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1274 DOORBELL_HIT, 1); 1275 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1276 1277 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1278 1279 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1280 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1281 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1282 1283 soc21_grbm_select(adev, 0, 0, 0, 0); 1284 mutex_unlock(&adev->srbm_mutex); 1285 } 1286 1287 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1288 { 1289 uint32_t tmp; 1290 struct amdgpu_device *adev = ring->adev; 1291 1292 /* tell RLC which is KIQ queue */ 1293 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1294 tmp &= 0xffffff00; 1295 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1296 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1297 tmp |= 0x80; 1298 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1299 } 1300 1301 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1302 { 1303 uint32_t tmp; 1304 1305 /* tell RLC which is KIQ dequeue */ 1306 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1307 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1308 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1309 } 1310 1311 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1312 { 1313 int r = 0; 1314 1315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1316 1317 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1318 if (r) { 1319 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1320 return r; 1321 } 1322 1323 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1324 if (r) { 1325 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1326 return r; 1327 } 1328 1329 } 1330 1331 mes_v11_0_enable(adev, true); 1332 1333 mes_v11_0_get_fw_version(adev); 1334 1335 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1336 1337 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1338 if (r) 1339 goto failure; 1340 1341 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1342 adev->mes.enable_legacy_queue_map = true; 1343 else 1344 adev->mes.enable_legacy_queue_map = false; 1345 1346 if (adev->mes.enable_legacy_queue_map) { 1347 r = mes_v11_0_hw_init(adev); 1348 if (r) 1349 goto failure; 1350 } 1351 1352 return r; 1353 1354 failure: 1355 mes_v11_0_hw_fini(adev); 1356 return r; 1357 } 1358 1359 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1360 { 1361 if (adev->mes.ring[0].sched.ready) { 1362 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1363 adev->mes.ring[0].sched.ready = false; 1364 } 1365 1366 if (amdgpu_sriov_vf(adev)) { 1367 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1368 mes_v11_0_kiq_clear(adev); 1369 } 1370 1371 mes_v11_0_enable(adev, false); 1372 1373 return 0; 1374 } 1375 1376 static int mes_v11_0_hw_init(void *handle) 1377 { 1378 int r; 1379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1380 1381 if (adev->mes.ring[0].sched.ready) 1382 goto out; 1383 1384 if (!adev->enable_mes_kiq) { 1385 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1386 r = mes_v11_0_load_microcode(adev, 1387 AMDGPU_MES_SCHED_PIPE, true); 1388 if (r) { 1389 DRM_ERROR("failed to MES fw, r=%d\n", r); 1390 return r; 1391 } 1392 } 1393 1394 mes_v11_0_enable(adev, true); 1395 } 1396 1397 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1398 if (r) 1399 goto failure; 1400 1401 r = mes_v11_0_set_hw_resources(&adev->mes); 1402 if (r) 1403 goto failure; 1404 1405 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1406 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1407 if (r) { 1408 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1409 goto failure; 1410 } 1411 } 1412 1413 r = mes_v11_0_query_sched_status(&adev->mes); 1414 if (r) { 1415 DRM_ERROR("MES is busy\n"); 1416 goto failure; 1417 } 1418 1419 out: 1420 /* 1421 * Disable KIQ ring usage from the driver once MES is enabled. 1422 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1423 * with MES enabled. 1424 */ 1425 adev->gfx.kiq[0].ring.sched.ready = false; 1426 adev->mes.ring[0].sched.ready = true; 1427 1428 return 0; 1429 1430 failure: 1431 mes_v11_0_hw_fini(adev); 1432 return r; 1433 } 1434 1435 static int mes_v11_0_hw_fini(void *handle) 1436 { 1437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1438 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1439 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1440 &adev->mes.resource_1_addr); 1441 } 1442 return 0; 1443 } 1444 1445 static int mes_v11_0_suspend(void *handle) 1446 { 1447 int r; 1448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1449 1450 r = amdgpu_mes_suspend(adev); 1451 if (r) 1452 return r; 1453 1454 return mes_v11_0_hw_fini(adev); 1455 } 1456 1457 static int mes_v11_0_resume(void *handle) 1458 { 1459 int r; 1460 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1461 1462 r = mes_v11_0_hw_init(adev); 1463 if (r) 1464 return r; 1465 1466 return amdgpu_mes_resume(adev); 1467 } 1468 1469 static int mes_v11_0_early_init(void *handle) 1470 { 1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1472 int pipe, r; 1473 1474 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1475 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1476 continue; 1477 r = amdgpu_mes_init_microcode(adev, pipe); 1478 if (r) 1479 return r; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static int mes_v11_0_late_init(void *handle) 1486 { 1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1488 1489 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1490 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1491 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1492 amdgpu_mes_self_test(adev); 1493 1494 return 0; 1495 } 1496 1497 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1498 .name = "mes_v11_0", 1499 .early_init = mes_v11_0_early_init, 1500 .late_init = mes_v11_0_late_init, 1501 .sw_init = mes_v11_0_sw_init, 1502 .sw_fini = mes_v11_0_sw_fini, 1503 .hw_init = mes_v11_0_hw_init, 1504 .hw_fini = mes_v11_0_hw_fini, 1505 .suspend = mes_v11_0_suspend, 1506 .resume = mes_v11_0_resume, 1507 .dump_ip_state = NULL, 1508 .print_ip_state = NULL, 1509 }; 1510 1511 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1512 .type = AMD_IP_BLOCK_TYPE_MES, 1513 .major = 11, 1514 .minor = 0, 1515 .rev = 0, 1516 .funcs = &mes_v11_0_ip_funcs, 1517 }; 1518