1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 62 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 63 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 64 65 #define MES_EOP_SIZE 2048 66 #define GFX_MES_DRAM_SIZE 0x80000 67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 68 69 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 70 #define MES11_HUNG_HQD_INFO_OFFSET 4 71 72 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 73 { 74 struct amdgpu_device *adev = ring->adev; 75 76 if (ring->use_doorbell) { 77 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 78 ring->wptr); 79 WDOORBELL64(ring->doorbell_index, ring->wptr); 80 } else { 81 BUG(); 82 } 83 } 84 85 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 86 { 87 return *ring->rptr_cpu_addr; 88 } 89 90 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 91 { 92 u64 wptr; 93 94 if (ring->use_doorbell) 95 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 96 else 97 BUG(); 98 return wptr; 99 } 100 101 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 102 .type = AMDGPU_RING_TYPE_MES, 103 .align_mask = 1, 104 .nop = 0, 105 .support_64bit_ptrs = true, 106 .get_rptr = mes_v11_0_ring_get_rptr, 107 .get_wptr = mes_v11_0_ring_get_wptr, 108 .set_wptr = mes_v11_0_ring_set_wptr, 109 .insert_nop = amdgpu_ring_insert_nop, 110 }; 111 112 static const char *mes_v11_0_opcodes[] = { 113 "SET_HW_RSRC", 114 "SET_SCHEDULING_CONFIG", 115 "ADD_QUEUE", 116 "REMOVE_QUEUE", 117 "PERFORM_YIELD", 118 "SET_GANG_PRIORITY_LEVEL", 119 "SUSPEND", 120 "RESUME", 121 "RESET", 122 "SET_LOG_BUFFER", 123 "CHANGE_GANG_PRORITY", 124 "QUERY_SCHEDULER_STATUS", 125 "PROGRAM_GDS", 126 "SET_DEBUG_VMID", 127 "MISC", 128 "UPDATE_ROOT_PAGE_TABLE", 129 "AMD_LOG", 130 "unused", 131 "unused", 132 "SET_HW_RSRC_1", 133 }; 134 135 static const char *mes_v11_0_misc_opcodes[] = { 136 "WRITE_REG", 137 "INV_GART", 138 "QUERY_STATUS", 139 "READ_REG", 140 "WAIT_REG_MEM", 141 "SET_SHADER_DEBUGGER", 142 }; 143 144 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 145 { 146 const char *op_str = NULL; 147 148 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 149 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 150 151 return op_str; 152 } 153 154 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 155 { 156 const char *op_str = NULL; 157 158 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 159 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 160 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 161 162 return op_str; 163 } 164 165 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 166 void *pkt, int size, 167 int api_status_off) 168 { 169 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 170 signed long timeout = 2100000; /* 2100 ms */ 171 struct amdgpu_device *adev = mes->adev; 172 struct amdgpu_ring *ring = &mes->ring[0]; 173 struct MES_API_STATUS *api_status; 174 union MESAPI__MISC *x_pkt = pkt; 175 const char *op_str, *misc_op_str; 176 unsigned long flags; 177 u64 status_gpu_addr; 178 u32 seq, status_offset; 179 u64 *status_ptr; 180 signed long r; 181 int ret; 182 183 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 184 return -EINVAL; 185 186 if (amdgpu_emu_mode) { 187 timeout *= 100; 188 } else if (amdgpu_sriov_vf(adev)) { 189 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 190 timeout = 15 * 600 * 1000; 191 } 192 193 ret = amdgpu_device_wb_get(adev, &status_offset); 194 if (ret) 195 return ret; 196 197 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 198 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 199 *status_ptr = 0; 200 201 spin_lock_irqsave(&mes->ring_lock[0], flags); 202 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 203 if (r) 204 goto error_unlock_free; 205 206 seq = ++ring->fence_drv.sync_seq; 207 r = amdgpu_fence_wait_polling(ring, 208 seq - ring->fence_drv.num_fences_mask, 209 timeout); 210 if (r < 1) 211 goto error_undo; 212 213 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 214 api_status->api_completion_fence_addr = status_gpu_addr; 215 api_status->api_completion_fence_value = 1; 216 217 amdgpu_ring_write_multiple(ring, pkt, size / 4); 218 219 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 220 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 221 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 222 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 223 mes_status_pkt.api_status.api_completion_fence_addr = 224 ring->fence_drv.gpu_addr; 225 mes_status_pkt.api_status.api_completion_fence_value = seq; 226 227 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 228 sizeof(mes_status_pkt) / 4); 229 230 amdgpu_ring_commit(ring); 231 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 232 233 op_str = mes_v11_0_get_op_string(x_pkt); 234 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 235 236 if (misc_op_str) 237 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 238 misc_op_str); 239 else if (op_str) 240 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 241 else 242 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 243 x_pkt->header.opcode); 244 245 r = amdgpu_fence_wait_polling(ring, seq, timeout); 246 if (r < 1 || !*status_ptr) { 247 248 if (misc_op_str) 249 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 250 op_str, misc_op_str); 251 else if (op_str) 252 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 253 op_str); 254 else 255 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 256 x_pkt->header.opcode); 257 258 while (halt_if_hws_hang) 259 schedule(); 260 261 r = -ETIMEDOUT; 262 goto error_wb_free; 263 } 264 265 amdgpu_device_wb_free(adev, status_offset); 266 return 0; 267 268 error_undo: 269 dev_err(adev->dev, "MES ring buffer is full.\n"); 270 amdgpu_ring_undo(ring); 271 272 error_unlock_free: 273 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 274 275 error_wb_free: 276 amdgpu_device_wb_free(adev, status_offset); 277 return r; 278 } 279 280 static int convert_to_mes_queue_type(int queue_type) 281 { 282 if (queue_type == AMDGPU_RING_TYPE_GFX) 283 return MES_QUEUE_TYPE_GFX; 284 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 285 return MES_QUEUE_TYPE_COMPUTE; 286 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 287 return MES_QUEUE_TYPE_SDMA; 288 else 289 BUG(); 290 return -1; 291 } 292 293 static int convert_to_mes_priority_level(int priority_level) 294 { 295 switch (priority_level) { 296 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 297 return AMD_PRIORITY_LEVEL_LOW; 298 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 299 default: 300 return AMD_PRIORITY_LEVEL_NORMAL; 301 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 302 return AMD_PRIORITY_LEVEL_MEDIUM; 303 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 304 return AMD_PRIORITY_LEVEL_HIGH; 305 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 306 return AMD_PRIORITY_LEVEL_REALTIME; 307 } 308 } 309 310 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 311 struct mes_add_queue_input *input) 312 { 313 struct amdgpu_device *adev = mes->adev; 314 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 315 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 316 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 317 318 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 319 320 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 321 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 322 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 323 324 mes_add_queue_pkt.process_id = input->process_id; 325 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 326 mes_add_queue_pkt.process_va_start = input->process_va_start; 327 mes_add_queue_pkt.process_va_end = input->process_va_end; 328 mes_add_queue_pkt.process_quantum = input->process_quantum; 329 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 330 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 331 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 332 mes_add_queue_pkt.inprocess_gang_priority = 333 convert_to_mes_priority_level(input->inprocess_gang_priority); 334 mes_add_queue_pkt.gang_global_priority_level = 335 convert_to_mes_priority_level(input->gang_global_priority_level); 336 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 337 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 338 339 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 340 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 341 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 342 else 343 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 344 345 mes_add_queue_pkt.queue_type = 346 convert_to_mes_queue_type(input->queue_type); 347 mes_add_queue_pkt.paging = input->paging; 348 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 349 mes_add_queue_pkt.gws_base = input->gws_base; 350 mes_add_queue_pkt.gws_size = input->gws_size; 351 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 352 mes_add_queue_pkt.tma_addr = input->tma_addr; 353 mes_add_queue_pkt.trap_en = input->trap_en; 354 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 355 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 356 357 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 358 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 359 mes_add_queue_pkt.gds_size = input->queue_size; 360 361 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 362 363 return mes_v11_0_submit_pkt_and_poll_completion(mes, 364 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 365 offsetof(union MESAPI__ADD_QUEUE, api_status)); 366 } 367 368 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 369 struct mes_remove_queue_input *input) 370 { 371 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 372 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 373 374 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 375 376 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 377 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 378 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 379 380 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 381 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 382 383 if (mes_rev >= 0x60) 384 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 385 386 return mes_v11_0_submit_pkt_and_poll_completion(mes, 387 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 388 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 389 } 390 391 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 392 uint32_t me_id, uint32_t pipe_id, 393 uint32_t queue_id, uint32_t vmid) 394 { 395 struct amdgpu_device *adev = mes->adev; 396 uint32_t value, reg; 397 int i, r = 0; 398 399 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 400 401 if (queue_type == AMDGPU_RING_TYPE_GFX) { 402 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 403 me_id, pipe_id, queue_id, vmid); 404 405 mutex_lock(&adev->gfx.reset_sem_mutex); 406 gfx_v11_0_request_gfx_index_mutex(adev, true); 407 /* all se allow writes */ 408 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 409 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 410 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 411 if (pipe_id == 0) 412 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 413 else 414 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 415 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 416 gfx_v11_0_request_gfx_index_mutex(adev, false); 417 mutex_unlock(&adev->gfx.reset_sem_mutex); 418 419 mutex_lock(&adev->srbm_mutex); 420 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 421 /* wait till dequeue take effects */ 422 for (i = 0; i < adev->usec_timeout; i++) { 423 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 424 break; 425 udelay(1); 426 } 427 if (i >= adev->usec_timeout) { 428 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 429 r = -ETIMEDOUT; 430 } 431 432 soc21_grbm_select(adev, 0, 0, 0, 0); 433 mutex_unlock(&adev->srbm_mutex); 434 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 435 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 436 me_id, pipe_id, queue_id); 437 mutex_lock(&adev->srbm_mutex); 438 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 439 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 440 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 441 442 /* wait till dequeue take effects */ 443 for (i = 0; i < adev->usec_timeout; i++) { 444 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 445 break; 446 udelay(1); 447 } 448 if (i >= adev->usec_timeout) { 449 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 450 r = -ETIMEDOUT; 451 } 452 soc21_grbm_select(adev, 0, 0, 0, 0); 453 mutex_unlock(&adev->srbm_mutex); 454 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 455 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 456 me_id, pipe_id, queue_id); 457 switch (me_id) { 458 case 1: 459 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 460 break; 461 case 0: 462 default: 463 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 464 break; 465 } 466 467 value = 1 << queue_id; 468 WREG32(reg, value); 469 /* wait for queue reset done */ 470 for (i = 0; i < adev->usec_timeout; i++) { 471 if (!(RREG32(reg) & value)) 472 break; 473 udelay(1); 474 } 475 if (i >= adev->usec_timeout) { 476 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 477 r = -ETIMEDOUT; 478 } 479 } 480 481 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 482 return r; 483 } 484 485 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 486 struct mes_map_legacy_queue_input *input) 487 { 488 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 489 490 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 491 492 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 493 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 494 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 495 496 mes_add_queue_pkt.pipe_id = input->pipe_id; 497 mes_add_queue_pkt.queue_id = input->queue_id; 498 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 499 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 500 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 501 mes_add_queue_pkt.queue_type = 502 convert_to_mes_queue_type(input->queue_type); 503 mes_add_queue_pkt.map_legacy_kq = 1; 504 505 return mes_v11_0_submit_pkt_and_poll_completion(mes, 506 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 507 offsetof(union MESAPI__ADD_QUEUE, api_status)); 508 } 509 510 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 511 struct mes_unmap_legacy_queue_input *input) 512 { 513 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 514 515 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 516 517 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 518 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 519 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 520 521 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 522 mes_remove_queue_pkt.gang_context_addr = 0; 523 524 mes_remove_queue_pkt.pipe_id = input->pipe_id; 525 mes_remove_queue_pkt.queue_id = input->queue_id; 526 527 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 528 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 529 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 530 mes_remove_queue_pkt.tf_data = 531 lower_32_bits(input->trail_fence_data); 532 } else { 533 mes_remove_queue_pkt.unmap_legacy_queue = 1; 534 mes_remove_queue_pkt.queue_type = 535 convert_to_mes_queue_type(input->queue_type); 536 } 537 538 return mes_v11_0_submit_pkt_and_poll_completion(mes, 539 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 540 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 541 } 542 543 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 544 struct mes_suspend_gang_input *input) 545 { 546 union MESAPI__SUSPEND mes_suspend_gang_pkt; 547 548 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 549 550 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 551 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 552 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 553 554 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 555 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 556 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 557 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 558 559 return mes_v11_0_submit_pkt_and_poll_completion(mes, 560 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 561 offsetof(union MESAPI__SUSPEND, api_status)); 562 } 563 564 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 565 struct mes_resume_gang_input *input) 566 { 567 union MESAPI__RESUME mes_resume_gang_pkt; 568 569 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 570 571 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 572 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 573 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 574 575 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 576 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 577 578 return mes_v11_0_submit_pkt_and_poll_completion(mes, 579 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 580 offsetof(union MESAPI__RESUME, api_status)); 581 } 582 583 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 584 { 585 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 586 587 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 588 589 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 590 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 591 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 592 593 return mes_v11_0_submit_pkt_and_poll_completion(mes, 594 &mes_status_pkt, sizeof(mes_status_pkt), 595 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 596 } 597 598 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 599 struct mes_misc_op_input *input) 600 { 601 union MESAPI__MISC misc_pkt; 602 603 memset(&misc_pkt, 0, sizeof(misc_pkt)); 604 605 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 606 misc_pkt.header.opcode = MES_SCH_API_MISC; 607 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 608 609 switch (input->op) { 610 case MES_MISC_OP_READ_REG: 611 misc_pkt.opcode = MESAPI_MISC__READ_REG; 612 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 613 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 614 break; 615 case MES_MISC_OP_WRITE_REG: 616 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 617 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 618 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 619 break; 620 case MES_MISC_OP_WRM_REG_WAIT: 621 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 622 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 623 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 624 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 625 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 626 misc_pkt.wait_reg_mem.reg_offset2 = 0; 627 break; 628 case MES_MISC_OP_WRM_REG_WR_WAIT: 629 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 630 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 631 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 632 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 633 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 634 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 635 break; 636 case MES_MISC_OP_SET_SHADER_DEBUGGER: 637 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 638 misc_pkt.set_shader_debugger.process_context_addr = 639 input->set_shader_debugger.process_context_addr; 640 misc_pkt.set_shader_debugger.flags.u32all = 641 input->set_shader_debugger.flags.u32all; 642 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 643 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 644 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 645 input->set_shader_debugger.tcp_watch_cntl, 646 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 647 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 648 break; 649 case MES_MISC_OP_CHANGE_CONFIG: 650 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 651 dev_warn_once(mes->adev->dev, 652 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 653 return 0; 654 } 655 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 656 misc_pkt.change_config.opcode = 657 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 658 misc_pkt.change_config.option.bits.limit_single_process = 659 input->change_config.option.limit_single_process; 660 break; 661 662 default: 663 DRM_ERROR("unsupported misc op (%d) \n", input->op); 664 return -EINVAL; 665 } 666 667 return mes_v11_0_submit_pkt_and_poll_completion(mes, 668 &misc_pkt, sizeof(misc_pkt), 669 offsetof(union MESAPI__MISC, api_status)); 670 } 671 672 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 673 { 674 int i; 675 struct amdgpu_device *adev = mes->adev; 676 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 677 678 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 679 680 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 681 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 682 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 683 684 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 685 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 686 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 687 mes_set_hw_res_pkt.paging_vmid = 0; 688 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 689 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 690 mes->query_status_fence_gpu_addr[0]; 691 692 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 693 mes_set_hw_res_pkt.compute_hqd_mask[i] = 694 mes->compute_hqd_mask[i]; 695 696 for (i = 0; i < MAX_GFX_PIPES; i++) 697 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 698 mes->gfx_hqd_mask[i]; 699 700 for (i = 0; i < MAX_SDMA_PIPES; i++) 701 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 702 703 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 704 mes_set_hw_res_pkt.aggregated_doorbells[i] = 705 mes->aggregated_doorbells[i]; 706 707 for (i = 0; i < 5; i++) { 708 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 709 mes_set_hw_res_pkt.mmhub_base[i] = 710 adev->reg_offset[MMHUB_HWIP][0][i]; 711 mes_set_hw_res_pkt.osssys_base[i] = 712 adev->reg_offset[OSSSYS_HWIP][0][i]; 713 } 714 715 mes_set_hw_res_pkt.disable_reset = 1; 716 mes_set_hw_res_pkt.disable_mes_log = 1; 717 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 718 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 719 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 720 mes_set_hw_res_pkt.oversubscription_timer = 50; 721 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) 722 mes_set_hw_res_pkt.enable_lr_compute_wa = 1; 723 else 724 dev_info_once(mes->adev->dev, 725 "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); 726 727 if (amdgpu_mes_log_enable) { 728 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 729 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 730 mes->event_log_gpu_addr; 731 } 732 733 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 734 mes_set_hw_res_pkt.limit_single_process = 1; 735 736 return mes_v11_0_submit_pkt_and_poll_completion(mes, 737 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 738 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 739 } 740 741 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 742 { 743 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 744 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 745 746 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 747 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 748 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 749 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 750 751 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 752 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 753 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 754 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 755 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 756 } 757 758 return mes_v11_0_submit_pkt_and_poll_completion(mes, 759 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 760 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 761 } 762 763 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 764 struct mes_reset_queue_input *input) 765 { 766 union MESAPI__RESET mes_reset_queue_pkt; 767 768 if (input->use_mmio) 769 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 770 input->me_id, input->pipe_id, 771 input->queue_id, input->vmid); 772 773 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 774 775 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 776 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 777 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 778 779 mes_reset_queue_pkt.queue_type = 780 convert_to_mes_queue_type(input->queue_type); 781 782 if (input->legacy_gfx) { 783 mes_reset_queue_pkt.reset_legacy_gfx = 1; 784 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 785 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 786 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 787 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 788 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 789 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 790 } else { 791 mes_reset_queue_pkt.reset_queue_only = 1; 792 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 793 } 794 795 return mes_v11_0_submit_pkt_and_poll_completion(mes, 796 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 797 offsetof(union MESAPI__RESET, api_status)); 798 } 799 800 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 801 struct mes_detect_and_reset_queue_input *input) 802 { 803 union MESAPI__RESET mes_reset_queue_pkt; 804 805 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 806 807 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 808 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 809 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 810 811 mes_reset_queue_pkt.queue_type = 812 convert_to_mes_queue_type(input->queue_type); 813 mes_reset_queue_pkt.doorbell_offset_addr = 814 mes->hung_queue_db_array_gpu_addr; 815 816 if (input->detect_only) 817 mes_reset_queue_pkt.hang_detect_only = 1; 818 else 819 mes_reset_queue_pkt.hang_detect_then_reset = 1; 820 821 return mes_v11_0_submit_pkt_and_poll_completion(mes, 822 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 823 offsetof(union MESAPI__RESET, api_status)); 824 } 825 826 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 827 .add_hw_queue = mes_v11_0_add_hw_queue, 828 .remove_hw_queue = mes_v11_0_remove_hw_queue, 829 .map_legacy_queue = mes_v11_0_map_legacy_queue, 830 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 831 .suspend_gang = mes_v11_0_suspend_gang, 832 .resume_gang = mes_v11_0_resume_gang, 833 .misc_op = mes_v11_0_misc_op, 834 .reset_hw_queue = mes_v11_0_reset_hw_queue, 835 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 836 }; 837 838 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 839 enum amdgpu_mes_pipe pipe) 840 { 841 int r; 842 const struct mes_firmware_header_v1_0 *mes_hdr; 843 const __le32 *fw_data; 844 unsigned fw_size; 845 846 mes_hdr = (const struct mes_firmware_header_v1_0 *) 847 adev->mes.fw[pipe]->data; 848 849 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 850 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 851 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 852 853 r = amdgpu_bo_create_reserved(adev, fw_size, 854 PAGE_SIZE, 855 AMDGPU_GEM_DOMAIN_VRAM | 856 AMDGPU_GEM_DOMAIN_GTT, 857 &adev->mes.ucode_fw_obj[pipe], 858 &adev->mes.ucode_fw_gpu_addr[pipe], 859 (void **)&adev->mes.ucode_fw_ptr[pipe]); 860 if (r) { 861 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 862 return r; 863 } 864 865 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 866 867 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 868 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 869 870 return 0; 871 } 872 873 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 874 enum amdgpu_mes_pipe pipe) 875 { 876 int r; 877 const struct mes_firmware_header_v1_0 *mes_hdr; 878 const __le32 *fw_data; 879 unsigned fw_size; 880 881 mes_hdr = (const struct mes_firmware_header_v1_0 *) 882 adev->mes.fw[pipe]->data; 883 884 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 885 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 886 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 887 888 if (fw_size > GFX_MES_DRAM_SIZE) { 889 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 890 pipe, fw_size, GFX_MES_DRAM_SIZE); 891 return -EINVAL; 892 } 893 894 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 895 64 * 1024, 896 AMDGPU_GEM_DOMAIN_VRAM | 897 AMDGPU_GEM_DOMAIN_GTT, 898 &adev->mes.data_fw_obj[pipe], 899 &adev->mes.data_fw_gpu_addr[pipe], 900 (void **)&adev->mes.data_fw_ptr[pipe]); 901 if (r) { 902 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 903 return r; 904 } 905 906 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 907 908 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 909 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 910 911 return 0; 912 } 913 914 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 915 enum amdgpu_mes_pipe pipe) 916 { 917 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 918 &adev->mes.data_fw_gpu_addr[pipe], 919 (void **)&adev->mes.data_fw_ptr[pipe]); 920 921 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 922 &adev->mes.ucode_fw_gpu_addr[pipe], 923 (void **)&adev->mes.ucode_fw_ptr[pipe]); 924 } 925 926 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 927 { 928 int pipe; 929 930 /* return early if we have already fetched these */ 931 if (adev->mes.sched_version && adev->mes.kiq_version) 932 return; 933 934 /* get MES scheduler/KIQ versions */ 935 mutex_lock(&adev->srbm_mutex); 936 937 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 938 soc21_grbm_select(adev, 3, pipe, 0, 0); 939 940 if (pipe == AMDGPU_MES_SCHED_PIPE) 941 adev->mes.sched_version = 942 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 943 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 944 adev->mes.kiq_version = 945 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 946 } 947 948 soc21_grbm_select(adev, 0, 0, 0, 0); 949 mutex_unlock(&adev->srbm_mutex); 950 } 951 952 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 953 { 954 uint64_t ucode_addr; 955 uint32_t pipe, data = 0; 956 957 if (enable) { 958 if (amdgpu_mes_log_enable) { 959 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 960 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 961 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 962 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 963 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 964 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 965 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 966 } 967 968 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 969 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 970 data = REG_SET_FIELD(data, CP_MES_CNTL, 971 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 972 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 973 974 mutex_lock(&adev->srbm_mutex); 975 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 976 if (!adev->enable_mes_kiq && 977 pipe == AMDGPU_MES_KIQ_PIPE) 978 continue; 979 980 soc21_grbm_select(adev, 3, pipe, 0, 0); 981 982 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 983 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 984 lower_32_bits(ucode_addr)); 985 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 986 upper_32_bits(ucode_addr)); 987 } 988 soc21_grbm_select(adev, 0, 0, 0, 0); 989 mutex_unlock(&adev->srbm_mutex); 990 991 /* unhalt MES and activate pipe0 */ 992 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 993 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 994 adev->enable_mes_kiq ? 1 : 0); 995 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 996 997 if (amdgpu_emu_mode) 998 msleep(100); 999 else 1000 udelay(500); 1001 } else { 1002 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1003 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1004 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1005 data = REG_SET_FIELD(data, CP_MES_CNTL, 1006 MES_INVALIDATE_ICACHE, 1); 1007 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1008 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1009 adev->enable_mes_kiq ? 1 : 0); 1010 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1011 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1012 } 1013 } 1014 1015 /* This function is for backdoor MES firmware */ 1016 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1017 enum amdgpu_mes_pipe pipe, bool prime_icache) 1018 { 1019 int r; 1020 uint32_t data; 1021 uint64_t ucode_addr; 1022 1023 mes_v11_0_enable(adev, false); 1024 1025 if (!adev->mes.fw[pipe]) 1026 return -EINVAL; 1027 1028 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1029 if (r) 1030 return r; 1031 1032 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1033 if (r) { 1034 mes_v11_0_free_ucode_buffers(adev, pipe); 1035 return r; 1036 } 1037 1038 mutex_lock(&adev->srbm_mutex); 1039 /* me=3, pipe=0, queue=0 */ 1040 soc21_grbm_select(adev, 3, pipe, 0, 0); 1041 1042 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1043 1044 /* set ucode start address */ 1045 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1046 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1047 lower_32_bits(ucode_addr)); 1048 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1049 upper_32_bits(ucode_addr)); 1050 1051 /* set ucode fimrware address */ 1052 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1053 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1054 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1055 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1056 1057 /* set ucode instruction cache boundary to 2M-1 */ 1058 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1059 1060 /* set ucode data firmware address */ 1061 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1062 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1063 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1064 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1065 1066 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1067 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1068 1069 if (prime_icache) { 1070 /* invalidate ICACHE */ 1071 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1072 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1073 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1074 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1075 1076 /* prime the ICACHE. */ 1077 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1078 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1079 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1080 } 1081 1082 soc21_grbm_select(adev, 0, 0, 0, 0); 1083 mutex_unlock(&adev->srbm_mutex); 1084 1085 return 0; 1086 } 1087 1088 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1089 enum amdgpu_mes_pipe pipe) 1090 { 1091 int r; 1092 u32 *eop; 1093 1094 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1095 AMDGPU_GEM_DOMAIN_GTT, 1096 &adev->mes.eop_gpu_obj[pipe], 1097 &adev->mes.eop_gpu_addr[pipe], 1098 (void **)&eop); 1099 if (r) { 1100 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1101 return r; 1102 } 1103 1104 memset(eop, 0, 1105 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1106 1107 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1108 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1109 1110 return 0; 1111 } 1112 1113 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1114 { 1115 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1116 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1117 uint32_t tmp; 1118 1119 memset(mqd, 0, sizeof(*mqd)); 1120 1121 mqd->header = 0xC0310800; 1122 mqd->compute_pipelinestat_enable = 0x00000001; 1123 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1124 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1125 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1126 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1127 mqd->compute_misc_reserved = 0x00000007; 1128 1129 eop_base_addr = ring->eop_gpu_addr >> 8; 1130 1131 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1132 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1133 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1134 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1135 1136 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1137 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1138 mqd->cp_hqd_eop_control = tmp; 1139 1140 /* disable the queue if it's active */ 1141 ring->wptr = 0; 1142 mqd->cp_hqd_pq_rptr = 0; 1143 mqd->cp_hqd_pq_wptr_lo = 0; 1144 mqd->cp_hqd_pq_wptr_hi = 0; 1145 1146 /* set the pointer to the MQD */ 1147 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1148 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1149 1150 /* set MQD vmid to 0 */ 1151 tmp = regCP_MQD_CONTROL_DEFAULT; 1152 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1153 mqd->cp_mqd_control = tmp; 1154 1155 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1156 hqd_gpu_addr = ring->gpu_addr >> 8; 1157 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1158 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1159 1160 /* set the wb address whether it's enabled or not */ 1161 wb_gpu_addr = ring->rptr_gpu_addr; 1162 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1163 mqd->cp_hqd_pq_rptr_report_addr_hi = 1164 upper_32_bits(wb_gpu_addr) & 0xffff; 1165 1166 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1167 wb_gpu_addr = ring->wptr_gpu_addr; 1168 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1169 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1170 1171 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1172 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1173 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1174 (order_base_2(ring->ring_size / 4) - 1)); 1175 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1176 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1182 mqd->cp_hqd_pq_control = tmp; 1183 1184 /* enable doorbell */ 1185 tmp = 0; 1186 if (ring->use_doorbell) { 1187 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1188 DOORBELL_OFFSET, ring->doorbell_index); 1189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1190 DOORBELL_EN, 1); 1191 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1192 DOORBELL_SOURCE, 0); 1193 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1194 DOORBELL_HIT, 0); 1195 } else 1196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1197 DOORBELL_EN, 0); 1198 mqd->cp_hqd_pq_doorbell_control = tmp; 1199 1200 mqd->cp_hqd_vmid = 0; 1201 /* activate the queue */ 1202 mqd->cp_hqd_active = 1; 1203 1204 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1205 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1206 PRELOAD_SIZE, 0x55); 1207 mqd->cp_hqd_persistent_state = tmp; 1208 1209 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1210 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1211 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1212 1213 amdgpu_device_flush_hdp(ring->adev, NULL); 1214 return 0; 1215 } 1216 1217 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1218 { 1219 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1220 struct amdgpu_device *adev = ring->adev; 1221 uint32_t data = 0; 1222 1223 mutex_lock(&adev->srbm_mutex); 1224 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1225 1226 /* set CP_HQD_VMID.VMID = 0. */ 1227 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1228 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1229 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1230 1231 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1232 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1233 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1234 DOORBELL_EN, 0); 1235 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1236 1237 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1238 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1239 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1240 1241 /* set CP_MQD_CONTROL.VMID=0 */ 1242 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1243 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1244 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1245 1246 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1247 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1248 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1249 1250 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1251 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1252 mqd->cp_hqd_pq_rptr_report_addr_lo); 1253 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1254 mqd->cp_hqd_pq_rptr_report_addr_hi); 1255 1256 /* set CP_HQD_PQ_CONTROL */ 1257 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1258 1259 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1260 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1261 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1262 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1263 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1264 1265 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1266 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1267 mqd->cp_hqd_pq_doorbell_control); 1268 1269 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1270 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1271 1272 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1273 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1274 1275 soc21_grbm_select(adev, 0, 0, 0, 0); 1276 mutex_unlock(&adev->srbm_mutex); 1277 } 1278 1279 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1280 { 1281 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1282 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1283 int r; 1284 1285 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1286 return -EINVAL; 1287 1288 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1289 if (r) { 1290 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1291 return r; 1292 } 1293 1294 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1295 1296 return amdgpu_ring_test_helper(kiq_ring); 1297 } 1298 1299 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1300 enum amdgpu_mes_pipe pipe) 1301 { 1302 struct amdgpu_ring *ring; 1303 int r; 1304 1305 if (pipe == AMDGPU_MES_KIQ_PIPE) 1306 ring = &adev->gfx.kiq[0].ring; 1307 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1308 ring = &adev->mes.ring[0]; 1309 else 1310 BUG(); 1311 1312 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1313 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1314 *(ring->wptr_cpu_addr) = 0; 1315 *(ring->rptr_cpu_addr) = 0; 1316 amdgpu_ring_clear_ring(ring); 1317 } 1318 1319 r = mes_v11_0_mqd_init(ring); 1320 if (r) 1321 return r; 1322 1323 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1324 r = mes_v11_0_kiq_enable_queue(adev); 1325 if (r) 1326 return r; 1327 } else { 1328 mes_v11_0_queue_init_register(ring); 1329 } 1330 1331 return 0; 1332 } 1333 1334 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1335 { 1336 struct amdgpu_ring *ring; 1337 1338 ring = &adev->mes.ring[0]; 1339 1340 ring->funcs = &mes_v11_0_ring_funcs; 1341 1342 ring->me = 3; 1343 ring->pipe = 0; 1344 ring->queue = 0; 1345 1346 ring->ring_obj = NULL; 1347 ring->use_doorbell = true; 1348 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1349 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1350 ring->no_scheduler = true; 1351 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1352 1353 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1354 AMDGPU_RING_PRIO_DEFAULT, NULL); 1355 } 1356 1357 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1358 { 1359 struct amdgpu_ring *ring; 1360 1361 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1362 1363 ring = &adev->gfx.kiq[0].ring; 1364 1365 ring->me = 3; 1366 ring->pipe = 1; 1367 ring->queue = 0; 1368 1369 ring->adev = NULL; 1370 ring->ring_obj = NULL; 1371 ring->use_doorbell = true; 1372 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1373 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1374 ring->no_scheduler = true; 1375 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1376 ring->me, ring->pipe, ring->queue); 1377 1378 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1379 AMDGPU_RING_PRIO_DEFAULT, NULL); 1380 } 1381 1382 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1383 enum amdgpu_mes_pipe pipe) 1384 { 1385 int r, mqd_size = sizeof(struct v11_compute_mqd); 1386 struct amdgpu_ring *ring; 1387 1388 if (pipe == AMDGPU_MES_KIQ_PIPE) 1389 ring = &adev->gfx.kiq[0].ring; 1390 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1391 ring = &adev->mes.ring[0]; 1392 else 1393 BUG(); 1394 1395 if (ring->mqd_obj) 1396 return 0; 1397 1398 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1399 AMDGPU_GEM_DOMAIN_VRAM | 1400 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1401 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1402 if (r) { 1403 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1404 return r; 1405 } 1406 1407 memset(ring->mqd_ptr, 0, mqd_size); 1408 1409 /* prepare MQD backup */ 1410 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1411 if (!adev->mes.mqd_backup[pipe]) { 1412 dev_warn(adev->dev, 1413 "no memory to create MQD backup for ring %s\n", 1414 ring->name); 1415 return -ENOMEM; 1416 } 1417 1418 return 0; 1419 } 1420 1421 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1422 { 1423 struct amdgpu_device *adev = ip_block->adev; 1424 int pipe, r, bo_size; 1425 1426 adev->mes.funcs = &mes_v11_0_funcs; 1427 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1428 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1429 1430 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1431 1432 r = amdgpu_mes_init(adev); 1433 if (r) 1434 return r; 1435 1436 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1437 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1438 continue; 1439 1440 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1441 if (r) 1442 return r; 1443 1444 r = mes_v11_0_mqd_sw_init(adev, pipe); 1445 if (r) 1446 return r; 1447 } 1448 1449 if (adev->enable_mes_kiq) { 1450 r = mes_v11_0_kiq_ring_init(adev); 1451 if (r) 1452 return r; 1453 } 1454 1455 r = mes_v11_0_ring_init(adev); 1456 if (r) 1457 return r; 1458 1459 bo_size = AMDGPU_GPU_PAGE_SIZE; 1460 if (amdgpu_sriov_is_mes_info_enable(adev)) 1461 bo_size += MES11_HW_RESOURCE_1_SIZE; 1462 1463 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1464 r = amdgpu_bo_create_kernel(adev, 1465 bo_size, 1466 PAGE_SIZE, 1467 AMDGPU_GEM_DOMAIN_VRAM, 1468 &adev->mes.resource_1[0], 1469 &adev->mes.resource_1_gpu_addr[0], 1470 &adev->mes.resource_1_addr[0]); 1471 if (r) { 1472 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1473 return r; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1480 { 1481 struct amdgpu_device *adev = ip_block->adev; 1482 int pipe; 1483 1484 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1485 &adev->mes.resource_1_addr[0]); 1486 1487 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1488 kfree(adev->mes.mqd_backup[pipe]); 1489 1490 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1491 &adev->mes.eop_gpu_addr[pipe], 1492 NULL); 1493 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1494 } 1495 1496 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1497 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1498 &adev->gfx.kiq[0].ring.mqd_ptr); 1499 1500 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1501 &adev->mes.ring[0].mqd_gpu_addr, 1502 &adev->mes.ring[0].mqd_ptr); 1503 1504 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1505 amdgpu_ring_fini(&adev->mes.ring[0]); 1506 1507 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1508 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1509 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1510 } 1511 1512 amdgpu_mes_fini(adev); 1513 return 0; 1514 } 1515 1516 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1517 { 1518 uint32_t data; 1519 int i; 1520 struct amdgpu_device *adev = ring->adev; 1521 1522 mutex_lock(&adev->srbm_mutex); 1523 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1524 1525 /* disable the queue if it's active */ 1526 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1527 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1528 for (i = 0; i < adev->usec_timeout; i++) { 1529 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1530 break; 1531 udelay(1); 1532 } 1533 } 1534 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1535 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1536 DOORBELL_EN, 0); 1537 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1538 DOORBELL_HIT, 1); 1539 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1540 1541 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1542 1543 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1544 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1545 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1546 1547 soc21_grbm_select(adev, 0, 0, 0, 0); 1548 mutex_unlock(&adev->srbm_mutex); 1549 } 1550 1551 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1552 { 1553 uint32_t tmp; 1554 struct amdgpu_device *adev = ring->adev; 1555 1556 /* tell RLC which is KIQ queue */ 1557 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1558 tmp &= 0xffffff00; 1559 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1560 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1561 } 1562 1563 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1564 { 1565 uint32_t tmp; 1566 1567 /* tell RLC which is KIQ dequeue */ 1568 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1569 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1570 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1571 } 1572 1573 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1574 { 1575 int r = 0; 1576 struct amdgpu_ip_block *ip_block; 1577 1578 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1579 1580 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1581 if (r) { 1582 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1583 return r; 1584 } 1585 1586 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1587 if (r) { 1588 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1589 return r; 1590 } 1591 1592 } 1593 1594 mes_v11_0_enable(adev, true); 1595 1596 mes_v11_0_get_fw_version(adev); 1597 1598 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1599 1600 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1601 if (unlikely(!ip_block)) { 1602 dev_err(adev->dev, "Failed to get MES handle\n"); 1603 return -EINVAL; 1604 } 1605 1606 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1607 if (r) 1608 goto failure; 1609 1610 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1611 adev->mes.enable_legacy_queue_map = true; 1612 else 1613 adev->mes.enable_legacy_queue_map = false; 1614 1615 if (adev->mes.enable_legacy_queue_map) { 1616 r = mes_v11_0_hw_init(ip_block); 1617 if (r) 1618 goto failure; 1619 } 1620 1621 return r; 1622 1623 failure: 1624 mes_v11_0_hw_fini(ip_block); 1625 return r; 1626 } 1627 1628 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1629 { 1630 if (adev->mes.ring[0].sched.ready) { 1631 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1632 adev->mes.ring[0].sched.ready = false; 1633 } 1634 1635 if (amdgpu_sriov_vf(adev)) { 1636 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1637 mes_v11_0_kiq_clear(adev); 1638 } 1639 1640 mes_v11_0_enable(adev, false); 1641 1642 return 0; 1643 } 1644 1645 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1646 { 1647 int r; 1648 struct amdgpu_device *adev = ip_block->adev; 1649 1650 if (adev->mes.ring[0].sched.ready) 1651 goto out; 1652 1653 if (!adev->enable_mes_kiq) { 1654 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1655 r = mes_v11_0_load_microcode(adev, 1656 AMDGPU_MES_SCHED_PIPE, true); 1657 if (r) { 1658 DRM_ERROR("failed to MES fw, r=%d\n", r); 1659 return r; 1660 } 1661 } 1662 1663 mes_v11_0_enable(adev, true); 1664 } 1665 1666 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1667 if (r) 1668 goto failure; 1669 1670 r = mes_v11_0_set_hw_resources(&adev->mes); 1671 if (r) 1672 goto failure; 1673 1674 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) { 1675 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1676 if (r) { 1677 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1678 goto failure; 1679 } 1680 } 1681 1682 r = mes_v11_0_query_sched_status(&adev->mes); 1683 if (r) { 1684 DRM_ERROR("MES is busy\n"); 1685 goto failure; 1686 } 1687 1688 r = amdgpu_mes_update_enforce_isolation(adev); 1689 if (r) 1690 goto failure; 1691 1692 out: 1693 /* 1694 * Disable KIQ ring usage from the driver once MES is enabled. 1695 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1696 * with MES enabled. 1697 */ 1698 adev->gfx.kiq[0].ring.sched.ready = false; 1699 adev->mes.ring[0].sched.ready = true; 1700 1701 return 0; 1702 1703 failure: 1704 mes_v11_0_hw_fini(ip_block); 1705 return r; 1706 } 1707 1708 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1709 { 1710 return 0; 1711 } 1712 1713 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1714 { 1715 return mes_v11_0_hw_fini(ip_block); 1716 } 1717 1718 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1719 { 1720 return mes_v11_0_hw_init(ip_block); 1721 } 1722 1723 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1724 { 1725 struct amdgpu_device *adev = ip_block->adev; 1726 int pipe, r; 1727 1728 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1729 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1730 1731 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1732 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1733 continue; 1734 r = amdgpu_mes_init_microcode(adev, pipe); 1735 if (r) 1736 return r; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1743 .name = "mes_v11_0", 1744 .early_init = mes_v11_0_early_init, 1745 .late_init = NULL, 1746 .sw_init = mes_v11_0_sw_init, 1747 .sw_fini = mes_v11_0_sw_fini, 1748 .hw_init = mes_v11_0_hw_init, 1749 .hw_fini = mes_v11_0_hw_fini, 1750 .suspend = mes_v11_0_suspend, 1751 .resume = mes_v11_0_resume, 1752 }; 1753 1754 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1755 .type = AMD_IP_BLOCK_TYPE_MES, 1756 .major = 11, 1757 .minor = 0, 1758 .rev = 0, 1759 .funcs = &mes_v11_0_ip_funcs, 1760 }; 1761