1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin"); 67 68 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 69 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 72 73 #define MES_EOP_SIZE 2048 74 #define GFX_MES_DRAM_SIZE 0x80000 75 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 76 77 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 78 #define MES11_HUNG_HQD_INFO_OFFSET 4 79 80 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 81 { 82 struct amdgpu_device *adev = ring->adev; 83 84 if (ring->use_doorbell) { 85 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 86 ring->wptr); 87 WDOORBELL64(ring->doorbell_index, ring->wptr); 88 } else { 89 BUG(); 90 } 91 } 92 93 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 94 { 95 return *ring->rptr_cpu_addr; 96 } 97 98 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 99 { 100 u64 wptr; 101 102 if (ring->use_doorbell) 103 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 104 else 105 BUG(); 106 return wptr; 107 } 108 109 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 110 .type = AMDGPU_RING_TYPE_MES, 111 .align_mask = 1, 112 .nop = 0, 113 .support_64bit_ptrs = true, 114 .get_rptr = mes_v11_0_ring_get_rptr, 115 .get_wptr = mes_v11_0_ring_get_wptr, 116 .set_wptr = mes_v11_0_ring_set_wptr, 117 .insert_nop = amdgpu_ring_insert_nop, 118 }; 119 120 static const char *mes_v11_0_opcodes[] = { 121 "SET_HW_RSRC", 122 "SET_SCHEDULING_CONFIG", 123 "ADD_QUEUE", 124 "REMOVE_QUEUE", 125 "PERFORM_YIELD", 126 "SET_GANG_PRIORITY_LEVEL", 127 "SUSPEND", 128 "RESUME", 129 "RESET", 130 "SET_LOG_BUFFER", 131 "CHANGE_GANG_PRORITY", 132 "QUERY_SCHEDULER_STATUS", 133 "PROGRAM_GDS", 134 "SET_DEBUG_VMID", 135 "MISC", 136 "UPDATE_ROOT_PAGE_TABLE", 137 "AMD_LOG", 138 "unused", 139 "unused", 140 "SET_HW_RSRC_1", 141 }; 142 143 static const char *mes_v11_0_misc_opcodes[] = { 144 "WRITE_REG", 145 "INV_GART", 146 "QUERY_STATUS", 147 "READ_REG", 148 "WAIT_REG_MEM", 149 "SET_SHADER_DEBUGGER", 150 }; 151 152 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 153 { 154 const char *op_str = NULL; 155 156 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 157 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 158 159 return op_str; 160 } 161 162 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 163 { 164 const char *op_str = NULL; 165 166 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 167 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 168 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 169 170 return op_str; 171 } 172 173 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 174 void *pkt, int size, 175 int api_status_off) 176 { 177 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 178 signed long timeout = 2100000; /* 2100 ms */ 179 struct amdgpu_device *adev = mes->adev; 180 struct amdgpu_ring *ring = &mes->ring[0]; 181 struct MES_API_STATUS *api_status; 182 union MESAPI__MISC *x_pkt = pkt; 183 const char *op_str, *misc_op_str; 184 unsigned long flags; 185 u64 status_gpu_addr; 186 u32 seq, status_offset; 187 u64 *status_ptr; 188 signed long r; 189 int ret; 190 191 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 192 return -EINVAL; 193 194 if (amdgpu_emu_mode) { 195 timeout *= 100; 196 } else if (amdgpu_sriov_vf(adev)) { 197 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 198 timeout = 15 * 600 * 1000; 199 } 200 201 ret = amdgpu_device_wb_get(adev, &status_offset); 202 if (ret) 203 return ret; 204 205 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 206 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 207 *status_ptr = 0; 208 209 spin_lock_irqsave(&mes->ring_lock[0], flags); 210 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 211 if (r) 212 goto error_unlock_free; 213 214 seq = ++ring->fence_drv.sync_seq; 215 r = amdgpu_fence_wait_polling(ring, 216 seq - ring->fence_drv.num_fences_mask, 217 timeout); 218 if (r < 1) 219 goto error_undo; 220 221 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 222 api_status->api_completion_fence_addr = status_gpu_addr; 223 api_status->api_completion_fence_value = 1; 224 225 amdgpu_ring_write_multiple(ring, pkt, size / 4); 226 227 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 228 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 229 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 230 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 231 mes_status_pkt.api_status.api_completion_fence_addr = 232 ring->fence_drv.gpu_addr; 233 mes_status_pkt.api_status.api_completion_fence_value = seq; 234 235 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 236 sizeof(mes_status_pkt) / 4); 237 238 amdgpu_ring_commit(ring); 239 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 240 241 op_str = mes_v11_0_get_op_string(x_pkt); 242 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 243 244 if (misc_op_str) 245 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 246 misc_op_str); 247 else if (op_str) 248 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 249 else 250 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 251 x_pkt->header.opcode); 252 253 r = amdgpu_fence_wait_polling(ring, seq, timeout); 254 if (r < 1 || !*status_ptr) { 255 256 if (misc_op_str) 257 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 258 op_str, misc_op_str); 259 else if (op_str) 260 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 261 op_str); 262 else 263 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 264 x_pkt->header.opcode); 265 266 while (halt_if_hws_hang) 267 schedule(); 268 269 r = -ETIMEDOUT; 270 goto error_wb_free; 271 } 272 273 amdgpu_device_wb_free(adev, status_offset); 274 return 0; 275 276 error_undo: 277 dev_err(adev->dev, "MES ring buffer is full.\n"); 278 amdgpu_ring_undo(ring); 279 280 error_unlock_free: 281 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 282 283 error_wb_free: 284 amdgpu_device_wb_free(adev, status_offset); 285 return r; 286 } 287 288 static int convert_to_mes_queue_type(int queue_type) 289 { 290 if (queue_type == AMDGPU_RING_TYPE_GFX) 291 return MES_QUEUE_TYPE_GFX; 292 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 293 return MES_QUEUE_TYPE_COMPUTE; 294 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 295 return MES_QUEUE_TYPE_SDMA; 296 else 297 BUG(); 298 return -1; 299 } 300 301 static int convert_to_mes_priority_level(int priority_level) 302 { 303 switch (priority_level) { 304 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 305 return AMD_PRIORITY_LEVEL_LOW; 306 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 307 default: 308 return AMD_PRIORITY_LEVEL_NORMAL; 309 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 310 return AMD_PRIORITY_LEVEL_MEDIUM; 311 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 312 return AMD_PRIORITY_LEVEL_HIGH; 313 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 314 return AMD_PRIORITY_LEVEL_REALTIME; 315 } 316 } 317 318 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 319 struct mes_add_queue_input *input) 320 { 321 struct amdgpu_device *adev = mes->adev; 322 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 323 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 324 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 325 326 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 327 328 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 329 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 330 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 331 332 mes_add_queue_pkt.process_id = input->process_id; 333 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 334 mes_add_queue_pkt.process_va_start = input->process_va_start; 335 mes_add_queue_pkt.process_va_end = input->process_va_end; 336 mes_add_queue_pkt.process_quantum = input->process_quantum; 337 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 338 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 339 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 340 mes_add_queue_pkt.inprocess_gang_priority = 341 convert_to_mes_priority_level(input->inprocess_gang_priority); 342 mes_add_queue_pkt.gang_global_priority_level = 343 convert_to_mes_priority_level(input->gang_global_priority_level); 344 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 345 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 346 347 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 348 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 349 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 350 else 351 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 352 353 mes_add_queue_pkt.queue_type = 354 convert_to_mes_queue_type(input->queue_type); 355 mes_add_queue_pkt.paging = input->paging; 356 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 357 mes_add_queue_pkt.gws_base = input->gws_base; 358 mes_add_queue_pkt.gws_size = input->gws_size; 359 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 360 mes_add_queue_pkt.tma_addr = input->tma_addr; 361 mes_add_queue_pkt.trap_en = input->trap_en; 362 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 363 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 364 365 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 366 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 367 mes_add_queue_pkt.gds_size = input->queue_size; 368 369 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 370 371 return mes_v11_0_submit_pkt_and_poll_completion(mes, 372 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 373 offsetof(union MESAPI__ADD_QUEUE, api_status)); 374 } 375 376 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 377 struct mes_remove_queue_input *input) 378 { 379 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 380 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 381 382 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 383 384 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 385 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 386 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 387 388 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 389 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 390 391 if (mes_rev >= 0x60) 392 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 393 394 return mes_v11_0_submit_pkt_and_poll_completion(mes, 395 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 396 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 397 } 398 399 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 400 uint32_t me_id, uint32_t pipe_id, 401 uint32_t queue_id, uint32_t vmid) 402 { 403 struct amdgpu_device *adev = mes->adev; 404 uint32_t value, reg; 405 int i, r = 0; 406 407 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 408 409 if (queue_type == AMDGPU_RING_TYPE_GFX) { 410 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 411 me_id, pipe_id, queue_id, vmid); 412 413 mutex_lock(&adev->gfx.reset_sem_mutex); 414 gfx_v11_0_request_gfx_index_mutex(adev, true); 415 /* all se allow writes */ 416 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 417 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 418 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 419 if (pipe_id == 0) 420 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 421 else 422 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 423 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 424 gfx_v11_0_request_gfx_index_mutex(adev, false); 425 mutex_unlock(&adev->gfx.reset_sem_mutex); 426 427 mutex_lock(&adev->srbm_mutex); 428 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 429 /* wait till dequeue take effects */ 430 for (i = 0; i < adev->usec_timeout; i++) { 431 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 432 break; 433 udelay(1); 434 } 435 if (i >= adev->usec_timeout) { 436 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 437 r = -ETIMEDOUT; 438 } 439 440 soc21_grbm_select(adev, 0, 0, 0, 0); 441 mutex_unlock(&adev->srbm_mutex); 442 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 443 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 444 me_id, pipe_id, queue_id); 445 mutex_lock(&adev->srbm_mutex); 446 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 447 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 448 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 449 450 /* wait till dequeue take effects */ 451 for (i = 0; i < adev->usec_timeout; i++) { 452 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 453 break; 454 udelay(1); 455 } 456 if (i >= adev->usec_timeout) { 457 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 458 r = -ETIMEDOUT; 459 } 460 soc21_grbm_select(adev, 0, 0, 0, 0); 461 mutex_unlock(&adev->srbm_mutex); 462 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 463 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 464 me_id, pipe_id, queue_id); 465 switch (me_id) { 466 case 1: 467 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 468 break; 469 case 0: 470 default: 471 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 472 break; 473 } 474 475 value = 1 << queue_id; 476 WREG32(reg, value); 477 /* wait for queue reset done */ 478 for (i = 0; i < adev->usec_timeout; i++) { 479 if (!(RREG32(reg) & value)) 480 break; 481 udelay(1); 482 } 483 if (i >= adev->usec_timeout) { 484 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 485 r = -ETIMEDOUT; 486 } 487 } 488 489 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 490 return r; 491 } 492 493 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 494 struct mes_map_legacy_queue_input *input) 495 { 496 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 497 498 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 499 500 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 501 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 502 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 503 504 mes_add_queue_pkt.pipe_id = input->pipe_id; 505 mes_add_queue_pkt.queue_id = input->queue_id; 506 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 507 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 508 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 509 mes_add_queue_pkt.queue_type = 510 convert_to_mes_queue_type(input->queue_type); 511 mes_add_queue_pkt.map_legacy_kq = 1; 512 513 return mes_v11_0_submit_pkt_and_poll_completion(mes, 514 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 515 offsetof(union MESAPI__ADD_QUEUE, api_status)); 516 } 517 518 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 519 struct mes_unmap_legacy_queue_input *input) 520 { 521 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 522 523 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 524 525 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 526 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 527 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 528 529 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 530 mes_remove_queue_pkt.gang_context_addr = 0; 531 532 mes_remove_queue_pkt.pipe_id = input->pipe_id; 533 mes_remove_queue_pkt.queue_id = input->queue_id; 534 535 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 536 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 537 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 538 mes_remove_queue_pkt.tf_data = 539 lower_32_bits(input->trail_fence_data); 540 } else { 541 mes_remove_queue_pkt.unmap_legacy_queue = 1; 542 mes_remove_queue_pkt.queue_type = 543 convert_to_mes_queue_type(input->queue_type); 544 } 545 546 return mes_v11_0_submit_pkt_and_poll_completion(mes, 547 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 548 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 549 } 550 551 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 552 struct mes_suspend_gang_input *input) 553 { 554 union MESAPI__SUSPEND mes_suspend_gang_pkt; 555 556 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 557 558 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 559 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 560 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 561 562 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 563 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 564 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 565 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 566 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 567 568 return mes_v11_0_submit_pkt_and_poll_completion(mes, 569 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 570 offsetof(union MESAPI__SUSPEND, api_status)); 571 } 572 573 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 574 struct mes_resume_gang_input *input) 575 { 576 union MESAPI__RESUME mes_resume_gang_pkt; 577 578 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 579 580 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 581 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 582 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 583 584 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 585 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 586 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 587 588 return mes_v11_0_submit_pkt_and_poll_completion(mes, 589 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 590 offsetof(union MESAPI__RESUME, api_status)); 591 } 592 593 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 594 { 595 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 596 597 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 598 599 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 600 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 601 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 602 603 return mes_v11_0_submit_pkt_and_poll_completion(mes, 604 &mes_status_pkt, sizeof(mes_status_pkt), 605 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 606 } 607 608 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 609 struct mes_misc_op_input *input) 610 { 611 union MESAPI__MISC misc_pkt; 612 613 memset(&misc_pkt, 0, sizeof(misc_pkt)); 614 615 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 616 misc_pkt.header.opcode = MES_SCH_API_MISC; 617 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 618 619 switch (input->op) { 620 case MES_MISC_OP_READ_REG: 621 misc_pkt.opcode = MESAPI_MISC__READ_REG; 622 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 623 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 624 break; 625 case MES_MISC_OP_WRITE_REG: 626 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 627 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 628 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 629 break; 630 case MES_MISC_OP_WRM_REG_WAIT: 631 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 632 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 633 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 634 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 635 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 636 misc_pkt.wait_reg_mem.reg_offset2 = 0; 637 break; 638 case MES_MISC_OP_WRM_REG_WR_WAIT: 639 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 640 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 641 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 642 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 643 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 644 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 645 break; 646 case MES_MISC_OP_SET_SHADER_DEBUGGER: 647 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 648 misc_pkt.set_shader_debugger.process_context_addr = 649 input->set_shader_debugger.process_context_addr; 650 misc_pkt.set_shader_debugger.flags.u32all = 651 input->set_shader_debugger.flags.u32all; 652 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 653 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 654 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 655 input->set_shader_debugger.tcp_watch_cntl, 656 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 657 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 658 break; 659 case MES_MISC_OP_CHANGE_CONFIG: 660 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 661 dev_warn_once(mes->adev->dev, 662 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 663 return 0; 664 } 665 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 666 misc_pkt.change_config.opcode = 667 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 668 misc_pkt.change_config.option.bits.limit_single_process = 669 input->change_config.option.limit_single_process; 670 break; 671 672 default: 673 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 674 return -EINVAL; 675 } 676 677 return mes_v11_0_submit_pkt_and_poll_completion(mes, 678 &misc_pkt, sizeof(misc_pkt), 679 offsetof(union MESAPI__MISC, api_status)); 680 } 681 682 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 683 { 684 int i; 685 struct amdgpu_device *adev = mes->adev; 686 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 687 688 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 689 690 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 691 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 692 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 693 694 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 695 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 696 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 697 mes_set_hw_res_pkt.paging_vmid = 0; 698 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 699 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 700 mes->query_status_fence_gpu_addr[0]; 701 702 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 703 mes_set_hw_res_pkt.compute_hqd_mask[i] = 704 mes->compute_hqd_mask[i]; 705 706 for (i = 0; i < MAX_GFX_PIPES; i++) 707 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 708 mes->gfx_hqd_mask[i]; 709 710 for (i = 0; i < MAX_SDMA_PIPES; i++) 711 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 712 713 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 714 mes_set_hw_res_pkt.aggregated_doorbells[i] = 715 mes->aggregated_doorbells[i]; 716 717 for (i = 0; i < 5; i++) { 718 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 719 mes_set_hw_res_pkt.mmhub_base[i] = 720 adev->reg_offset[MMHUB_HWIP][0][i]; 721 mes_set_hw_res_pkt.osssys_base[i] = 722 adev->reg_offset[OSSSYS_HWIP][0][i]; 723 } 724 725 mes_set_hw_res_pkt.disable_reset = 1; 726 mes_set_hw_res_pkt.disable_mes_log = 1; 727 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 728 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 729 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 730 mes_set_hw_res_pkt.oversubscription_timer = 50; 731 732 if (amdgpu_mes_log_enable) { 733 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 734 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 735 mes->event_log_gpu_addr; 736 } 737 738 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 739 mes_set_hw_res_pkt.limit_single_process = 1; 740 741 return mes_v11_0_submit_pkt_and_poll_completion(mes, 742 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 743 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 744 } 745 746 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 747 { 748 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 749 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 750 751 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 752 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 753 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 754 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 755 756 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 757 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 758 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 759 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 760 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 761 } 762 763 return mes_v11_0_submit_pkt_and_poll_completion(mes, 764 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 765 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 766 } 767 768 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 769 struct mes_reset_queue_input *input) 770 { 771 union MESAPI__RESET mes_reset_queue_pkt; 772 773 if (input->use_mmio) 774 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 775 input->me_id, input->pipe_id, 776 input->queue_id, input->vmid); 777 778 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 779 780 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 781 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 782 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 783 784 mes_reset_queue_pkt.queue_type = 785 convert_to_mes_queue_type(input->queue_type); 786 787 if (input->legacy_gfx) { 788 mes_reset_queue_pkt.reset_legacy_gfx = 1; 789 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 790 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 791 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 792 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 793 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 794 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 795 } else { 796 mes_reset_queue_pkt.reset_queue_only = 1; 797 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 798 } 799 800 return mes_v11_0_submit_pkt_and_poll_completion(mes, 801 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 802 offsetof(union MESAPI__RESET, api_status)); 803 } 804 805 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 806 struct mes_detect_and_reset_queue_input *input) 807 { 808 union MESAPI__RESET mes_reset_queue_pkt; 809 810 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 811 812 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 813 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 814 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 815 816 mes_reset_queue_pkt.queue_type = 817 convert_to_mes_queue_type(input->queue_type); 818 mes_reset_queue_pkt.doorbell_offset_addr = 819 mes->hung_queue_db_array_gpu_addr[0]; 820 821 if (input->detect_only) 822 mes_reset_queue_pkt.hang_detect_only = 1; 823 else 824 mes_reset_queue_pkt.hang_detect_then_reset = 1; 825 826 return mes_v11_0_submit_pkt_and_poll_completion(mes, 827 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 828 offsetof(union MESAPI__RESET, api_status)); 829 } 830 831 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 832 .add_hw_queue = mes_v11_0_add_hw_queue, 833 .remove_hw_queue = mes_v11_0_remove_hw_queue, 834 .map_legacy_queue = mes_v11_0_map_legacy_queue, 835 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 836 .suspend_gang = mes_v11_0_suspend_gang, 837 .resume_gang = mes_v11_0_resume_gang, 838 .misc_op = mes_v11_0_misc_op, 839 .reset_hw_queue = mes_v11_0_reset_hw_queue, 840 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 841 }; 842 843 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 844 enum amdgpu_mes_pipe pipe) 845 { 846 int r; 847 const struct mes_firmware_header_v1_0 *mes_hdr; 848 const __le32 *fw_data; 849 unsigned fw_size; 850 851 mes_hdr = (const struct mes_firmware_header_v1_0 *) 852 adev->mes.fw[pipe]->data; 853 854 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 855 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 856 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 857 858 r = amdgpu_bo_create_reserved(adev, fw_size, 859 PAGE_SIZE, 860 AMDGPU_GEM_DOMAIN_VRAM | 861 AMDGPU_GEM_DOMAIN_GTT, 862 &adev->mes.ucode_fw_obj[pipe], 863 &adev->mes.ucode_fw_gpu_addr[pipe], 864 (void **)&adev->mes.ucode_fw_ptr[pipe]); 865 if (r) { 866 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 867 return r; 868 } 869 870 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 871 872 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 873 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 874 875 return 0; 876 } 877 878 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 879 enum amdgpu_mes_pipe pipe) 880 { 881 int r; 882 const struct mes_firmware_header_v1_0 *mes_hdr; 883 const __le32 *fw_data; 884 unsigned fw_size; 885 886 mes_hdr = (const struct mes_firmware_header_v1_0 *) 887 adev->mes.fw[pipe]->data; 888 889 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 890 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 891 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 892 893 if (fw_size > GFX_MES_DRAM_SIZE) { 894 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 895 pipe, fw_size, GFX_MES_DRAM_SIZE); 896 return -EINVAL; 897 } 898 899 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 900 64 * 1024, 901 AMDGPU_GEM_DOMAIN_VRAM | 902 AMDGPU_GEM_DOMAIN_GTT, 903 &adev->mes.data_fw_obj[pipe], 904 &adev->mes.data_fw_gpu_addr[pipe], 905 (void **)&adev->mes.data_fw_ptr[pipe]); 906 if (r) { 907 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 908 return r; 909 } 910 911 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 912 913 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 914 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 915 916 return 0; 917 } 918 919 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 920 enum amdgpu_mes_pipe pipe) 921 { 922 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 923 &adev->mes.data_fw_gpu_addr[pipe], 924 (void **)&adev->mes.data_fw_ptr[pipe]); 925 926 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 927 &adev->mes.ucode_fw_gpu_addr[pipe], 928 (void **)&adev->mes.ucode_fw_ptr[pipe]); 929 } 930 931 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 932 { 933 int pipe; 934 935 /* return early if we have already fetched these */ 936 if (adev->mes.sched_version && adev->mes.kiq_version) 937 return; 938 939 /* get MES scheduler/KIQ versions */ 940 mutex_lock(&adev->srbm_mutex); 941 942 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 943 soc21_grbm_select(adev, 3, pipe, 0, 0); 944 945 if (pipe == AMDGPU_MES_SCHED_PIPE) 946 adev->mes.sched_version = 947 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 948 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 949 adev->mes.kiq_version = 950 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 951 } 952 953 soc21_grbm_select(adev, 0, 0, 0, 0); 954 mutex_unlock(&adev->srbm_mutex); 955 } 956 957 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 958 { 959 uint64_t ucode_addr; 960 uint32_t pipe, data = 0; 961 962 if (enable) { 963 if (amdgpu_mes_log_enable) { 964 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 965 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 966 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 967 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 968 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 969 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 970 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 971 } 972 973 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 974 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 975 data = REG_SET_FIELD(data, CP_MES_CNTL, 976 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 977 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 978 979 mutex_lock(&adev->srbm_mutex); 980 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 981 if (!adev->enable_mes_kiq && 982 pipe == AMDGPU_MES_KIQ_PIPE) 983 continue; 984 985 soc21_grbm_select(adev, 3, pipe, 0, 0); 986 987 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 988 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 989 lower_32_bits(ucode_addr)); 990 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 991 upper_32_bits(ucode_addr)); 992 } 993 soc21_grbm_select(adev, 0, 0, 0, 0); 994 mutex_unlock(&adev->srbm_mutex); 995 996 /* unhalt MES and activate pipe0 */ 997 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 998 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 999 adev->enable_mes_kiq ? 1 : 0); 1000 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1001 1002 if (amdgpu_emu_mode) 1003 msleep(100); 1004 else 1005 udelay(500); 1006 } else { 1007 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1008 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1009 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1010 data = REG_SET_FIELD(data, CP_MES_CNTL, 1011 MES_INVALIDATE_ICACHE, 1); 1012 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1013 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1014 adev->enable_mes_kiq ? 1 : 0); 1015 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1016 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1017 } 1018 } 1019 1020 /* This function is for backdoor MES firmware */ 1021 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1022 enum amdgpu_mes_pipe pipe, bool prime_icache) 1023 { 1024 int r; 1025 uint32_t data; 1026 uint64_t ucode_addr; 1027 1028 mes_v11_0_enable(adev, false); 1029 1030 if (!adev->mes.fw[pipe]) 1031 return -EINVAL; 1032 1033 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1034 if (r) 1035 return r; 1036 1037 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1038 if (r) { 1039 mes_v11_0_free_ucode_buffers(adev, pipe); 1040 return r; 1041 } 1042 1043 mutex_lock(&adev->srbm_mutex); 1044 /* me=3, pipe=0, queue=0 */ 1045 soc21_grbm_select(adev, 3, pipe, 0, 0); 1046 1047 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1048 1049 /* set ucode start address */ 1050 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1051 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1052 lower_32_bits(ucode_addr)); 1053 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1054 upper_32_bits(ucode_addr)); 1055 1056 /* set ucode fimrware address */ 1057 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1058 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1059 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1060 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1061 1062 /* set ucode instruction cache boundary to 2M-1 */ 1063 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1064 1065 /* set ucode data firmware address */ 1066 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1067 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1068 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1069 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1070 1071 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1072 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1073 1074 if (prime_icache) { 1075 /* invalidate ICACHE */ 1076 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1077 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1078 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1079 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1080 1081 /* prime the ICACHE. */ 1082 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1083 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1084 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1085 } 1086 1087 soc21_grbm_select(adev, 0, 0, 0, 0); 1088 mutex_unlock(&adev->srbm_mutex); 1089 1090 return 0; 1091 } 1092 1093 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1094 enum amdgpu_mes_pipe pipe) 1095 { 1096 int r; 1097 u32 *eop; 1098 1099 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1100 AMDGPU_GEM_DOMAIN_GTT, 1101 &adev->mes.eop_gpu_obj[pipe], 1102 &adev->mes.eop_gpu_addr[pipe], 1103 (void **)&eop); 1104 if (r) { 1105 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1106 return r; 1107 } 1108 1109 memset(eop, 0, 1110 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1111 1112 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1113 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1114 1115 return 0; 1116 } 1117 1118 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1119 { 1120 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1121 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1122 uint32_t tmp; 1123 1124 memset(mqd, 0, sizeof(*mqd)); 1125 1126 mqd->header = 0xC0310800; 1127 mqd->compute_pipelinestat_enable = 0x00000001; 1128 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1129 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1130 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1131 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1132 mqd->compute_misc_reserved = 0x00000007; 1133 1134 eop_base_addr = ring->eop_gpu_addr >> 8; 1135 1136 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1137 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1138 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1139 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1140 1141 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1142 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1143 mqd->cp_hqd_eop_control = tmp; 1144 1145 /* disable the queue if it's active */ 1146 ring->wptr = 0; 1147 mqd->cp_hqd_pq_rptr = 0; 1148 mqd->cp_hqd_pq_wptr_lo = 0; 1149 mqd->cp_hqd_pq_wptr_hi = 0; 1150 1151 /* set the pointer to the MQD */ 1152 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1153 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1154 1155 /* set MQD vmid to 0 */ 1156 tmp = regCP_MQD_CONTROL_DEFAULT; 1157 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1158 mqd->cp_mqd_control = tmp; 1159 1160 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1161 hqd_gpu_addr = ring->gpu_addr >> 8; 1162 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1163 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1164 1165 /* set the wb address whether it's enabled or not */ 1166 wb_gpu_addr = ring->rptr_gpu_addr; 1167 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1168 mqd->cp_hqd_pq_rptr_report_addr_hi = 1169 upper_32_bits(wb_gpu_addr) & 0xffff; 1170 1171 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1172 wb_gpu_addr = ring->wptr_gpu_addr; 1173 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1174 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1175 1176 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1177 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1179 (order_base_2(ring->ring_size / 4) - 1)); 1180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1181 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1184 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1185 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1186 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1187 mqd->cp_hqd_pq_control = tmp; 1188 1189 /* enable doorbell */ 1190 tmp = 0; 1191 if (ring->use_doorbell) { 1192 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1193 DOORBELL_OFFSET, ring->doorbell_index); 1194 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1195 DOORBELL_EN, 1); 1196 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1197 DOORBELL_SOURCE, 0); 1198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1199 DOORBELL_HIT, 0); 1200 } else 1201 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1202 DOORBELL_EN, 0); 1203 mqd->cp_hqd_pq_doorbell_control = tmp; 1204 1205 mqd->cp_hqd_vmid = 0; 1206 /* activate the queue */ 1207 mqd->cp_hqd_active = 1; 1208 1209 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1210 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1211 PRELOAD_SIZE, 0x55); 1212 mqd->cp_hqd_persistent_state = tmp; 1213 1214 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1215 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1216 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1217 1218 amdgpu_device_flush_hdp(ring->adev, NULL); 1219 return 0; 1220 } 1221 1222 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1223 { 1224 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1225 struct amdgpu_device *adev = ring->adev; 1226 uint32_t data = 0; 1227 1228 mutex_lock(&adev->srbm_mutex); 1229 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1230 1231 /* set CP_HQD_VMID.VMID = 0. */ 1232 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1233 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1234 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1235 1236 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1237 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1238 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1239 DOORBELL_EN, 0); 1240 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1241 1242 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1243 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1244 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1245 1246 /* set CP_MQD_CONTROL.VMID=0 */ 1247 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1248 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1249 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1250 1251 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1252 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1253 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1254 1255 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1256 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1257 mqd->cp_hqd_pq_rptr_report_addr_lo); 1258 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1259 mqd->cp_hqd_pq_rptr_report_addr_hi); 1260 1261 /* set CP_HQD_PQ_CONTROL */ 1262 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1263 1264 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1265 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1266 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1267 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1268 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1269 1270 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1271 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1272 mqd->cp_hqd_pq_doorbell_control); 1273 1274 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1275 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1276 1277 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1278 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1279 1280 soc21_grbm_select(adev, 0, 0, 0, 0); 1281 mutex_unlock(&adev->srbm_mutex); 1282 } 1283 1284 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1285 { 1286 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1287 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1288 int r; 1289 1290 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1291 return -EINVAL; 1292 1293 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1294 if (r) { 1295 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1296 return r; 1297 } 1298 1299 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1300 1301 return amdgpu_ring_test_helper(kiq_ring); 1302 } 1303 1304 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1305 enum amdgpu_mes_pipe pipe) 1306 { 1307 struct amdgpu_ring *ring; 1308 int r; 1309 1310 if (pipe == AMDGPU_MES_KIQ_PIPE) 1311 ring = &adev->gfx.kiq[0].ring; 1312 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1313 ring = &adev->mes.ring[0]; 1314 else 1315 BUG(); 1316 1317 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1318 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1319 *(ring->wptr_cpu_addr) = 0; 1320 *(ring->rptr_cpu_addr) = 0; 1321 amdgpu_ring_clear_ring(ring); 1322 } 1323 1324 r = mes_v11_0_mqd_init(ring); 1325 if (r) 1326 return r; 1327 1328 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1329 r = mes_v11_0_kiq_enable_queue(adev); 1330 if (r) 1331 return r; 1332 } else { 1333 mes_v11_0_queue_init_register(ring); 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1340 { 1341 struct amdgpu_ring *ring; 1342 1343 ring = &adev->mes.ring[0]; 1344 1345 ring->funcs = &mes_v11_0_ring_funcs; 1346 1347 ring->me = 3; 1348 ring->pipe = 0; 1349 ring->queue = 0; 1350 1351 ring->ring_obj = NULL; 1352 ring->use_doorbell = true; 1353 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1354 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1355 ring->no_scheduler = true; 1356 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1357 1358 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1359 AMDGPU_RING_PRIO_DEFAULT, NULL); 1360 } 1361 1362 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1363 { 1364 struct amdgpu_ring *ring; 1365 1366 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1367 1368 ring = &adev->gfx.kiq[0].ring; 1369 1370 ring->me = 3; 1371 ring->pipe = 1; 1372 ring->queue = 0; 1373 1374 ring->adev = NULL; 1375 ring->ring_obj = NULL; 1376 ring->use_doorbell = true; 1377 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1378 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1379 ring->no_scheduler = true; 1380 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1381 ring->me, ring->pipe, ring->queue); 1382 1383 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1384 AMDGPU_RING_PRIO_DEFAULT, NULL); 1385 } 1386 1387 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1388 enum amdgpu_mes_pipe pipe) 1389 { 1390 int r, mqd_size = sizeof(struct v11_compute_mqd); 1391 struct amdgpu_ring *ring; 1392 1393 if (pipe == AMDGPU_MES_KIQ_PIPE) 1394 ring = &adev->gfx.kiq[0].ring; 1395 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1396 ring = &adev->mes.ring[0]; 1397 else 1398 BUG(); 1399 1400 if (ring->mqd_obj) 1401 return 0; 1402 1403 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1404 AMDGPU_GEM_DOMAIN_VRAM | 1405 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1406 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1407 if (r) { 1408 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1409 return r; 1410 } 1411 1412 memset(ring->mqd_ptr, 0, mqd_size); 1413 1414 /* prepare MQD backup */ 1415 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1416 if (!adev->mes.mqd_backup[pipe]) { 1417 dev_warn(adev->dev, 1418 "no memory to create MQD backup for ring %s\n", 1419 ring->name); 1420 return -ENOMEM; 1421 } 1422 1423 return 0; 1424 } 1425 1426 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1427 { 1428 struct amdgpu_device *adev = ip_block->adev; 1429 int pipe, r, bo_size; 1430 1431 adev->mes.funcs = &mes_v11_0_funcs; 1432 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1433 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1434 1435 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1436 1437 r = amdgpu_mes_init(adev); 1438 if (r) 1439 return r; 1440 1441 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1442 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1443 continue; 1444 1445 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1446 if (r) 1447 return r; 1448 1449 r = mes_v11_0_mqd_sw_init(adev, pipe); 1450 if (r) 1451 return r; 1452 } 1453 1454 if (adev->enable_mes_kiq) { 1455 r = mes_v11_0_kiq_ring_init(adev); 1456 if (r) 1457 return r; 1458 } 1459 1460 r = mes_v11_0_ring_init(adev); 1461 if (r) 1462 return r; 1463 1464 bo_size = AMDGPU_GPU_PAGE_SIZE; 1465 if (amdgpu_sriov_is_mes_info_enable(adev)) 1466 bo_size += MES11_HW_RESOURCE_1_SIZE; 1467 1468 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1469 r = amdgpu_bo_create_kernel(adev, 1470 bo_size, 1471 PAGE_SIZE, 1472 AMDGPU_GEM_DOMAIN_VRAM, 1473 &adev->mes.resource_1[0], 1474 &adev->mes.resource_1_gpu_addr[0], 1475 &adev->mes.resource_1_addr[0]); 1476 if (r) { 1477 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1478 return r; 1479 } 1480 1481 return 0; 1482 } 1483 1484 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1485 { 1486 struct amdgpu_device *adev = ip_block->adev; 1487 int pipe; 1488 1489 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1490 &adev->mes.resource_1_addr[0]); 1491 1492 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1493 kfree(adev->mes.mqd_backup[pipe]); 1494 1495 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1496 &adev->mes.eop_gpu_addr[pipe], 1497 NULL); 1498 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1499 } 1500 1501 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1502 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1503 &adev->gfx.kiq[0].ring.mqd_ptr); 1504 1505 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1506 &adev->mes.ring[0].mqd_gpu_addr, 1507 &adev->mes.ring[0].mqd_ptr); 1508 1509 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1510 amdgpu_ring_fini(&adev->mes.ring[0]); 1511 1512 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1513 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1514 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1515 } 1516 1517 amdgpu_mes_fini(adev); 1518 return 0; 1519 } 1520 1521 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1522 { 1523 uint32_t data; 1524 int i; 1525 struct amdgpu_device *adev = ring->adev; 1526 1527 mutex_lock(&adev->srbm_mutex); 1528 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1529 1530 /* disable the queue if it's active */ 1531 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1532 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1533 for (i = 0; i < adev->usec_timeout; i++) { 1534 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1535 break; 1536 udelay(1); 1537 } 1538 } 1539 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1540 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1541 DOORBELL_EN, 0); 1542 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1543 DOORBELL_HIT, 1); 1544 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1545 1546 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1547 1548 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1549 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1550 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1551 1552 soc21_grbm_select(adev, 0, 0, 0, 0); 1553 mutex_unlock(&adev->srbm_mutex); 1554 } 1555 1556 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1557 { 1558 uint32_t tmp; 1559 struct amdgpu_device *adev = ring->adev; 1560 1561 /* tell RLC which is KIQ queue */ 1562 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1563 tmp &= 0xffffff00; 1564 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1565 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1566 } 1567 1568 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1569 { 1570 uint32_t tmp; 1571 1572 /* tell RLC which is KIQ dequeue */ 1573 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1574 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1575 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1576 } 1577 1578 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1579 { 1580 int r = 0; 1581 struct amdgpu_ip_block *ip_block; 1582 1583 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1584 1585 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1586 if (r) { 1587 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1588 return r; 1589 } 1590 1591 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1592 if (r) { 1593 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1594 return r; 1595 } 1596 1597 } 1598 1599 mes_v11_0_enable(adev, true); 1600 1601 mes_v11_0_get_fw_version(adev); 1602 1603 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1604 1605 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1606 if (unlikely(!ip_block)) { 1607 dev_err(adev->dev, "Failed to get MES handle\n"); 1608 return -EINVAL; 1609 } 1610 1611 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1612 if (r) 1613 goto failure; 1614 1615 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1616 adev->mes.enable_legacy_queue_map = true; 1617 else 1618 adev->mes.enable_legacy_queue_map = false; 1619 1620 if (adev->mes.enable_legacy_queue_map) { 1621 r = mes_v11_0_hw_init(ip_block); 1622 if (r) 1623 goto failure; 1624 } 1625 1626 return r; 1627 1628 failure: 1629 mes_v11_0_hw_fini(ip_block); 1630 return r; 1631 } 1632 1633 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1634 { 1635 if (adev->mes.ring[0].sched.ready) { 1636 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1637 adev->mes.ring[0].sched.ready = false; 1638 } 1639 1640 if (amdgpu_sriov_vf(adev)) { 1641 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1642 mes_v11_0_kiq_clear(adev); 1643 } 1644 1645 mes_v11_0_enable(adev, false); 1646 1647 return 0; 1648 } 1649 1650 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1651 { 1652 int r; 1653 struct amdgpu_device *adev = ip_block->adev; 1654 1655 if (adev->mes.ring[0].sched.ready) 1656 goto out; 1657 1658 if (!adev->enable_mes_kiq) { 1659 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1660 r = mes_v11_0_load_microcode(adev, 1661 AMDGPU_MES_SCHED_PIPE, true); 1662 if (r) { 1663 DRM_ERROR("failed to MES fw, r=%d\n", r); 1664 return r; 1665 } 1666 } 1667 1668 mes_v11_0_enable(adev, true); 1669 } 1670 1671 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1672 if (r) 1673 goto failure; 1674 1675 r = mes_v11_0_set_hw_resources(&adev->mes); 1676 if (r) 1677 goto failure; 1678 1679 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1680 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1681 if (r) { 1682 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1683 goto failure; 1684 } 1685 } 1686 1687 r = mes_v11_0_query_sched_status(&adev->mes); 1688 if (r) { 1689 DRM_ERROR("MES is busy\n"); 1690 goto failure; 1691 } 1692 1693 r = amdgpu_mes_update_enforce_isolation(adev); 1694 if (r) 1695 goto failure; 1696 1697 amdgpu_mes_validate_fw_version(adev); 1698 out: 1699 /* 1700 * Disable KIQ ring usage from the driver once MES is enabled. 1701 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1702 * with MES enabled. 1703 */ 1704 adev->gfx.kiq[0].ring.sched.ready = false; 1705 adev->mes.ring[0].sched.ready = true; 1706 1707 return 0; 1708 1709 failure: 1710 mes_v11_0_hw_fini(ip_block); 1711 return r; 1712 } 1713 1714 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1715 { 1716 return 0; 1717 } 1718 1719 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1720 { 1721 return mes_v11_0_hw_fini(ip_block); 1722 } 1723 1724 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1725 { 1726 return mes_v11_0_hw_init(ip_block); 1727 } 1728 1729 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1730 { 1731 struct amdgpu_device *adev = ip_block->adev; 1732 int pipe, r; 1733 1734 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1735 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1736 1737 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1738 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1739 continue; 1740 r = amdgpu_mes_init_microcode(adev, pipe); 1741 if (r) 1742 return r; 1743 } 1744 1745 return 0; 1746 } 1747 1748 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1749 .name = "mes_v11_0", 1750 .early_init = mes_v11_0_early_init, 1751 .late_init = NULL, 1752 .sw_init = mes_v11_0_sw_init, 1753 .sw_fini = mes_v11_0_sw_fini, 1754 .hw_init = mes_v11_0_hw_init, 1755 .hw_fini = mes_v11_0_hw_fini, 1756 .suspend = mes_v11_0_suspend, 1757 .resume = mes_v11_0_resume, 1758 }; 1759 1760 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1761 .type = AMD_IP_BLOCK_TYPE_MES, 1762 .major = 11, 1763 .minor = 0, 1764 .rev = 0, 1765 .funcs = &mes_v11_0_ip_funcs, 1766 }; 1767