1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 53 54 static int mes_v11_0_hw_fini(void *handle); 55 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 56 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 57 58 #define MES_EOP_SIZE 2048 59 60 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 61 { 62 struct amdgpu_device *adev = ring->adev; 63 64 if (ring->use_doorbell) { 65 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 66 ring->wptr); 67 WDOORBELL64(ring->doorbell_index, ring->wptr); 68 } else { 69 BUG(); 70 } 71 } 72 73 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 74 { 75 return *ring->rptr_cpu_addr; 76 } 77 78 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 79 { 80 u64 wptr; 81 82 if (ring->use_doorbell) 83 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 84 else 85 BUG(); 86 return wptr; 87 } 88 89 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 90 .type = AMDGPU_RING_TYPE_MES, 91 .align_mask = 1, 92 .nop = 0, 93 .support_64bit_ptrs = true, 94 .get_rptr = mes_v11_0_ring_get_rptr, 95 .get_wptr = mes_v11_0_ring_get_wptr, 96 .set_wptr = mes_v11_0_ring_set_wptr, 97 .insert_nop = amdgpu_ring_insert_nop, 98 }; 99 100 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 101 void *pkt, int size, 102 int api_status_off) 103 { 104 int ndw = size / 4; 105 signed long r; 106 union MESAPI__ADD_QUEUE *x_pkt = pkt; 107 struct MES_API_STATUS *api_status; 108 struct amdgpu_device *adev = mes->adev; 109 struct amdgpu_ring *ring = &mes->ring; 110 unsigned long flags; 111 signed long timeout = adev->usec_timeout; 112 113 if (amdgpu_emu_mode) { 114 timeout *= 100; 115 } else if (amdgpu_sriov_vf(adev)) { 116 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 117 timeout = 15 * 600 * 1000; 118 } 119 BUG_ON(size % 4 != 0); 120 121 spin_lock_irqsave(&mes->ring_lock, flags); 122 if (amdgpu_ring_alloc(ring, ndw)) { 123 spin_unlock_irqrestore(&mes->ring_lock, flags); 124 return -ENOMEM; 125 } 126 127 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 128 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 129 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 130 131 amdgpu_ring_write_multiple(ring, pkt, ndw); 132 amdgpu_ring_commit(ring); 133 spin_unlock_irqrestore(&mes->ring_lock, flags); 134 135 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 136 137 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 138 timeout); 139 if (r < 1) { 140 DRM_ERROR("MES failed to response msg=%d\n", 141 x_pkt->header.opcode); 142 143 while (halt_if_hws_hang) 144 schedule(); 145 146 return -ETIMEDOUT; 147 } 148 149 return 0; 150 } 151 152 static int convert_to_mes_queue_type(int queue_type) 153 { 154 if (queue_type == AMDGPU_RING_TYPE_GFX) 155 return MES_QUEUE_TYPE_GFX; 156 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 157 return MES_QUEUE_TYPE_COMPUTE; 158 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 159 return MES_QUEUE_TYPE_SDMA; 160 else 161 BUG(); 162 return -1; 163 } 164 165 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 166 struct mes_add_queue_input *input) 167 { 168 struct amdgpu_device *adev = mes->adev; 169 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 170 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 171 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 172 173 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 174 175 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 176 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 177 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 178 179 mes_add_queue_pkt.process_id = input->process_id; 180 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 181 mes_add_queue_pkt.process_va_start = input->process_va_start; 182 mes_add_queue_pkt.process_va_end = input->process_va_end; 183 mes_add_queue_pkt.process_quantum = input->process_quantum; 184 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 185 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 186 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 187 mes_add_queue_pkt.inprocess_gang_priority = 188 input->inprocess_gang_priority; 189 mes_add_queue_pkt.gang_global_priority_level = 190 input->gang_global_priority_level; 191 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 192 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 193 194 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 195 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 196 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 197 else 198 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 199 200 mes_add_queue_pkt.queue_type = 201 convert_to_mes_queue_type(input->queue_type); 202 mes_add_queue_pkt.paging = input->paging; 203 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 204 mes_add_queue_pkt.gws_base = input->gws_base; 205 mes_add_queue_pkt.gws_size = input->gws_size; 206 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 207 mes_add_queue_pkt.tma_addr = input->tma_addr; 208 mes_add_queue_pkt.trap_en = input->trap_en; 209 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 210 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 211 212 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 213 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 214 mes_add_queue_pkt.gds_size = input->queue_size; 215 216 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 217 218 return mes_v11_0_submit_pkt_and_poll_completion(mes, 219 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 220 offsetof(union MESAPI__ADD_QUEUE, api_status)); 221 } 222 223 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 224 struct mes_remove_queue_input *input) 225 { 226 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 227 228 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 229 230 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 231 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 232 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 233 234 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 235 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 236 237 return mes_v11_0_submit_pkt_and_poll_completion(mes, 238 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 239 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 240 } 241 242 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 243 struct mes_unmap_legacy_queue_input *input) 244 { 245 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 246 247 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 248 249 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 250 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 251 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 252 253 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 254 mes_remove_queue_pkt.gang_context_addr = 0; 255 256 mes_remove_queue_pkt.pipe_id = input->pipe_id; 257 mes_remove_queue_pkt.queue_id = input->queue_id; 258 259 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 260 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 261 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 262 mes_remove_queue_pkt.tf_data = 263 lower_32_bits(input->trail_fence_data); 264 } else { 265 mes_remove_queue_pkt.unmap_legacy_queue = 1; 266 mes_remove_queue_pkt.queue_type = 267 convert_to_mes_queue_type(input->queue_type); 268 } 269 270 return mes_v11_0_submit_pkt_and_poll_completion(mes, 271 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 272 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 273 } 274 275 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 276 struct mes_suspend_gang_input *input) 277 { 278 return 0; 279 } 280 281 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 282 struct mes_resume_gang_input *input) 283 { 284 return 0; 285 } 286 287 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 288 { 289 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 290 291 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 292 293 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 294 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 295 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 296 297 return mes_v11_0_submit_pkt_and_poll_completion(mes, 298 &mes_status_pkt, sizeof(mes_status_pkt), 299 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 300 } 301 302 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 303 struct mes_misc_op_input *input) 304 { 305 union MESAPI__MISC misc_pkt; 306 307 memset(&misc_pkt, 0, sizeof(misc_pkt)); 308 309 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 310 misc_pkt.header.opcode = MES_SCH_API_MISC; 311 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 312 313 switch (input->op) { 314 case MES_MISC_OP_READ_REG: 315 misc_pkt.opcode = MESAPI_MISC__READ_REG; 316 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 317 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 318 break; 319 case MES_MISC_OP_WRITE_REG: 320 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 321 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 322 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 323 break; 324 case MES_MISC_OP_WRM_REG_WAIT: 325 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 326 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 327 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 328 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 329 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 330 misc_pkt.wait_reg_mem.reg_offset2 = 0; 331 break; 332 case MES_MISC_OP_WRM_REG_WR_WAIT: 333 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 334 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 335 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 336 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 337 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 338 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 339 break; 340 case MES_MISC_OP_SET_SHADER_DEBUGGER: 341 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 342 misc_pkt.set_shader_debugger.process_context_addr = 343 input->set_shader_debugger.process_context_addr; 344 misc_pkt.set_shader_debugger.flags.u32all = 345 input->set_shader_debugger.flags.u32all; 346 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 347 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 348 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 349 input->set_shader_debugger.tcp_watch_cntl, 350 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 351 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 352 break; 353 default: 354 DRM_ERROR("unsupported misc op (%d) \n", input->op); 355 return -EINVAL; 356 } 357 358 return mes_v11_0_submit_pkt_and_poll_completion(mes, 359 &misc_pkt, sizeof(misc_pkt), 360 offsetof(union MESAPI__MISC, api_status)); 361 } 362 363 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 364 { 365 int i; 366 struct amdgpu_device *adev = mes->adev; 367 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 368 369 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 370 371 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 372 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 373 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 374 375 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 376 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 377 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 378 mes_set_hw_res_pkt.paging_vmid = 0; 379 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 380 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 381 mes->query_status_fence_gpu_addr; 382 383 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 384 mes_set_hw_res_pkt.compute_hqd_mask[i] = 385 mes->compute_hqd_mask[i]; 386 387 for (i = 0; i < MAX_GFX_PIPES; i++) 388 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 389 390 for (i = 0; i < MAX_SDMA_PIPES; i++) 391 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 392 393 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 394 mes_set_hw_res_pkt.aggregated_doorbells[i] = 395 mes->aggregated_doorbells[i]; 396 397 for (i = 0; i < 5; i++) { 398 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 399 mes_set_hw_res_pkt.mmhub_base[i] = 400 adev->reg_offset[MMHUB_HWIP][0][i]; 401 mes_set_hw_res_pkt.osssys_base[i] = 402 adev->reg_offset[OSSSYS_HWIP][0][i]; 403 } 404 405 mes_set_hw_res_pkt.disable_reset = 1; 406 mes_set_hw_res_pkt.disable_mes_log = 1; 407 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 408 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 409 mes_set_hw_res_pkt.oversubscription_timer = 50; 410 411 return mes_v11_0_submit_pkt_and_poll_completion(mes, 412 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 413 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 414 } 415 416 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 417 { 418 struct amdgpu_device *adev = mes->adev; 419 uint32_t data; 420 421 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 422 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 423 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 424 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 425 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 426 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 427 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 428 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 429 430 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 431 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 432 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 433 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 434 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 435 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 436 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 437 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 438 439 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 440 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 441 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 442 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 443 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 444 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 445 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 446 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 447 448 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 449 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 450 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 451 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 452 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 453 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 454 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 455 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 456 457 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 458 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 459 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 460 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 461 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 462 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 463 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 464 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 465 466 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 467 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 468 } 469 470 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 471 .add_hw_queue = mes_v11_0_add_hw_queue, 472 .remove_hw_queue = mes_v11_0_remove_hw_queue, 473 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 474 .suspend_gang = mes_v11_0_suspend_gang, 475 .resume_gang = mes_v11_0_resume_gang, 476 .misc_op = mes_v11_0_misc_op, 477 }; 478 479 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 480 enum admgpu_mes_pipe pipe) 481 { 482 int r; 483 const struct mes_firmware_header_v1_0 *mes_hdr; 484 const __le32 *fw_data; 485 unsigned fw_size; 486 487 mes_hdr = (const struct mes_firmware_header_v1_0 *) 488 adev->mes.fw[pipe]->data; 489 490 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 491 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 492 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 493 494 r = amdgpu_bo_create_reserved(adev, fw_size, 495 PAGE_SIZE, 496 AMDGPU_GEM_DOMAIN_VRAM | 497 AMDGPU_GEM_DOMAIN_GTT, 498 &adev->mes.ucode_fw_obj[pipe], 499 &adev->mes.ucode_fw_gpu_addr[pipe], 500 (void **)&adev->mes.ucode_fw_ptr[pipe]); 501 if (r) { 502 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 503 return r; 504 } 505 506 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 507 508 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 509 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 510 511 return 0; 512 } 513 514 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 515 enum admgpu_mes_pipe pipe) 516 { 517 int r; 518 const struct mes_firmware_header_v1_0 *mes_hdr; 519 const __le32 *fw_data; 520 unsigned fw_size; 521 522 mes_hdr = (const struct mes_firmware_header_v1_0 *) 523 adev->mes.fw[pipe]->data; 524 525 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 526 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 527 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 528 529 r = amdgpu_bo_create_reserved(adev, fw_size, 530 64 * 1024, 531 AMDGPU_GEM_DOMAIN_VRAM | 532 AMDGPU_GEM_DOMAIN_GTT, 533 &adev->mes.data_fw_obj[pipe], 534 &adev->mes.data_fw_gpu_addr[pipe], 535 (void **)&adev->mes.data_fw_ptr[pipe]); 536 if (r) { 537 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 538 return r; 539 } 540 541 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 542 543 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 544 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 545 546 return 0; 547 } 548 549 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 550 enum admgpu_mes_pipe pipe) 551 { 552 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 553 &adev->mes.data_fw_gpu_addr[pipe], 554 (void **)&adev->mes.data_fw_ptr[pipe]); 555 556 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 557 &adev->mes.ucode_fw_gpu_addr[pipe], 558 (void **)&adev->mes.ucode_fw_ptr[pipe]); 559 } 560 561 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 562 { 563 uint64_t ucode_addr; 564 uint32_t pipe, data = 0; 565 566 if (enable) { 567 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 568 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 569 data = REG_SET_FIELD(data, CP_MES_CNTL, 570 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 571 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 572 573 mutex_lock(&adev->srbm_mutex); 574 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 575 if (!adev->enable_mes_kiq && 576 pipe == AMDGPU_MES_KIQ_PIPE) 577 continue; 578 579 soc21_grbm_select(adev, 3, pipe, 0, 0); 580 581 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 582 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 583 lower_32_bits(ucode_addr)); 584 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 585 upper_32_bits(ucode_addr)); 586 } 587 soc21_grbm_select(adev, 0, 0, 0, 0); 588 mutex_unlock(&adev->srbm_mutex); 589 590 /* unhalt MES and activate pipe0 */ 591 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 592 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 593 adev->enable_mes_kiq ? 1 : 0); 594 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 595 596 if (amdgpu_emu_mode) 597 msleep(100); 598 else 599 udelay(50); 600 } else { 601 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 602 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 603 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 604 data = REG_SET_FIELD(data, CP_MES_CNTL, 605 MES_INVALIDATE_ICACHE, 1); 606 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 607 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 608 adev->enable_mes_kiq ? 1 : 0); 609 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 610 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 611 } 612 } 613 614 /* This function is for backdoor MES firmware */ 615 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 616 enum admgpu_mes_pipe pipe, bool prime_icache) 617 { 618 int r; 619 uint32_t data; 620 uint64_t ucode_addr; 621 622 mes_v11_0_enable(adev, false); 623 624 if (!adev->mes.fw[pipe]) 625 return -EINVAL; 626 627 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 628 if (r) 629 return r; 630 631 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 632 if (r) { 633 mes_v11_0_free_ucode_buffers(adev, pipe); 634 return r; 635 } 636 637 mutex_lock(&adev->srbm_mutex); 638 /* me=3, pipe=0, queue=0 */ 639 soc21_grbm_select(adev, 3, pipe, 0, 0); 640 641 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 642 643 /* set ucode start address */ 644 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 645 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 646 lower_32_bits(ucode_addr)); 647 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 648 upper_32_bits(ucode_addr)); 649 650 /* set ucode fimrware address */ 651 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 652 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 653 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 654 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 655 656 /* set ucode instruction cache boundary to 2M-1 */ 657 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 658 659 /* set ucode data firmware address */ 660 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 661 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 662 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 663 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 664 665 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 666 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 667 668 if (prime_icache) { 669 /* invalidate ICACHE */ 670 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 671 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 672 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 673 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 674 675 /* prime the ICACHE. */ 676 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 677 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 678 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 679 } 680 681 soc21_grbm_select(adev, 0, 0, 0, 0); 682 mutex_unlock(&adev->srbm_mutex); 683 684 return 0; 685 } 686 687 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 688 enum admgpu_mes_pipe pipe) 689 { 690 int r; 691 u32 *eop; 692 693 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 694 AMDGPU_GEM_DOMAIN_GTT, 695 &adev->mes.eop_gpu_obj[pipe], 696 &adev->mes.eop_gpu_addr[pipe], 697 (void **)&eop); 698 if (r) { 699 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 700 return r; 701 } 702 703 memset(eop, 0, 704 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 705 706 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 707 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 708 709 return 0; 710 } 711 712 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 713 { 714 struct v11_compute_mqd *mqd = ring->mqd_ptr; 715 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 716 uint32_t tmp; 717 718 memset(mqd, 0, sizeof(*mqd)); 719 720 mqd->header = 0xC0310800; 721 mqd->compute_pipelinestat_enable = 0x00000001; 722 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 723 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 724 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 725 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 726 mqd->compute_misc_reserved = 0x00000007; 727 728 eop_base_addr = ring->eop_gpu_addr >> 8; 729 730 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 731 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 732 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 733 (order_base_2(MES_EOP_SIZE / 4) - 1)); 734 735 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 736 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 737 mqd->cp_hqd_eop_control = tmp; 738 739 /* disable the queue if it's active */ 740 ring->wptr = 0; 741 mqd->cp_hqd_pq_rptr = 0; 742 mqd->cp_hqd_pq_wptr_lo = 0; 743 mqd->cp_hqd_pq_wptr_hi = 0; 744 745 /* set the pointer to the MQD */ 746 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 747 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 748 749 /* set MQD vmid to 0 */ 750 tmp = regCP_MQD_CONTROL_DEFAULT; 751 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 752 mqd->cp_mqd_control = tmp; 753 754 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 755 hqd_gpu_addr = ring->gpu_addr >> 8; 756 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 757 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 758 759 /* set the wb address whether it's enabled or not */ 760 wb_gpu_addr = ring->rptr_gpu_addr; 761 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 762 mqd->cp_hqd_pq_rptr_report_addr_hi = 763 upper_32_bits(wb_gpu_addr) & 0xffff; 764 765 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 766 wb_gpu_addr = ring->wptr_gpu_addr; 767 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 768 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 769 770 /* set up the HQD, this is similar to CP_RB0_CNTL */ 771 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 772 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 773 (order_base_2(ring->ring_size / 4) - 1)); 774 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 775 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 776 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 780 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 781 mqd->cp_hqd_pq_control = tmp; 782 783 /* enable doorbell */ 784 tmp = 0; 785 if (ring->use_doorbell) { 786 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 787 DOORBELL_OFFSET, ring->doorbell_index); 788 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 789 DOORBELL_EN, 1); 790 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 791 DOORBELL_SOURCE, 0); 792 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 793 DOORBELL_HIT, 0); 794 } else 795 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 796 DOORBELL_EN, 0); 797 mqd->cp_hqd_pq_doorbell_control = tmp; 798 799 mqd->cp_hqd_vmid = 0; 800 /* activate the queue */ 801 mqd->cp_hqd_active = 1; 802 803 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 804 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 805 PRELOAD_SIZE, 0x55); 806 mqd->cp_hqd_persistent_state = tmp; 807 808 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 809 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 810 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 811 812 amdgpu_device_flush_hdp(ring->adev, NULL); 813 return 0; 814 } 815 816 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 817 { 818 struct v11_compute_mqd *mqd = ring->mqd_ptr; 819 struct amdgpu_device *adev = ring->adev; 820 uint32_t data = 0; 821 822 mutex_lock(&adev->srbm_mutex); 823 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 824 825 /* set CP_HQD_VMID.VMID = 0. */ 826 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 827 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 828 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 829 830 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 831 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 832 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 833 DOORBELL_EN, 0); 834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 835 836 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 837 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 838 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 839 840 /* set CP_MQD_CONTROL.VMID=0 */ 841 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 842 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 843 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 844 845 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 846 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 847 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 848 849 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 850 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 851 mqd->cp_hqd_pq_rptr_report_addr_lo); 852 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 853 mqd->cp_hqd_pq_rptr_report_addr_hi); 854 855 /* set CP_HQD_PQ_CONTROL */ 856 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 857 858 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 859 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 860 mqd->cp_hqd_pq_wptr_poll_addr_lo); 861 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 862 mqd->cp_hqd_pq_wptr_poll_addr_hi); 863 864 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 865 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 866 mqd->cp_hqd_pq_doorbell_control); 867 868 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 869 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 870 871 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 872 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 873 874 soc21_grbm_select(adev, 0, 0, 0, 0); 875 mutex_unlock(&adev->srbm_mutex); 876 } 877 878 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 879 { 880 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 881 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 882 int r; 883 884 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 885 return -EINVAL; 886 887 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 888 if (r) { 889 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 890 return r; 891 } 892 893 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 894 895 return amdgpu_ring_test_helper(kiq_ring); 896 } 897 898 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 899 enum admgpu_mes_pipe pipe) 900 { 901 struct amdgpu_ring *ring; 902 int r; 903 904 if (pipe == AMDGPU_MES_KIQ_PIPE) 905 ring = &adev->gfx.kiq[0].ring; 906 else if (pipe == AMDGPU_MES_SCHED_PIPE) 907 ring = &adev->mes.ring; 908 else 909 BUG(); 910 911 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 912 (amdgpu_in_reset(adev) || adev->in_suspend)) { 913 *(ring->wptr_cpu_addr) = 0; 914 *(ring->rptr_cpu_addr) = 0; 915 amdgpu_ring_clear_ring(ring); 916 } 917 918 r = mes_v11_0_mqd_init(ring); 919 if (r) 920 return r; 921 922 if (pipe == AMDGPU_MES_SCHED_PIPE) { 923 r = mes_v11_0_kiq_enable_queue(adev); 924 if (r) 925 return r; 926 } else { 927 mes_v11_0_queue_init_register(ring); 928 } 929 930 /* get MES scheduler/KIQ versions */ 931 mutex_lock(&adev->srbm_mutex); 932 soc21_grbm_select(adev, 3, pipe, 0, 0); 933 934 if (pipe == AMDGPU_MES_SCHED_PIPE) 935 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 936 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 937 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 938 939 soc21_grbm_select(adev, 0, 0, 0, 0); 940 mutex_unlock(&adev->srbm_mutex); 941 942 return 0; 943 } 944 945 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 946 { 947 struct amdgpu_ring *ring; 948 949 ring = &adev->mes.ring; 950 951 ring->funcs = &mes_v11_0_ring_funcs; 952 953 ring->me = 3; 954 ring->pipe = 0; 955 ring->queue = 0; 956 957 ring->ring_obj = NULL; 958 ring->use_doorbell = true; 959 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 960 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 961 ring->no_scheduler = true; 962 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 963 964 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 965 AMDGPU_RING_PRIO_DEFAULT, NULL); 966 } 967 968 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 969 { 970 struct amdgpu_ring *ring; 971 972 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 973 974 ring = &adev->gfx.kiq[0].ring; 975 976 ring->me = 3; 977 ring->pipe = 1; 978 ring->queue = 0; 979 980 ring->adev = NULL; 981 ring->ring_obj = NULL; 982 ring->use_doorbell = true; 983 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 984 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 985 ring->no_scheduler = true; 986 sprintf(ring->name, "mes_kiq_%d.%d.%d", 987 ring->me, ring->pipe, ring->queue); 988 989 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 990 AMDGPU_RING_PRIO_DEFAULT, NULL); 991 } 992 993 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 994 enum admgpu_mes_pipe pipe) 995 { 996 int r, mqd_size = sizeof(struct v11_compute_mqd); 997 struct amdgpu_ring *ring; 998 999 if (pipe == AMDGPU_MES_KIQ_PIPE) 1000 ring = &adev->gfx.kiq[0].ring; 1001 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1002 ring = &adev->mes.ring; 1003 else 1004 BUG(); 1005 1006 if (ring->mqd_obj) 1007 return 0; 1008 1009 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1010 AMDGPU_GEM_DOMAIN_VRAM | 1011 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1012 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1013 if (r) { 1014 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1015 return r; 1016 } 1017 1018 memset(ring->mqd_ptr, 0, mqd_size); 1019 1020 /* prepare MQD backup */ 1021 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1022 if (!adev->mes.mqd_backup[pipe]) { 1023 dev_warn(adev->dev, 1024 "no memory to create MQD backup for ring %s\n", 1025 ring->name); 1026 return -ENOMEM; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int mes_v11_0_sw_init(void *handle) 1033 { 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 int pipe, r; 1036 1037 adev->mes.funcs = &mes_v11_0_funcs; 1038 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1039 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1040 1041 r = amdgpu_mes_init(adev); 1042 if (r) 1043 return r; 1044 1045 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1046 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1047 continue; 1048 1049 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1050 if (r) 1051 return r; 1052 1053 r = mes_v11_0_mqd_sw_init(adev, pipe); 1054 if (r) 1055 return r; 1056 } 1057 1058 if (adev->enable_mes_kiq) { 1059 r = mes_v11_0_kiq_ring_init(adev); 1060 if (r) 1061 return r; 1062 } 1063 1064 r = mes_v11_0_ring_init(adev); 1065 if (r) 1066 return r; 1067 1068 return 0; 1069 } 1070 1071 static int mes_v11_0_sw_fini(void *handle) 1072 { 1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1074 int pipe; 1075 1076 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1077 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1078 1079 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1080 kfree(adev->mes.mqd_backup[pipe]); 1081 1082 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1083 &adev->mes.eop_gpu_addr[pipe], 1084 NULL); 1085 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1086 } 1087 1088 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1089 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1090 &adev->gfx.kiq[0].ring.mqd_ptr); 1091 1092 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1093 &adev->mes.ring.mqd_gpu_addr, 1094 &adev->mes.ring.mqd_ptr); 1095 1096 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1097 amdgpu_ring_fini(&adev->mes.ring); 1098 1099 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1100 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1101 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1102 } 1103 1104 amdgpu_mes_fini(adev); 1105 return 0; 1106 } 1107 1108 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1109 { 1110 uint32_t data; 1111 int i; 1112 struct amdgpu_device *adev = ring->adev; 1113 1114 mutex_lock(&adev->srbm_mutex); 1115 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1116 1117 /* disable the queue if it's active */ 1118 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1119 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1120 for (i = 0; i < adev->usec_timeout; i++) { 1121 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1122 break; 1123 udelay(1); 1124 } 1125 } 1126 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1127 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1128 DOORBELL_EN, 0); 1129 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1130 DOORBELL_HIT, 1); 1131 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1132 1133 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1134 1135 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1136 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1137 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1138 1139 soc21_grbm_select(adev, 0, 0, 0, 0); 1140 mutex_unlock(&adev->srbm_mutex); 1141 } 1142 1143 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1144 { 1145 uint32_t tmp; 1146 struct amdgpu_device *adev = ring->adev; 1147 1148 /* tell RLC which is KIQ queue */ 1149 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1150 tmp &= 0xffffff00; 1151 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1152 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1153 tmp |= 0x80; 1154 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1155 } 1156 1157 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1158 { 1159 uint32_t tmp; 1160 1161 /* tell RLC which is KIQ dequeue */ 1162 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1163 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1164 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1165 } 1166 1167 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1168 { 1169 int r = 0; 1170 1171 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1172 1173 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1174 if (r) { 1175 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1176 return r; 1177 } 1178 1179 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1180 if (r) { 1181 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1182 return r; 1183 } 1184 1185 } 1186 1187 mes_v11_0_enable(adev, true); 1188 1189 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1190 1191 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1192 if (r) 1193 goto failure; 1194 1195 return r; 1196 1197 failure: 1198 mes_v11_0_hw_fini(adev); 1199 return r; 1200 } 1201 1202 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1203 { 1204 if (adev->mes.ring.sched.ready) { 1205 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1206 adev->mes.ring.sched.ready = false; 1207 } 1208 1209 if (amdgpu_sriov_vf(adev)) { 1210 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1211 mes_v11_0_kiq_clear(adev); 1212 } 1213 1214 mes_v11_0_enable(adev, false); 1215 1216 return 0; 1217 } 1218 1219 static int mes_v11_0_hw_init(void *handle) 1220 { 1221 int r; 1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1223 1224 if (!adev->enable_mes_kiq) { 1225 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1226 r = mes_v11_0_load_microcode(adev, 1227 AMDGPU_MES_SCHED_PIPE, true); 1228 if (r) { 1229 DRM_ERROR("failed to MES fw, r=%d\n", r); 1230 return r; 1231 } 1232 } 1233 1234 mes_v11_0_enable(adev, true); 1235 } 1236 1237 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1238 if (r) 1239 goto failure; 1240 1241 r = mes_v11_0_set_hw_resources(&adev->mes); 1242 if (r) 1243 goto failure; 1244 1245 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1246 1247 r = mes_v11_0_query_sched_status(&adev->mes); 1248 if (r) { 1249 DRM_ERROR("MES is busy\n"); 1250 goto failure; 1251 } 1252 1253 /* 1254 * Disable KIQ ring usage from the driver once MES is enabled. 1255 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1256 * with MES enabled. 1257 */ 1258 adev->gfx.kiq[0].ring.sched.ready = false; 1259 adev->mes.ring.sched.ready = true; 1260 1261 return 0; 1262 1263 failure: 1264 mes_v11_0_hw_fini(adev); 1265 return r; 1266 } 1267 1268 static int mes_v11_0_hw_fini(void *handle) 1269 { 1270 return 0; 1271 } 1272 1273 static int mes_v11_0_suspend(void *handle) 1274 { 1275 int r; 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 1278 r = amdgpu_mes_suspend(adev); 1279 if (r) 1280 return r; 1281 1282 return mes_v11_0_hw_fini(adev); 1283 } 1284 1285 static int mes_v11_0_resume(void *handle) 1286 { 1287 int r; 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1289 1290 r = mes_v11_0_hw_init(adev); 1291 if (r) 1292 return r; 1293 1294 return amdgpu_mes_resume(adev); 1295 } 1296 1297 static int mes_v11_0_early_init(void *handle) 1298 { 1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1300 int pipe, r; 1301 1302 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1303 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1304 continue; 1305 r = amdgpu_mes_init_microcode(adev, pipe); 1306 if (r) 1307 return r; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int mes_v11_0_late_init(void *handle) 1314 { 1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1316 1317 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1318 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1319 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1320 amdgpu_mes_self_test(adev); 1321 1322 return 0; 1323 } 1324 1325 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1326 .name = "mes_v11_0", 1327 .early_init = mes_v11_0_early_init, 1328 .late_init = mes_v11_0_late_init, 1329 .sw_init = mes_v11_0_sw_init, 1330 .sw_fini = mes_v11_0_sw_fini, 1331 .hw_init = mes_v11_0_hw_init, 1332 .hw_fini = mes_v11_0_hw_fini, 1333 .suspend = mes_v11_0_suspend, 1334 .resume = mes_v11_0_resume, 1335 }; 1336 1337 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1338 .type = AMD_IP_BLOCK_TYPE_MES, 1339 .major = 11, 1340 .minor = 0, 1341 .rev = 0, 1342 .funcs = &mes_v11_0_ip_funcs, 1343 }; 1344