1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 62 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 63 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 64 65 #define MES_EOP_SIZE 2048 66 #define GFX_MES_DRAM_SIZE 0x80000 67 68 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 69 { 70 struct amdgpu_device *adev = ring->adev; 71 72 if (ring->use_doorbell) { 73 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 74 ring->wptr); 75 WDOORBELL64(ring->doorbell_index, ring->wptr); 76 } else { 77 BUG(); 78 } 79 } 80 81 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 82 { 83 return *ring->rptr_cpu_addr; 84 } 85 86 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 87 { 88 u64 wptr; 89 90 if (ring->use_doorbell) 91 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 92 else 93 BUG(); 94 return wptr; 95 } 96 97 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 98 .type = AMDGPU_RING_TYPE_MES, 99 .align_mask = 1, 100 .nop = 0, 101 .support_64bit_ptrs = true, 102 .get_rptr = mes_v11_0_ring_get_rptr, 103 .get_wptr = mes_v11_0_ring_get_wptr, 104 .set_wptr = mes_v11_0_ring_set_wptr, 105 .insert_nop = amdgpu_ring_insert_nop, 106 }; 107 108 static const char *mes_v11_0_opcodes[] = { 109 "SET_HW_RSRC", 110 "SET_SCHEDULING_CONFIG", 111 "ADD_QUEUE", 112 "REMOVE_QUEUE", 113 "PERFORM_YIELD", 114 "SET_GANG_PRIORITY_LEVEL", 115 "SUSPEND", 116 "RESUME", 117 "RESET", 118 "SET_LOG_BUFFER", 119 "CHANGE_GANG_PRORITY", 120 "QUERY_SCHEDULER_STATUS", 121 "PROGRAM_GDS", 122 "SET_DEBUG_VMID", 123 "MISC", 124 "UPDATE_ROOT_PAGE_TABLE", 125 "AMD_LOG", 126 "unused", 127 "unused", 128 "SET_HW_RSRC_1", 129 }; 130 131 static const char *mes_v11_0_misc_opcodes[] = { 132 "WRITE_REG", 133 "INV_GART", 134 "QUERY_STATUS", 135 "READ_REG", 136 "WAIT_REG_MEM", 137 "SET_SHADER_DEBUGGER", 138 }; 139 140 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 141 { 142 const char *op_str = NULL; 143 144 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 145 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 146 147 return op_str; 148 } 149 150 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 151 { 152 const char *op_str = NULL; 153 154 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 155 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 156 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 157 158 return op_str; 159 } 160 161 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 162 void *pkt, int size, 163 int api_status_off) 164 { 165 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 166 signed long timeout = 2100000; /* 2100 ms */ 167 struct amdgpu_device *adev = mes->adev; 168 struct amdgpu_ring *ring = &mes->ring[0]; 169 struct MES_API_STATUS *api_status; 170 union MESAPI__MISC *x_pkt = pkt; 171 const char *op_str, *misc_op_str; 172 unsigned long flags; 173 u64 status_gpu_addr; 174 u32 seq, status_offset; 175 u64 *status_ptr; 176 signed long r; 177 int ret; 178 179 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 180 return -EINVAL; 181 182 if (amdgpu_emu_mode) { 183 timeout *= 100; 184 } else if (amdgpu_sriov_vf(adev)) { 185 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 186 timeout = 15 * 600 * 1000; 187 } 188 189 ret = amdgpu_device_wb_get(adev, &status_offset); 190 if (ret) 191 return ret; 192 193 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 194 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 195 *status_ptr = 0; 196 197 spin_lock_irqsave(&mes->ring_lock[0], flags); 198 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 199 if (r) 200 goto error_unlock_free; 201 202 seq = ++ring->fence_drv.sync_seq; 203 r = amdgpu_fence_wait_polling(ring, 204 seq - ring->fence_drv.num_fences_mask, 205 timeout); 206 if (r < 1) 207 goto error_undo; 208 209 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 210 api_status->api_completion_fence_addr = status_gpu_addr; 211 api_status->api_completion_fence_value = 1; 212 213 amdgpu_ring_write_multiple(ring, pkt, size / 4); 214 215 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 216 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 217 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 218 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 219 mes_status_pkt.api_status.api_completion_fence_addr = 220 ring->fence_drv.gpu_addr; 221 mes_status_pkt.api_status.api_completion_fence_value = seq; 222 223 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 224 sizeof(mes_status_pkt) / 4); 225 226 amdgpu_ring_commit(ring); 227 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 228 229 op_str = mes_v11_0_get_op_string(x_pkt); 230 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 231 232 if (misc_op_str) 233 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 234 misc_op_str); 235 else if (op_str) 236 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 237 else 238 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 239 x_pkt->header.opcode); 240 241 r = amdgpu_fence_wait_polling(ring, seq, timeout); 242 if (r < 1 || !*status_ptr) { 243 244 if (misc_op_str) 245 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 246 op_str, misc_op_str); 247 else if (op_str) 248 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 249 op_str); 250 else 251 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 252 x_pkt->header.opcode); 253 254 while (halt_if_hws_hang) 255 schedule(); 256 257 r = -ETIMEDOUT; 258 goto error_wb_free; 259 } 260 261 amdgpu_device_wb_free(adev, status_offset); 262 return 0; 263 264 error_undo: 265 dev_err(adev->dev, "MES ring buffer is full.\n"); 266 amdgpu_ring_undo(ring); 267 268 error_unlock_free: 269 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 270 271 error_wb_free: 272 amdgpu_device_wb_free(adev, status_offset); 273 return r; 274 } 275 276 static int convert_to_mes_queue_type(int queue_type) 277 { 278 if (queue_type == AMDGPU_RING_TYPE_GFX) 279 return MES_QUEUE_TYPE_GFX; 280 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 281 return MES_QUEUE_TYPE_COMPUTE; 282 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 283 return MES_QUEUE_TYPE_SDMA; 284 else 285 BUG(); 286 return -1; 287 } 288 289 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 290 struct mes_add_queue_input *input) 291 { 292 struct amdgpu_device *adev = mes->adev; 293 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 294 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 295 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 296 297 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 298 299 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 300 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 301 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 302 303 mes_add_queue_pkt.process_id = input->process_id; 304 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 305 mes_add_queue_pkt.process_va_start = input->process_va_start; 306 mes_add_queue_pkt.process_va_end = input->process_va_end; 307 mes_add_queue_pkt.process_quantum = input->process_quantum; 308 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 309 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 310 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 311 mes_add_queue_pkt.inprocess_gang_priority = 312 input->inprocess_gang_priority; 313 mes_add_queue_pkt.gang_global_priority_level = 314 input->gang_global_priority_level; 315 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 316 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 317 318 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 319 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 320 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 321 else 322 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 323 324 mes_add_queue_pkt.queue_type = 325 convert_to_mes_queue_type(input->queue_type); 326 mes_add_queue_pkt.paging = input->paging; 327 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 328 mes_add_queue_pkt.gws_base = input->gws_base; 329 mes_add_queue_pkt.gws_size = input->gws_size; 330 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 331 mes_add_queue_pkt.tma_addr = input->tma_addr; 332 mes_add_queue_pkt.trap_en = input->trap_en; 333 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 334 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 335 336 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 337 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 338 mes_add_queue_pkt.gds_size = input->queue_size; 339 340 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 341 342 return mes_v11_0_submit_pkt_and_poll_completion(mes, 343 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 344 offsetof(union MESAPI__ADD_QUEUE, api_status)); 345 } 346 347 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 348 struct mes_remove_queue_input *input) 349 { 350 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 351 352 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 353 354 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 355 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 356 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 357 358 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 359 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 360 361 return mes_v11_0_submit_pkt_and_poll_completion(mes, 362 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 363 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 364 } 365 366 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 367 uint32_t me_id, uint32_t pipe_id, 368 uint32_t queue_id, uint32_t vmid) 369 { 370 struct amdgpu_device *adev = mes->adev; 371 uint32_t value, reg; 372 int i, r = 0; 373 374 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 375 376 if (queue_type == AMDGPU_RING_TYPE_GFX) { 377 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 378 me_id, pipe_id, queue_id, vmid); 379 380 mutex_lock(&adev->gfx.reset_sem_mutex); 381 gfx_v11_0_request_gfx_index_mutex(adev, true); 382 /* all se allow writes */ 383 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 384 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 385 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 386 if (pipe_id == 0) 387 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 388 else 389 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 390 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 391 gfx_v11_0_request_gfx_index_mutex(adev, false); 392 mutex_unlock(&adev->gfx.reset_sem_mutex); 393 394 mutex_lock(&adev->srbm_mutex); 395 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 396 /* wait till dequeue take effects */ 397 for (i = 0; i < adev->usec_timeout; i++) { 398 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 399 break; 400 udelay(1); 401 } 402 if (i >= adev->usec_timeout) { 403 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 404 r = -ETIMEDOUT; 405 } 406 407 soc21_grbm_select(adev, 0, 0, 0, 0); 408 mutex_unlock(&adev->srbm_mutex); 409 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 410 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 411 me_id, pipe_id, queue_id); 412 mutex_lock(&adev->srbm_mutex); 413 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 414 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 415 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 416 417 /* wait till dequeue take effects */ 418 for (i = 0; i < adev->usec_timeout; i++) { 419 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 420 break; 421 udelay(1); 422 } 423 if (i >= adev->usec_timeout) { 424 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 425 r = -ETIMEDOUT; 426 } 427 soc21_grbm_select(adev, 0, 0, 0, 0); 428 mutex_unlock(&adev->srbm_mutex); 429 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 430 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 431 me_id, pipe_id, queue_id); 432 switch (me_id) { 433 case 1: 434 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 435 break; 436 case 0: 437 default: 438 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 439 break; 440 } 441 442 value = 1 << queue_id; 443 WREG32(reg, value); 444 /* wait for queue reset done */ 445 for (i = 0; i < adev->usec_timeout; i++) { 446 if (!(RREG32(reg) & value)) 447 break; 448 udelay(1); 449 } 450 if (i >= adev->usec_timeout) { 451 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 452 r = -ETIMEDOUT; 453 } 454 } 455 456 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 457 return r; 458 } 459 460 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 461 struct mes_reset_queue_input *input) 462 { 463 if (input->use_mmio) 464 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 465 input->me_id, input->pipe_id, 466 input->queue_id, input->vmid); 467 468 union MESAPI__RESET mes_reset_queue_pkt; 469 470 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 471 472 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 473 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 474 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 475 476 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 477 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; 478 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 479 480 return mes_v11_0_submit_pkt_and_poll_completion(mes, 481 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 482 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 483 } 484 485 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 486 struct mes_map_legacy_queue_input *input) 487 { 488 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 489 490 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 491 492 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 493 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 494 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 495 496 mes_add_queue_pkt.pipe_id = input->pipe_id; 497 mes_add_queue_pkt.queue_id = input->queue_id; 498 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 499 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 500 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 501 mes_add_queue_pkt.queue_type = 502 convert_to_mes_queue_type(input->queue_type); 503 mes_add_queue_pkt.map_legacy_kq = 1; 504 505 return mes_v11_0_submit_pkt_and_poll_completion(mes, 506 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 507 offsetof(union MESAPI__ADD_QUEUE, api_status)); 508 } 509 510 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 511 struct mes_unmap_legacy_queue_input *input) 512 { 513 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 514 515 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 516 517 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 518 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 519 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 520 521 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 522 mes_remove_queue_pkt.gang_context_addr = 0; 523 524 mes_remove_queue_pkt.pipe_id = input->pipe_id; 525 mes_remove_queue_pkt.queue_id = input->queue_id; 526 527 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 528 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 529 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 530 mes_remove_queue_pkt.tf_data = 531 lower_32_bits(input->trail_fence_data); 532 } else { 533 mes_remove_queue_pkt.unmap_legacy_queue = 1; 534 mes_remove_queue_pkt.queue_type = 535 convert_to_mes_queue_type(input->queue_type); 536 } 537 538 return mes_v11_0_submit_pkt_and_poll_completion(mes, 539 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 540 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 541 } 542 543 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 544 struct mes_suspend_gang_input *input) 545 { 546 union MESAPI__SUSPEND mes_suspend_gang_pkt; 547 548 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 549 550 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 551 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 552 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 553 554 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 555 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 556 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 557 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 558 559 return mes_v11_0_submit_pkt_and_poll_completion(mes, 560 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 561 offsetof(union MESAPI__SUSPEND, api_status)); 562 } 563 564 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 565 struct mes_resume_gang_input *input) 566 { 567 union MESAPI__RESUME mes_resume_gang_pkt; 568 569 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 570 571 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 572 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 573 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 574 575 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 576 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 577 578 return mes_v11_0_submit_pkt_and_poll_completion(mes, 579 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 580 offsetof(union MESAPI__RESUME, api_status)); 581 } 582 583 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 584 { 585 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 586 587 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 588 589 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 590 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 591 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 592 593 return mes_v11_0_submit_pkt_and_poll_completion(mes, 594 &mes_status_pkt, sizeof(mes_status_pkt), 595 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 596 } 597 598 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 599 struct mes_misc_op_input *input) 600 { 601 union MESAPI__MISC misc_pkt; 602 603 memset(&misc_pkt, 0, sizeof(misc_pkt)); 604 605 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 606 misc_pkt.header.opcode = MES_SCH_API_MISC; 607 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 608 609 switch (input->op) { 610 case MES_MISC_OP_READ_REG: 611 misc_pkt.opcode = MESAPI_MISC__READ_REG; 612 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 613 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 614 break; 615 case MES_MISC_OP_WRITE_REG: 616 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 617 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 618 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 619 break; 620 case MES_MISC_OP_WRM_REG_WAIT: 621 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 622 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 623 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 624 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 625 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 626 misc_pkt.wait_reg_mem.reg_offset2 = 0; 627 break; 628 case MES_MISC_OP_WRM_REG_WR_WAIT: 629 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 630 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 631 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 632 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 633 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 634 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 635 break; 636 case MES_MISC_OP_SET_SHADER_DEBUGGER: 637 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 638 misc_pkt.set_shader_debugger.process_context_addr = 639 input->set_shader_debugger.process_context_addr; 640 misc_pkt.set_shader_debugger.flags.u32all = 641 input->set_shader_debugger.flags.u32all; 642 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 643 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 644 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 645 input->set_shader_debugger.tcp_watch_cntl, 646 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 647 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 648 break; 649 case MES_MISC_OP_CHANGE_CONFIG: 650 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 651 dev_err(mes->adev->dev, "MES FW versoin must be larger than 0x63 to support limit single process feature.\n"); 652 return -EINVAL; 653 } 654 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 655 misc_pkt.change_config.opcode = 656 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 657 misc_pkt.change_config.option.bits.limit_single_process = 658 input->change_config.option.limit_single_process; 659 break; 660 661 default: 662 DRM_ERROR("unsupported misc op (%d) \n", input->op); 663 return -EINVAL; 664 } 665 666 return mes_v11_0_submit_pkt_and_poll_completion(mes, 667 &misc_pkt, sizeof(misc_pkt), 668 offsetof(union MESAPI__MISC, api_status)); 669 } 670 671 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 672 { 673 int i; 674 struct amdgpu_device *adev = mes->adev; 675 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 676 677 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 678 679 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 680 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 681 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 682 683 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 684 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 685 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 686 mes_set_hw_res_pkt.paging_vmid = 0; 687 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 688 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 689 mes->query_status_fence_gpu_addr[0]; 690 691 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 692 mes_set_hw_res_pkt.compute_hqd_mask[i] = 693 mes->compute_hqd_mask[i]; 694 695 for (i = 0; i < MAX_GFX_PIPES; i++) 696 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 697 698 for (i = 0; i < MAX_SDMA_PIPES; i++) 699 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 700 701 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 702 mes_set_hw_res_pkt.aggregated_doorbells[i] = 703 mes->aggregated_doorbells[i]; 704 705 for (i = 0; i < 5; i++) { 706 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 707 mes_set_hw_res_pkt.mmhub_base[i] = 708 adev->reg_offset[MMHUB_HWIP][0][i]; 709 mes_set_hw_res_pkt.osssys_base[i] = 710 adev->reg_offset[OSSSYS_HWIP][0][i]; 711 } 712 713 mes_set_hw_res_pkt.disable_reset = 1; 714 mes_set_hw_res_pkt.disable_mes_log = 1; 715 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 716 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 717 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 718 mes_set_hw_res_pkt.oversubscription_timer = 50; 719 if (amdgpu_mes_log_enable) { 720 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 721 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 722 mes->event_log_gpu_addr; 723 } 724 725 if (enforce_isolation) 726 mes_set_hw_res_pkt.limit_single_process = 1; 727 728 return mes_v11_0_submit_pkt_and_poll_completion(mes, 729 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 730 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 731 } 732 733 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 734 { 735 int size = 128 * PAGE_SIZE; 736 int ret = 0; 737 struct amdgpu_device *adev = mes->adev; 738 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 739 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 740 741 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 742 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 743 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 744 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 745 746 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 747 AMDGPU_GEM_DOMAIN_VRAM, 748 &mes->resource_1, 749 &mes->resource_1_gpu_addr, 750 &mes->resource_1_addr); 751 if (ret) { 752 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 753 return ret; 754 } 755 756 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 757 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 758 return mes_v11_0_submit_pkt_and_poll_completion(mes, 759 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 760 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 761 } 762 763 static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes, 764 struct mes_reset_legacy_queue_input *input) 765 { 766 union MESAPI__RESET mes_reset_queue_pkt; 767 768 if (input->use_mmio) 769 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 770 input->me_id, input->pipe_id, 771 input->queue_id, input->vmid); 772 773 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 774 775 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 776 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 777 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 778 779 mes_reset_queue_pkt.queue_type = 780 convert_to_mes_queue_type(input->queue_type); 781 782 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 783 mes_reset_queue_pkt.reset_legacy_gfx = 1; 784 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 785 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 786 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 787 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 788 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 789 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 790 } else { 791 mes_reset_queue_pkt.reset_queue_only = 1; 792 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 793 } 794 795 return mes_v11_0_submit_pkt_and_poll_completion(mes, 796 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 797 offsetof(union MESAPI__RESET, api_status)); 798 } 799 800 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 801 .add_hw_queue = mes_v11_0_add_hw_queue, 802 .remove_hw_queue = mes_v11_0_remove_hw_queue, 803 .map_legacy_queue = mes_v11_0_map_legacy_queue, 804 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 805 .suspend_gang = mes_v11_0_suspend_gang, 806 .resume_gang = mes_v11_0_resume_gang, 807 .misc_op = mes_v11_0_misc_op, 808 .reset_legacy_queue = mes_v11_0_reset_legacy_queue, 809 .reset_hw_queue = mes_v11_0_reset_hw_queue, 810 }; 811 812 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 813 enum admgpu_mes_pipe pipe) 814 { 815 int r; 816 const struct mes_firmware_header_v1_0 *mes_hdr; 817 const __le32 *fw_data; 818 unsigned fw_size; 819 820 mes_hdr = (const struct mes_firmware_header_v1_0 *) 821 adev->mes.fw[pipe]->data; 822 823 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 824 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 825 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 826 827 r = amdgpu_bo_create_reserved(adev, fw_size, 828 PAGE_SIZE, 829 AMDGPU_GEM_DOMAIN_VRAM | 830 AMDGPU_GEM_DOMAIN_GTT, 831 &adev->mes.ucode_fw_obj[pipe], 832 &adev->mes.ucode_fw_gpu_addr[pipe], 833 (void **)&adev->mes.ucode_fw_ptr[pipe]); 834 if (r) { 835 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 836 return r; 837 } 838 839 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 840 841 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 842 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 843 844 return 0; 845 } 846 847 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 848 enum admgpu_mes_pipe pipe) 849 { 850 int r; 851 const struct mes_firmware_header_v1_0 *mes_hdr; 852 const __le32 *fw_data; 853 unsigned fw_size; 854 855 mes_hdr = (const struct mes_firmware_header_v1_0 *) 856 adev->mes.fw[pipe]->data; 857 858 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 859 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 860 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 861 862 if (fw_size > GFX_MES_DRAM_SIZE) { 863 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 864 pipe, fw_size, GFX_MES_DRAM_SIZE); 865 return -EINVAL; 866 } 867 868 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 869 64 * 1024, 870 AMDGPU_GEM_DOMAIN_VRAM | 871 AMDGPU_GEM_DOMAIN_GTT, 872 &adev->mes.data_fw_obj[pipe], 873 &adev->mes.data_fw_gpu_addr[pipe], 874 (void **)&adev->mes.data_fw_ptr[pipe]); 875 if (r) { 876 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 877 return r; 878 } 879 880 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 881 882 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 883 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 884 885 return 0; 886 } 887 888 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 889 enum admgpu_mes_pipe pipe) 890 { 891 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 892 &adev->mes.data_fw_gpu_addr[pipe], 893 (void **)&adev->mes.data_fw_ptr[pipe]); 894 895 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 896 &adev->mes.ucode_fw_gpu_addr[pipe], 897 (void **)&adev->mes.ucode_fw_ptr[pipe]); 898 } 899 900 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 901 { 902 int pipe; 903 904 /* get MES scheduler/KIQ versions */ 905 mutex_lock(&adev->srbm_mutex); 906 907 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 908 soc21_grbm_select(adev, 3, pipe, 0, 0); 909 910 if (pipe == AMDGPU_MES_SCHED_PIPE) 911 adev->mes.sched_version = 912 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 913 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 914 adev->mes.kiq_version = 915 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 916 } 917 918 soc21_grbm_select(adev, 0, 0, 0, 0); 919 mutex_unlock(&adev->srbm_mutex); 920 } 921 922 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 923 { 924 uint64_t ucode_addr; 925 uint32_t pipe, data = 0; 926 927 if (enable) { 928 if (amdgpu_mes_log_enable) { 929 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 930 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 931 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 932 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 933 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 934 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 935 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 936 } 937 938 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 939 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 940 data = REG_SET_FIELD(data, CP_MES_CNTL, 941 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 942 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 943 944 mutex_lock(&adev->srbm_mutex); 945 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 946 if (!adev->enable_mes_kiq && 947 pipe == AMDGPU_MES_KIQ_PIPE) 948 continue; 949 950 soc21_grbm_select(adev, 3, pipe, 0, 0); 951 952 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 953 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 954 lower_32_bits(ucode_addr)); 955 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 956 upper_32_bits(ucode_addr)); 957 } 958 soc21_grbm_select(adev, 0, 0, 0, 0); 959 mutex_unlock(&adev->srbm_mutex); 960 961 /* unhalt MES and activate pipe0 */ 962 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 963 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 964 adev->enable_mes_kiq ? 1 : 0); 965 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 966 967 if (amdgpu_emu_mode) 968 msleep(100); 969 else 970 udelay(500); 971 } else { 972 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 973 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 974 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 975 data = REG_SET_FIELD(data, CP_MES_CNTL, 976 MES_INVALIDATE_ICACHE, 1); 977 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 978 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 979 adev->enable_mes_kiq ? 1 : 0); 980 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 981 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 982 } 983 } 984 985 /* This function is for backdoor MES firmware */ 986 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 987 enum admgpu_mes_pipe pipe, bool prime_icache) 988 { 989 int r; 990 uint32_t data; 991 uint64_t ucode_addr; 992 993 mes_v11_0_enable(adev, false); 994 995 if (!adev->mes.fw[pipe]) 996 return -EINVAL; 997 998 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 999 if (r) 1000 return r; 1001 1002 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1003 if (r) { 1004 mes_v11_0_free_ucode_buffers(adev, pipe); 1005 return r; 1006 } 1007 1008 mutex_lock(&adev->srbm_mutex); 1009 /* me=3, pipe=0, queue=0 */ 1010 soc21_grbm_select(adev, 3, pipe, 0, 0); 1011 1012 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1013 1014 /* set ucode start address */ 1015 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1016 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1017 lower_32_bits(ucode_addr)); 1018 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1019 upper_32_bits(ucode_addr)); 1020 1021 /* set ucode fimrware address */ 1022 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1023 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1024 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1025 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1026 1027 /* set ucode instruction cache boundary to 2M-1 */ 1028 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1029 1030 /* set ucode data firmware address */ 1031 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1032 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1033 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1034 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1035 1036 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1037 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1038 1039 if (prime_icache) { 1040 /* invalidate ICACHE */ 1041 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1042 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1043 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1044 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1045 1046 /* prime the ICACHE. */ 1047 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1048 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1049 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1050 } 1051 1052 soc21_grbm_select(adev, 0, 0, 0, 0); 1053 mutex_unlock(&adev->srbm_mutex); 1054 1055 return 0; 1056 } 1057 1058 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1059 enum admgpu_mes_pipe pipe) 1060 { 1061 int r; 1062 u32 *eop; 1063 1064 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1065 AMDGPU_GEM_DOMAIN_GTT, 1066 &adev->mes.eop_gpu_obj[pipe], 1067 &adev->mes.eop_gpu_addr[pipe], 1068 (void **)&eop); 1069 if (r) { 1070 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1071 return r; 1072 } 1073 1074 memset(eop, 0, 1075 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1076 1077 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1078 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1079 1080 return 0; 1081 } 1082 1083 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1084 { 1085 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1086 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1087 uint32_t tmp; 1088 1089 memset(mqd, 0, sizeof(*mqd)); 1090 1091 mqd->header = 0xC0310800; 1092 mqd->compute_pipelinestat_enable = 0x00000001; 1093 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1094 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1095 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1096 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1097 mqd->compute_misc_reserved = 0x00000007; 1098 1099 eop_base_addr = ring->eop_gpu_addr >> 8; 1100 1101 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1102 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1103 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1104 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1105 1106 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1107 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1108 mqd->cp_hqd_eop_control = tmp; 1109 1110 /* disable the queue if it's active */ 1111 ring->wptr = 0; 1112 mqd->cp_hqd_pq_rptr = 0; 1113 mqd->cp_hqd_pq_wptr_lo = 0; 1114 mqd->cp_hqd_pq_wptr_hi = 0; 1115 1116 /* set the pointer to the MQD */ 1117 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1118 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1119 1120 /* set MQD vmid to 0 */ 1121 tmp = regCP_MQD_CONTROL_DEFAULT; 1122 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1123 mqd->cp_mqd_control = tmp; 1124 1125 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1126 hqd_gpu_addr = ring->gpu_addr >> 8; 1127 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1128 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1129 1130 /* set the wb address whether it's enabled or not */ 1131 wb_gpu_addr = ring->rptr_gpu_addr; 1132 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1133 mqd->cp_hqd_pq_rptr_report_addr_hi = 1134 upper_32_bits(wb_gpu_addr) & 0xffff; 1135 1136 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1137 wb_gpu_addr = ring->wptr_gpu_addr; 1138 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1139 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1140 1141 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1142 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1143 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1144 (order_base_2(ring->ring_size / 4) - 1)); 1145 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1146 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1147 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1148 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1149 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1150 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1151 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1152 mqd->cp_hqd_pq_control = tmp; 1153 1154 /* enable doorbell */ 1155 tmp = 0; 1156 if (ring->use_doorbell) { 1157 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1158 DOORBELL_OFFSET, ring->doorbell_index); 1159 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1160 DOORBELL_EN, 1); 1161 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1162 DOORBELL_SOURCE, 0); 1163 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1164 DOORBELL_HIT, 0); 1165 } else 1166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1167 DOORBELL_EN, 0); 1168 mqd->cp_hqd_pq_doorbell_control = tmp; 1169 1170 mqd->cp_hqd_vmid = 0; 1171 /* activate the queue */ 1172 mqd->cp_hqd_active = 1; 1173 1174 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1175 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1176 PRELOAD_SIZE, 0x55); 1177 mqd->cp_hqd_persistent_state = tmp; 1178 1179 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1180 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1181 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1182 1183 amdgpu_device_flush_hdp(ring->adev, NULL); 1184 return 0; 1185 } 1186 1187 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1188 { 1189 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1190 struct amdgpu_device *adev = ring->adev; 1191 uint32_t data = 0; 1192 1193 mutex_lock(&adev->srbm_mutex); 1194 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1195 1196 /* set CP_HQD_VMID.VMID = 0. */ 1197 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1198 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1199 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1200 1201 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1202 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1203 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1204 DOORBELL_EN, 0); 1205 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1206 1207 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1208 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1209 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1210 1211 /* set CP_MQD_CONTROL.VMID=0 */ 1212 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1213 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1214 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1215 1216 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1217 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1218 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1219 1220 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1221 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1222 mqd->cp_hqd_pq_rptr_report_addr_lo); 1223 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1224 mqd->cp_hqd_pq_rptr_report_addr_hi); 1225 1226 /* set CP_HQD_PQ_CONTROL */ 1227 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1228 1229 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1230 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1231 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1233 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1234 1235 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1236 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1237 mqd->cp_hqd_pq_doorbell_control); 1238 1239 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1240 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1241 1242 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1243 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1244 1245 soc21_grbm_select(adev, 0, 0, 0, 0); 1246 mutex_unlock(&adev->srbm_mutex); 1247 } 1248 1249 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1250 { 1251 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1252 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1253 int r; 1254 1255 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1256 return -EINVAL; 1257 1258 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1259 if (r) { 1260 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1261 return r; 1262 } 1263 1264 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1265 1266 return amdgpu_ring_test_helper(kiq_ring); 1267 } 1268 1269 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1270 enum admgpu_mes_pipe pipe) 1271 { 1272 struct amdgpu_ring *ring; 1273 int r; 1274 1275 if (pipe == AMDGPU_MES_KIQ_PIPE) 1276 ring = &adev->gfx.kiq[0].ring; 1277 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1278 ring = &adev->mes.ring[0]; 1279 else 1280 BUG(); 1281 1282 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1283 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1284 *(ring->wptr_cpu_addr) = 0; 1285 *(ring->rptr_cpu_addr) = 0; 1286 amdgpu_ring_clear_ring(ring); 1287 } 1288 1289 r = mes_v11_0_mqd_init(ring); 1290 if (r) 1291 return r; 1292 1293 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1294 r = mes_v11_0_kiq_enable_queue(adev); 1295 if (r) 1296 return r; 1297 } else { 1298 mes_v11_0_queue_init_register(ring); 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1305 { 1306 struct amdgpu_ring *ring; 1307 1308 ring = &adev->mes.ring[0]; 1309 1310 ring->funcs = &mes_v11_0_ring_funcs; 1311 1312 ring->me = 3; 1313 ring->pipe = 0; 1314 ring->queue = 0; 1315 1316 ring->ring_obj = NULL; 1317 ring->use_doorbell = true; 1318 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1319 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1320 ring->no_scheduler = true; 1321 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1322 1323 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1324 AMDGPU_RING_PRIO_DEFAULT, NULL); 1325 } 1326 1327 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1328 { 1329 struct amdgpu_ring *ring; 1330 1331 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1332 1333 ring = &adev->gfx.kiq[0].ring; 1334 1335 ring->me = 3; 1336 ring->pipe = 1; 1337 ring->queue = 0; 1338 1339 ring->adev = NULL; 1340 ring->ring_obj = NULL; 1341 ring->use_doorbell = true; 1342 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1343 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1344 ring->no_scheduler = true; 1345 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1346 ring->me, ring->pipe, ring->queue); 1347 1348 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1349 AMDGPU_RING_PRIO_DEFAULT, NULL); 1350 } 1351 1352 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1353 enum admgpu_mes_pipe pipe) 1354 { 1355 int r, mqd_size = sizeof(struct v11_compute_mqd); 1356 struct amdgpu_ring *ring; 1357 1358 if (pipe == AMDGPU_MES_KIQ_PIPE) 1359 ring = &adev->gfx.kiq[0].ring; 1360 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1361 ring = &adev->mes.ring[0]; 1362 else 1363 BUG(); 1364 1365 if (ring->mqd_obj) 1366 return 0; 1367 1368 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1369 AMDGPU_GEM_DOMAIN_VRAM | 1370 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1371 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1372 if (r) { 1373 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1374 return r; 1375 } 1376 1377 memset(ring->mqd_ptr, 0, mqd_size); 1378 1379 /* prepare MQD backup */ 1380 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1381 if (!adev->mes.mqd_backup[pipe]) { 1382 dev_warn(adev->dev, 1383 "no memory to create MQD backup for ring %s\n", 1384 ring->name); 1385 return -ENOMEM; 1386 } 1387 1388 return 0; 1389 } 1390 1391 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1392 { 1393 struct amdgpu_device *adev = ip_block->adev; 1394 int pipe, r; 1395 1396 adev->mes.funcs = &mes_v11_0_funcs; 1397 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1398 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1399 1400 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1401 1402 r = amdgpu_mes_init(adev); 1403 if (r) 1404 return r; 1405 1406 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1407 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1408 continue; 1409 1410 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1411 if (r) 1412 return r; 1413 1414 r = mes_v11_0_mqd_sw_init(adev, pipe); 1415 if (r) 1416 return r; 1417 } 1418 1419 if (adev->enable_mes_kiq) { 1420 r = mes_v11_0_kiq_ring_init(adev); 1421 if (r) 1422 return r; 1423 } 1424 1425 r = mes_v11_0_ring_init(adev); 1426 if (r) 1427 return r; 1428 1429 return 0; 1430 } 1431 1432 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1433 { 1434 struct amdgpu_device *adev = ip_block->adev; 1435 int pipe; 1436 1437 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1438 kfree(adev->mes.mqd_backup[pipe]); 1439 1440 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1441 &adev->mes.eop_gpu_addr[pipe], 1442 NULL); 1443 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1444 } 1445 1446 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1447 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1448 &adev->gfx.kiq[0].ring.mqd_ptr); 1449 1450 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1451 &adev->mes.ring[0].mqd_gpu_addr, 1452 &adev->mes.ring[0].mqd_ptr); 1453 1454 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1455 amdgpu_ring_fini(&adev->mes.ring[0]); 1456 1457 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1458 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1459 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1460 } 1461 1462 amdgpu_mes_fini(adev); 1463 return 0; 1464 } 1465 1466 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1467 { 1468 uint32_t data; 1469 int i; 1470 struct amdgpu_device *adev = ring->adev; 1471 1472 mutex_lock(&adev->srbm_mutex); 1473 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1474 1475 /* disable the queue if it's active */ 1476 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1477 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1478 for (i = 0; i < adev->usec_timeout; i++) { 1479 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1480 break; 1481 udelay(1); 1482 } 1483 } 1484 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1485 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1486 DOORBELL_EN, 0); 1487 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1488 DOORBELL_HIT, 1); 1489 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1490 1491 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1492 1493 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1494 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1495 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1496 1497 soc21_grbm_select(adev, 0, 0, 0, 0); 1498 mutex_unlock(&adev->srbm_mutex); 1499 } 1500 1501 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1502 { 1503 uint32_t tmp; 1504 struct amdgpu_device *adev = ring->adev; 1505 1506 /* tell RLC which is KIQ queue */ 1507 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1508 tmp &= 0xffffff00; 1509 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1510 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1511 } 1512 1513 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1514 { 1515 uint32_t tmp; 1516 1517 /* tell RLC which is KIQ dequeue */ 1518 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1519 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1520 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1521 } 1522 1523 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1524 { 1525 int r = 0; 1526 struct amdgpu_ip_block *ip_block; 1527 1528 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1529 1530 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1531 if (r) { 1532 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1533 return r; 1534 } 1535 1536 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1537 if (r) { 1538 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1539 return r; 1540 } 1541 1542 } 1543 1544 mes_v11_0_enable(adev, true); 1545 1546 mes_v11_0_get_fw_version(adev); 1547 1548 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1549 1550 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1551 if (unlikely(!ip_block)) { 1552 dev_err(adev->dev, "Failed to get MES handle\n"); 1553 return -EINVAL; 1554 } 1555 1556 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1557 if (r) 1558 goto failure; 1559 1560 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1561 adev->mes.enable_legacy_queue_map = true; 1562 else 1563 adev->mes.enable_legacy_queue_map = false; 1564 1565 if (adev->mes.enable_legacy_queue_map) { 1566 r = mes_v11_0_hw_init(ip_block); 1567 if (r) 1568 goto failure; 1569 } 1570 1571 return r; 1572 1573 failure: 1574 mes_v11_0_hw_fini(ip_block); 1575 return r; 1576 } 1577 1578 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1579 { 1580 if (adev->mes.ring[0].sched.ready) { 1581 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1582 adev->mes.ring[0].sched.ready = false; 1583 } 1584 1585 if (amdgpu_sriov_vf(adev)) { 1586 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1587 mes_v11_0_kiq_clear(adev); 1588 } 1589 1590 mes_v11_0_enable(adev, false); 1591 1592 return 0; 1593 } 1594 1595 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1596 { 1597 int r; 1598 struct amdgpu_device *adev = ip_block->adev; 1599 1600 if (adev->mes.ring[0].sched.ready) 1601 goto out; 1602 1603 if (!adev->enable_mes_kiq) { 1604 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1605 r = mes_v11_0_load_microcode(adev, 1606 AMDGPU_MES_SCHED_PIPE, true); 1607 if (r) { 1608 DRM_ERROR("failed to MES fw, r=%d\n", r); 1609 return r; 1610 } 1611 } 1612 1613 mes_v11_0_enable(adev, true); 1614 } 1615 1616 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1617 if (r) 1618 goto failure; 1619 1620 r = mes_v11_0_set_hw_resources(&adev->mes); 1621 if (r) 1622 goto failure; 1623 1624 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1625 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1626 if (r) { 1627 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1628 goto failure; 1629 } 1630 } 1631 1632 r = mes_v11_0_query_sched_status(&adev->mes); 1633 if (r) { 1634 DRM_ERROR("MES is busy\n"); 1635 goto failure; 1636 } 1637 1638 out: 1639 /* 1640 * Disable KIQ ring usage from the driver once MES is enabled. 1641 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1642 * with MES enabled. 1643 */ 1644 adev->gfx.kiq[0].ring.sched.ready = false; 1645 adev->mes.ring[0].sched.ready = true; 1646 1647 return 0; 1648 1649 failure: 1650 mes_v11_0_hw_fini(ip_block); 1651 return r; 1652 } 1653 1654 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1655 { 1656 struct amdgpu_device *adev = ip_block->adev; 1657 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1658 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1659 &adev->mes.resource_1_addr); 1660 } 1661 return 0; 1662 } 1663 1664 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1665 { 1666 int r; 1667 1668 r = amdgpu_mes_suspend(ip_block->adev); 1669 if (r) 1670 return r; 1671 1672 return mes_v11_0_hw_fini(ip_block); 1673 } 1674 1675 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1676 { 1677 int r; 1678 1679 r = mes_v11_0_hw_init(ip_block); 1680 if (r) 1681 return r; 1682 1683 return amdgpu_mes_resume(ip_block->adev); 1684 } 1685 1686 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1687 { 1688 struct amdgpu_device *adev = ip_block->adev; 1689 int pipe, r; 1690 1691 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1692 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1693 continue; 1694 r = amdgpu_mes_init_microcode(adev, pipe); 1695 if (r) 1696 return r; 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int mes_v11_0_late_init(struct amdgpu_ip_block *ip_block) 1703 { 1704 struct amdgpu_device *adev = ip_block->adev; 1705 1706 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1707 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1708 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1709 amdgpu_mes_self_test(adev); 1710 1711 return 0; 1712 } 1713 1714 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1715 .name = "mes_v11_0", 1716 .early_init = mes_v11_0_early_init, 1717 .late_init = mes_v11_0_late_init, 1718 .sw_init = mes_v11_0_sw_init, 1719 .sw_fini = mes_v11_0_sw_fini, 1720 .hw_init = mes_v11_0_hw_init, 1721 .hw_fini = mes_v11_0_hw_fini, 1722 .suspend = mes_v11_0_suspend, 1723 .resume = mes_v11_0_resume, 1724 }; 1725 1726 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1727 .type = AMD_IP_BLOCK_TYPE_MES, 1728 .major = 11, 1729 .minor = 0, 1730 .rev = 0, 1731 .funcs = &mes_v11_0_ip_funcs, 1732 }; 1733