1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 62 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 63 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 64 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 65 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 66 67 #define MES_EOP_SIZE 2048 68 #define GFX_MES_DRAM_SIZE 0x80000 69 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 70 71 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 72 #define MES11_HUNG_HQD_INFO_OFFSET 4 73 74 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 75 { 76 struct amdgpu_device *adev = ring->adev; 77 78 if (ring->use_doorbell) { 79 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 80 ring->wptr); 81 WDOORBELL64(ring->doorbell_index, ring->wptr); 82 } else { 83 BUG(); 84 } 85 } 86 87 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 88 { 89 return *ring->rptr_cpu_addr; 90 } 91 92 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 93 { 94 u64 wptr; 95 96 if (ring->use_doorbell) 97 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 98 else 99 BUG(); 100 return wptr; 101 } 102 103 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 104 .type = AMDGPU_RING_TYPE_MES, 105 .align_mask = 1, 106 .nop = 0, 107 .support_64bit_ptrs = true, 108 .get_rptr = mes_v11_0_ring_get_rptr, 109 .get_wptr = mes_v11_0_ring_get_wptr, 110 .set_wptr = mes_v11_0_ring_set_wptr, 111 .insert_nop = amdgpu_ring_insert_nop, 112 }; 113 114 static const char *mes_v11_0_opcodes[] = { 115 "SET_HW_RSRC", 116 "SET_SCHEDULING_CONFIG", 117 "ADD_QUEUE", 118 "REMOVE_QUEUE", 119 "PERFORM_YIELD", 120 "SET_GANG_PRIORITY_LEVEL", 121 "SUSPEND", 122 "RESUME", 123 "RESET", 124 "SET_LOG_BUFFER", 125 "CHANGE_GANG_PRORITY", 126 "QUERY_SCHEDULER_STATUS", 127 "PROGRAM_GDS", 128 "SET_DEBUG_VMID", 129 "MISC", 130 "UPDATE_ROOT_PAGE_TABLE", 131 "AMD_LOG", 132 "unused", 133 "unused", 134 "SET_HW_RSRC_1", 135 }; 136 137 static const char *mes_v11_0_misc_opcodes[] = { 138 "WRITE_REG", 139 "INV_GART", 140 "QUERY_STATUS", 141 "READ_REG", 142 "WAIT_REG_MEM", 143 "SET_SHADER_DEBUGGER", 144 }; 145 146 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 147 { 148 const char *op_str = NULL; 149 150 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 151 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 152 153 return op_str; 154 } 155 156 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 157 { 158 const char *op_str = NULL; 159 160 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 161 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 162 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 163 164 return op_str; 165 } 166 167 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 168 void *pkt, int size, 169 int api_status_off) 170 { 171 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 172 signed long timeout = 2100000; /* 2100 ms */ 173 struct amdgpu_device *adev = mes->adev; 174 struct amdgpu_ring *ring = &mes->ring[0]; 175 struct MES_API_STATUS *api_status; 176 union MESAPI__MISC *x_pkt = pkt; 177 const char *op_str, *misc_op_str; 178 unsigned long flags; 179 u64 status_gpu_addr; 180 u32 seq, status_offset; 181 u64 *status_ptr; 182 signed long r; 183 int ret; 184 185 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 186 return -EINVAL; 187 188 if (amdgpu_emu_mode) { 189 timeout *= 100; 190 } else if (amdgpu_sriov_vf(adev)) { 191 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 192 timeout = 15 * 600 * 1000; 193 } 194 195 ret = amdgpu_device_wb_get(adev, &status_offset); 196 if (ret) 197 return ret; 198 199 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 200 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 201 *status_ptr = 0; 202 203 spin_lock_irqsave(&mes->ring_lock[0], flags); 204 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 205 if (r) 206 goto error_unlock_free; 207 208 seq = ++ring->fence_drv.sync_seq; 209 r = amdgpu_fence_wait_polling(ring, 210 seq - ring->fence_drv.num_fences_mask, 211 timeout); 212 if (r < 1) 213 goto error_undo; 214 215 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 216 api_status->api_completion_fence_addr = status_gpu_addr; 217 api_status->api_completion_fence_value = 1; 218 219 amdgpu_ring_write_multiple(ring, pkt, size / 4); 220 221 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 222 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 223 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 224 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 225 mes_status_pkt.api_status.api_completion_fence_addr = 226 ring->fence_drv.gpu_addr; 227 mes_status_pkt.api_status.api_completion_fence_value = seq; 228 229 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 230 sizeof(mes_status_pkt) / 4); 231 232 amdgpu_ring_commit(ring); 233 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 234 235 op_str = mes_v11_0_get_op_string(x_pkt); 236 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 237 238 if (misc_op_str) 239 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 240 misc_op_str); 241 else if (op_str) 242 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 243 else 244 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 245 x_pkt->header.opcode); 246 247 r = amdgpu_fence_wait_polling(ring, seq, timeout); 248 if (r < 1 || !*status_ptr) { 249 250 if (misc_op_str) 251 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 252 op_str, misc_op_str); 253 else if (op_str) 254 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 255 op_str); 256 else 257 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 258 x_pkt->header.opcode); 259 260 while (halt_if_hws_hang) 261 schedule(); 262 263 r = -ETIMEDOUT; 264 goto error_wb_free; 265 } 266 267 amdgpu_device_wb_free(adev, status_offset); 268 return 0; 269 270 error_undo: 271 dev_err(adev->dev, "MES ring buffer is full.\n"); 272 amdgpu_ring_undo(ring); 273 274 error_unlock_free: 275 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 276 277 error_wb_free: 278 amdgpu_device_wb_free(adev, status_offset); 279 return r; 280 } 281 282 static int convert_to_mes_queue_type(int queue_type) 283 { 284 if (queue_type == AMDGPU_RING_TYPE_GFX) 285 return MES_QUEUE_TYPE_GFX; 286 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 287 return MES_QUEUE_TYPE_COMPUTE; 288 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 289 return MES_QUEUE_TYPE_SDMA; 290 else 291 BUG(); 292 return -1; 293 } 294 295 static int convert_to_mes_priority_level(int priority_level) 296 { 297 switch (priority_level) { 298 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 299 return AMD_PRIORITY_LEVEL_LOW; 300 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 301 default: 302 return AMD_PRIORITY_LEVEL_NORMAL; 303 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 304 return AMD_PRIORITY_LEVEL_MEDIUM; 305 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 306 return AMD_PRIORITY_LEVEL_HIGH; 307 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 308 return AMD_PRIORITY_LEVEL_REALTIME; 309 } 310 } 311 312 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 313 struct mes_add_queue_input *input) 314 { 315 struct amdgpu_device *adev = mes->adev; 316 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 317 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 318 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 319 320 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 321 322 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 323 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 324 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 325 326 mes_add_queue_pkt.process_id = input->process_id; 327 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 328 mes_add_queue_pkt.process_va_start = input->process_va_start; 329 mes_add_queue_pkt.process_va_end = input->process_va_end; 330 mes_add_queue_pkt.process_quantum = input->process_quantum; 331 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 332 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 333 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 334 mes_add_queue_pkt.inprocess_gang_priority = 335 convert_to_mes_priority_level(input->inprocess_gang_priority); 336 mes_add_queue_pkt.gang_global_priority_level = 337 convert_to_mes_priority_level(input->gang_global_priority_level); 338 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 339 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 340 341 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 342 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 343 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 344 else 345 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 346 347 mes_add_queue_pkt.queue_type = 348 convert_to_mes_queue_type(input->queue_type); 349 mes_add_queue_pkt.paging = input->paging; 350 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 351 mes_add_queue_pkt.gws_base = input->gws_base; 352 mes_add_queue_pkt.gws_size = input->gws_size; 353 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 354 mes_add_queue_pkt.tma_addr = input->tma_addr; 355 mes_add_queue_pkt.trap_en = input->trap_en; 356 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 357 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 358 359 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 360 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 361 mes_add_queue_pkt.gds_size = input->queue_size; 362 363 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 364 365 return mes_v11_0_submit_pkt_and_poll_completion(mes, 366 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 367 offsetof(union MESAPI__ADD_QUEUE, api_status)); 368 } 369 370 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 371 struct mes_remove_queue_input *input) 372 { 373 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 374 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 375 376 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 377 378 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 379 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 380 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 381 382 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 383 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 384 385 if (mes_rev >= 0x60) 386 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 387 388 return mes_v11_0_submit_pkt_and_poll_completion(mes, 389 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 390 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 391 } 392 393 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 394 uint32_t me_id, uint32_t pipe_id, 395 uint32_t queue_id, uint32_t vmid) 396 { 397 struct amdgpu_device *adev = mes->adev; 398 uint32_t value, reg; 399 int i, r = 0; 400 401 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 402 403 if (queue_type == AMDGPU_RING_TYPE_GFX) { 404 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 405 me_id, pipe_id, queue_id, vmid); 406 407 mutex_lock(&adev->gfx.reset_sem_mutex); 408 gfx_v11_0_request_gfx_index_mutex(adev, true); 409 /* all se allow writes */ 410 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 411 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 412 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 413 if (pipe_id == 0) 414 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 415 else 416 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 417 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 418 gfx_v11_0_request_gfx_index_mutex(adev, false); 419 mutex_unlock(&adev->gfx.reset_sem_mutex); 420 421 mutex_lock(&adev->srbm_mutex); 422 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 423 /* wait till dequeue take effects */ 424 for (i = 0; i < adev->usec_timeout; i++) { 425 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 426 break; 427 udelay(1); 428 } 429 if (i >= adev->usec_timeout) { 430 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 431 r = -ETIMEDOUT; 432 } 433 434 soc21_grbm_select(adev, 0, 0, 0, 0); 435 mutex_unlock(&adev->srbm_mutex); 436 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 437 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 438 me_id, pipe_id, queue_id); 439 mutex_lock(&adev->srbm_mutex); 440 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 441 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 442 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 443 444 /* wait till dequeue take effects */ 445 for (i = 0; i < adev->usec_timeout; i++) { 446 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 447 break; 448 udelay(1); 449 } 450 if (i >= adev->usec_timeout) { 451 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 452 r = -ETIMEDOUT; 453 } 454 soc21_grbm_select(adev, 0, 0, 0, 0); 455 mutex_unlock(&adev->srbm_mutex); 456 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 457 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 458 me_id, pipe_id, queue_id); 459 switch (me_id) { 460 case 1: 461 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 462 break; 463 case 0: 464 default: 465 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 466 break; 467 } 468 469 value = 1 << queue_id; 470 WREG32(reg, value); 471 /* wait for queue reset done */ 472 for (i = 0; i < adev->usec_timeout; i++) { 473 if (!(RREG32(reg) & value)) 474 break; 475 udelay(1); 476 } 477 if (i >= adev->usec_timeout) { 478 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 479 r = -ETIMEDOUT; 480 } 481 } 482 483 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 484 return r; 485 } 486 487 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 488 struct mes_map_legacy_queue_input *input) 489 { 490 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 491 492 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 493 494 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 495 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 496 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 497 498 mes_add_queue_pkt.pipe_id = input->pipe_id; 499 mes_add_queue_pkt.queue_id = input->queue_id; 500 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 501 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 502 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 503 mes_add_queue_pkt.queue_type = 504 convert_to_mes_queue_type(input->queue_type); 505 mes_add_queue_pkt.map_legacy_kq = 1; 506 507 return mes_v11_0_submit_pkt_and_poll_completion(mes, 508 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 509 offsetof(union MESAPI__ADD_QUEUE, api_status)); 510 } 511 512 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 513 struct mes_unmap_legacy_queue_input *input) 514 { 515 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 516 517 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 518 519 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 520 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 521 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 522 523 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 524 mes_remove_queue_pkt.gang_context_addr = 0; 525 526 mes_remove_queue_pkt.pipe_id = input->pipe_id; 527 mes_remove_queue_pkt.queue_id = input->queue_id; 528 529 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 530 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 531 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 532 mes_remove_queue_pkt.tf_data = 533 lower_32_bits(input->trail_fence_data); 534 } else { 535 mes_remove_queue_pkt.unmap_legacy_queue = 1; 536 mes_remove_queue_pkt.queue_type = 537 convert_to_mes_queue_type(input->queue_type); 538 } 539 540 return mes_v11_0_submit_pkt_and_poll_completion(mes, 541 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 542 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 543 } 544 545 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 546 struct mes_suspend_gang_input *input) 547 { 548 union MESAPI__SUSPEND mes_suspend_gang_pkt; 549 550 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 551 552 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 553 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 554 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 555 556 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 557 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 558 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 559 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 560 561 return mes_v11_0_submit_pkt_and_poll_completion(mes, 562 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 563 offsetof(union MESAPI__SUSPEND, api_status)); 564 } 565 566 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 567 struct mes_resume_gang_input *input) 568 { 569 union MESAPI__RESUME mes_resume_gang_pkt; 570 571 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 572 573 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 574 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 575 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 576 577 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 578 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 579 580 return mes_v11_0_submit_pkt_and_poll_completion(mes, 581 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 582 offsetof(union MESAPI__RESUME, api_status)); 583 } 584 585 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 586 { 587 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 588 589 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 590 591 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 592 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 593 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 594 595 return mes_v11_0_submit_pkt_and_poll_completion(mes, 596 &mes_status_pkt, sizeof(mes_status_pkt), 597 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 598 } 599 600 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 601 struct mes_misc_op_input *input) 602 { 603 union MESAPI__MISC misc_pkt; 604 605 memset(&misc_pkt, 0, sizeof(misc_pkt)); 606 607 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 608 misc_pkt.header.opcode = MES_SCH_API_MISC; 609 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 610 611 switch (input->op) { 612 case MES_MISC_OP_READ_REG: 613 misc_pkt.opcode = MESAPI_MISC__READ_REG; 614 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 615 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 616 break; 617 case MES_MISC_OP_WRITE_REG: 618 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 619 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 620 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 621 break; 622 case MES_MISC_OP_WRM_REG_WAIT: 623 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 624 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 625 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 626 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 627 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 628 misc_pkt.wait_reg_mem.reg_offset2 = 0; 629 break; 630 case MES_MISC_OP_WRM_REG_WR_WAIT: 631 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 632 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 633 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 634 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 635 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 636 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 637 break; 638 case MES_MISC_OP_SET_SHADER_DEBUGGER: 639 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 640 misc_pkt.set_shader_debugger.process_context_addr = 641 input->set_shader_debugger.process_context_addr; 642 misc_pkt.set_shader_debugger.flags.u32all = 643 input->set_shader_debugger.flags.u32all; 644 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 645 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 646 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 647 input->set_shader_debugger.tcp_watch_cntl, 648 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 649 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 650 break; 651 case MES_MISC_OP_CHANGE_CONFIG: 652 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 653 dev_warn_once(mes->adev->dev, 654 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 655 return 0; 656 } 657 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 658 misc_pkt.change_config.opcode = 659 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 660 misc_pkt.change_config.option.bits.limit_single_process = 661 input->change_config.option.limit_single_process; 662 break; 663 664 default: 665 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 666 return -EINVAL; 667 } 668 669 return mes_v11_0_submit_pkt_and_poll_completion(mes, 670 &misc_pkt, sizeof(misc_pkt), 671 offsetof(union MESAPI__MISC, api_status)); 672 } 673 674 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 675 { 676 int i; 677 struct amdgpu_device *adev = mes->adev; 678 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 679 680 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 681 682 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 683 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 684 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 685 686 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 687 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 688 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 689 mes_set_hw_res_pkt.paging_vmid = 0; 690 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 691 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 692 mes->query_status_fence_gpu_addr[0]; 693 694 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 695 mes_set_hw_res_pkt.compute_hqd_mask[i] = 696 mes->compute_hqd_mask[i]; 697 698 for (i = 0; i < MAX_GFX_PIPES; i++) 699 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 700 mes->gfx_hqd_mask[i]; 701 702 for (i = 0; i < MAX_SDMA_PIPES; i++) 703 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 704 705 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 706 mes_set_hw_res_pkt.aggregated_doorbells[i] = 707 mes->aggregated_doorbells[i]; 708 709 for (i = 0; i < 5; i++) { 710 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 711 mes_set_hw_res_pkt.mmhub_base[i] = 712 adev->reg_offset[MMHUB_HWIP][0][i]; 713 mes_set_hw_res_pkt.osssys_base[i] = 714 adev->reg_offset[OSSSYS_HWIP][0][i]; 715 } 716 717 mes_set_hw_res_pkt.disable_reset = 1; 718 mes_set_hw_res_pkt.disable_mes_log = 1; 719 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 720 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 721 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 722 mes_set_hw_res_pkt.oversubscription_timer = 50; 723 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) 724 mes_set_hw_res_pkt.enable_lr_compute_wa = 1; 725 else 726 dev_info_once(mes->adev->dev, 727 "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); 728 729 if (amdgpu_mes_log_enable) { 730 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 731 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 732 mes->event_log_gpu_addr; 733 } 734 735 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 736 mes_set_hw_res_pkt.limit_single_process = 1; 737 738 return mes_v11_0_submit_pkt_and_poll_completion(mes, 739 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 740 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 741 } 742 743 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 744 { 745 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 746 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 747 748 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 749 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 750 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 751 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 752 753 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 754 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 755 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 756 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 757 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 758 } 759 760 return mes_v11_0_submit_pkt_and_poll_completion(mes, 761 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 762 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 763 } 764 765 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 766 struct mes_reset_queue_input *input) 767 { 768 union MESAPI__RESET mes_reset_queue_pkt; 769 770 if (input->use_mmio) 771 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 772 input->me_id, input->pipe_id, 773 input->queue_id, input->vmid); 774 775 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 776 777 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 778 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 779 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 780 781 mes_reset_queue_pkt.queue_type = 782 convert_to_mes_queue_type(input->queue_type); 783 784 if (input->legacy_gfx) { 785 mes_reset_queue_pkt.reset_legacy_gfx = 1; 786 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 787 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 788 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 789 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 790 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 791 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 792 } else { 793 mes_reset_queue_pkt.reset_queue_only = 1; 794 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 795 } 796 797 return mes_v11_0_submit_pkt_and_poll_completion(mes, 798 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 799 offsetof(union MESAPI__RESET, api_status)); 800 } 801 802 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 803 struct mes_detect_and_reset_queue_input *input) 804 { 805 union MESAPI__RESET mes_reset_queue_pkt; 806 807 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 808 809 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 810 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 811 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 812 813 mes_reset_queue_pkt.queue_type = 814 convert_to_mes_queue_type(input->queue_type); 815 mes_reset_queue_pkt.doorbell_offset_addr = 816 mes->hung_queue_db_array_gpu_addr[0]; 817 818 if (input->detect_only) 819 mes_reset_queue_pkt.hang_detect_only = 1; 820 else 821 mes_reset_queue_pkt.hang_detect_then_reset = 1; 822 823 return mes_v11_0_submit_pkt_and_poll_completion(mes, 824 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 825 offsetof(union MESAPI__RESET, api_status)); 826 } 827 828 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 829 .add_hw_queue = mes_v11_0_add_hw_queue, 830 .remove_hw_queue = mes_v11_0_remove_hw_queue, 831 .map_legacy_queue = mes_v11_0_map_legacy_queue, 832 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 833 .suspend_gang = mes_v11_0_suspend_gang, 834 .resume_gang = mes_v11_0_resume_gang, 835 .misc_op = mes_v11_0_misc_op, 836 .reset_hw_queue = mes_v11_0_reset_hw_queue, 837 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 838 }; 839 840 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 841 enum amdgpu_mes_pipe pipe) 842 { 843 int r; 844 const struct mes_firmware_header_v1_0 *mes_hdr; 845 const __le32 *fw_data; 846 unsigned fw_size; 847 848 mes_hdr = (const struct mes_firmware_header_v1_0 *) 849 adev->mes.fw[pipe]->data; 850 851 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 852 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 853 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 854 855 r = amdgpu_bo_create_reserved(adev, fw_size, 856 PAGE_SIZE, 857 AMDGPU_GEM_DOMAIN_VRAM | 858 AMDGPU_GEM_DOMAIN_GTT, 859 &adev->mes.ucode_fw_obj[pipe], 860 &adev->mes.ucode_fw_gpu_addr[pipe], 861 (void **)&adev->mes.ucode_fw_ptr[pipe]); 862 if (r) { 863 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 864 return r; 865 } 866 867 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 868 869 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 870 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 871 872 return 0; 873 } 874 875 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 876 enum amdgpu_mes_pipe pipe) 877 { 878 int r; 879 const struct mes_firmware_header_v1_0 *mes_hdr; 880 const __le32 *fw_data; 881 unsigned fw_size; 882 883 mes_hdr = (const struct mes_firmware_header_v1_0 *) 884 adev->mes.fw[pipe]->data; 885 886 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 887 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 888 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 889 890 if (fw_size > GFX_MES_DRAM_SIZE) { 891 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 892 pipe, fw_size, GFX_MES_DRAM_SIZE); 893 return -EINVAL; 894 } 895 896 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 897 64 * 1024, 898 AMDGPU_GEM_DOMAIN_VRAM | 899 AMDGPU_GEM_DOMAIN_GTT, 900 &adev->mes.data_fw_obj[pipe], 901 &adev->mes.data_fw_gpu_addr[pipe], 902 (void **)&adev->mes.data_fw_ptr[pipe]); 903 if (r) { 904 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 905 return r; 906 } 907 908 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 909 910 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 911 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 912 913 return 0; 914 } 915 916 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 917 enum amdgpu_mes_pipe pipe) 918 { 919 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 920 &adev->mes.data_fw_gpu_addr[pipe], 921 (void **)&adev->mes.data_fw_ptr[pipe]); 922 923 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 924 &adev->mes.ucode_fw_gpu_addr[pipe], 925 (void **)&adev->mes.ucode_fw_ptr[pipe]); 926 } 927 928 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 929 { 930 int pipe; 931 932 /* return early if we have already fetched these */ 933 if (adev->mes.sched_version && adev->mes.kiq_version) 934 return; 935 936 /* get MES scheduler/KIQ versions */ 937 mutex_lock(&adev->srbm_mutex); 938 939 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 940 soc21_grbm_select(adev, 3, pipe, 0, 0); 941 942 if (pipe == AMDGPU_MES_SCHED_PIPE) 943 adev->mes.sched_version = 944 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 945 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 946 adev->mes.kiq_version = 947 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 948 } 949 950 soc21_grbm_select(adev, 0, 0, 0, 0); 951 mutex_unlock(&adev->srbm_mutex); 952 } 953 954 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 955 { 956 uint64_t ucode_addr; 957 uint32_t pipe, data = 0; 958 959 if (enable) { 960 if (amdgpu_mes_log_enable) { 961 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 962 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 963 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 964 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 965 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 966 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 967 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 968 } 969 970 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 971 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 972 data = REG_SET_FIELD(data, CP_MES_CNTL, 973 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 974 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 975 976 mutex_lock(&adev->srbm_mutex); 977 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 978 if (!adev->enable_mes_kiq && 979 pipe == AMDGPU_MES_KIQ_PIPE) 980 continue; 981 982 soc21_grbm_select(adev, 3, pipe, 0, 0); 983 984 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 985 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 986 lower_32_bits(ucode_addr)); 987 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 988 upper_32_bits(ucode_addr)); 989 } 990 soc21_grbm_select(adev, 0, 0, 0, 0); 991 mutex_unlock(&adev->srbm_mutex); 992 993 /* unhalt MES and activate pipe0 */ 994 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 995 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 996 adev->enable_mes_kiq ? 1 : 0); 997 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 998 999 if (amdgpu_emu_mode) 1000 msleep(100); 1001 else 1002 udelay(500); 1003 } else { 1004 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1005 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1006 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1007 data = REG_SET_FIELD(data, CP_MES_CNTL, 1008 MES_INVALIDATE_ICACHE, 1); 1009 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1010 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1011 adev->enable_mes_kiq ? 1 : 0); 1012 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1013 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1014 } 1015 } 1016 1017 /* This function is for backdoor MES firmware */ 1018 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1019 enum amdgpu_mes_pipe pipe, bool prime_icache) 1020 { 1021 int r; 1022 uint32_t data; 1023 uint64_t ucode_addr; 1024 1025 mes_v11_0_enable(adev, false); 1026 1027 if (!adev->mes.fw[pipe]) 1028 return -EINVAL; 1029 1030 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1031 if (r) 1032 return r; 1033 1034 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1035 if (r) { 1036 mes_v11_0_free_ucode_buffers(adev, pipe); 1037 return r; 1038 } 1039 1040 mutex_lock(&adev->srbm_mutex); 1041 /* me=3, pipe=0, queue=0 */ 1042 soc21_grbm_select(adev, 3, pipe, 0, 0); 1043 1044 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1045 1046 /* set ucode start address */ 1047 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1048 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1049 lower_32_bits(ucode_addr)); 1050 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1051 upper_32_bits(ucode_addr)); 1052 1053 /* set ucode fimrware address */ 1054 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1055 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1056 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1057 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1058 1059 /* set ucode instruction cache boundary to 2M-1 */ 1060 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1061 1062 /* set ucode data firmware address */ 1063 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1064 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1065 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1066 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1067 1068 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1069 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1070 1071 if (prime_icache) { 1072 /* invalidate ICACHE */ 1073 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1074 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1075 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1076 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1077 1078 /* prime the ICACHE. */ 1079 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1080 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1081 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1082 } 1083 1084 soc21_grbm_select(adev, 0, 0, 0, 0); 1085 mutex_unlock(&adev->srbm_mutex); 1086 1087 return 0; 1088 } 1089 1090 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1091 enum amdgpu_mes_pipe pipe) 1092 { 1093 int r; 1094 u32 *eop; 1095 1096 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1097 AMDGPU_GEM_DOMAIN_GTT, 1098 &adev->mes.eop_gpu_obj[pipe], 1099 &adev->mes.eop_gpu_addr[pipe], 1100 (void **)&eop); 1101 if (r) { 1102 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1103 return r; 1104 } 1105 1106 memset(eop, 0, 1107 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1108 1109 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1110 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1111 1112 return 0; 1113 } 1114 1115 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1116 { 1117 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1118 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1119 uint32_t tmp; 1120 1121 memset(mqd, 0, sizeof(*mqd)); 1122 1123 mqd->header = 0xC0310800; 1124 mqd->compute_pipelinestat_enable = 0x00000001; 1125 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1126 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1127 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1128 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1129 mqd->compute_misc_reserved = 0x00000007; 1130 1131 eop_base_addr = ring->eop_gpu_addr >> 8; 1132 1133 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1134 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1135 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1136 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1137 1138 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1139 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1140 mqd->cp_hqd_eop_control = tmp; 1141 1142 /* disable the queue if it's active */ 1143 ring->wptr = 0; 1144 mqd->cp_hqd_pq_rptr = 0; 1145 mqd->cp_hqd_pq_wptr_lo = 0; 1146 mqd->cp_hqd_pq_wptr_hi = 0; 1147 1148 /* set the pointer to the MQD */ 1149 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1150 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1151 1152 /* set MQD vmid to 0 */ 1153 tmp = regCP_MQD_CONTROL_DEFAULT; 1154 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1155 mqd->cp_mqd_control = tmp; 1156 1157 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1158 hqd_gpu_addr = ring->gpu_addr >> 8; 1159 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1160 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1161 1162 /* set the wb address whether it's enabled or not */ 1163 wb_gpu_addr = ring->rptr_gpu_addr; 1164 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1165 mqd->cp_hqd_pq_rptr_report_addr_hi = 1166 upper_32_bits(wb_gpu_addr) & 0xffff; 1167 1168 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1169 wb_gpu_addr = ring->wptr_gpu_addr; 1170 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1171 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1172 1173 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1174 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1175 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1176 (order_base_2(ring->ring_size / 4) - 1)); 1177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1178 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1184 mqd->cp_hqd_pq_control = tmp; 1185 1186 /* enable doorbell */ 1187 tmp = 0; 1188 if (ring->use_doorbell) { 1189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1190 DOORBELL_OFFSET, ring->doorbell_index); 1191 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1192 DOORBELL_EN, 1); 1193 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1194 DOORBELL_SOURCE, 0); 1195 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1196 DOORBELL_HIT, 0); 1197 } else 1198 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1199 DOORBELL_EN, 0); 1200 mqd->cp_hqd_pq_doorbell_control = tmp; 1201 1202 mqd->cp_hqd_vmid = 0; 1203 /* activate the queue */ 1204 mqd->cp_hqd_active = 1; 1205 1206 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1207 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1208 PRELOAD_SIZE, 0x55); 1209 mqd->cp_hqd_persistent_state = tmp; 1210 1211 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1212 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1213 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1214 1215 amdgpu_device_flush_hdp(ring->adev, NULL); 1216 return 0; 1217 } 1218 1219 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1220 { 1221 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1222 struct amdgpu_device *adev = ring->adev; 1223 uint32_t data = 0; 1224 1225 mutex_lock(&adev->srbm_mutex); 1226 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1227 1228 /* set CP_HQD_VMID.VMID = 0. */ 1229 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1230 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1231 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1232 1233 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1234 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1235 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1236 DOORBELL_EN, 0); 1237 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1238 1239 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1240 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1241 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1242 1243 /* set CP_MQD_CONTROL.VMID=0 */ 1244 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1245 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1246 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1247 1248 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1249 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1250 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1251 1252 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1253 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1254 mqd->cp_hqd_pq_rptr_report_addr_lo); 1255 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1256 mqd->cp_hqd_pq_rptr_report_addr_hi); 1257 1258 /* set CP_HQD_PQ_CONTROL */ 1259 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1260 1261 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1262 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1263 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1264 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1265 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1266 1267 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1268 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1269 mqd->cp_hqd_pq_doorbell_control); 1270 1271 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1272 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1273 1274 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1275 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1276 1277 soc21_grbm_select(adev, 0, 0, 0, 0); 1278 mutex_unlock(&adev->srbm_mutex); 1279 } 1280 1281 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1282 { 1283 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1284 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1285 int r; 1286 1287 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1288 return -EINVAL; 1289 1290 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1291 if (r) { 1292 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1293 return r; 1294 } 1295 1296 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1297 1298 return amdgpu_ring_test_helper(kiq_ring); 1299 } 1300 1301 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1302 enum amdgpu_mes_pipe pipe) 1303 { 1304 struct amdgpu_ring *ring; 1305 int r; 1306 1307 if (pipe == AMDGPU_MES_KIQ_PIPE) 1308 ring = &adev->gfx.kiq[0].ring; 1309 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1310 ring = &adev->mes.ring[0]; 1311 else 1312 BUG(); 1313 1314 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1315 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1316 *(ring->wptr_cpu_addr) = 0; 1317 *(ring->rptr_cpu_addr) = 0; 1318 amdgpu_ring_clear_ring(ring); 1319 } 1320 1321 r = mes_v11_0_mqd_init(ring); 1322 if (r) 1323 return r; 1324 1325 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1326 r = mes_v11_0_kiq_enable_queue(adev); 1327 if (r) 1328 return r; 1329 } else { 1330 mes_v11_0_queue_init_register(ring); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1337 { 1338 struct amdgpu_ring *ring; 1339 1340 ring = &adev->mes.ring[0]; 1341 1342 ring->funcs = &mes_v11_0_ring_funcs; 1343 1344 ring->me = 3; 1345 ring->pipe = 0; 1346 ring->queue = 0; 1347 1348 ring->ring_obj = NULL; 1349 ring->use_doorbell = true; 1350 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1351 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1352 ring->no_scheduler = true; 1353 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1354 1355 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1356 AMDGPU_RING_PRIO_DEFAULT, NULL); 1357 } 1358 1359 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1360 { 1361 struct amdgpu_ring *ring; 1362 1363 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1364 1365 ring = &adev->gfx.kiq[0].ring; 1366 1367 ring->me = 3; 1368 ring->pipe = 1; 1369 ring->queue = 0; 1370 1371 ring->adev = NULL; 1372 ring->ring_obj = NULL; 1373 ring->use_doorbell = true; 1374 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1375 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1376 ring->no_scheduler = true; 1377 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1378 ring->me, ring->pipe, ring->queue); 1379 1380 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1381 AMDGPU_RING_PRIO_DEFAULT, NULL); 1382 } 1383 1384 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1385 enum amdgpu_mes_pipe pipe) 1386 { 1387 int r, mqd_size = sizeof(struct v11_compute_mqd); 1388 struct amdgpu_ring *ring; 1389 1390 if (pipe == AMDGPU_MES_KIQ_PIPE) 1391 ring = &adev->gfx.kiq[0].ring; 1392 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1393 ring = &adev->mes.ring[0]; 1394 else 1395 BUG(); 1396 1397 if (ring->mqd_obj) 1398 return 0; 1399 1400 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1401 AMDGPU_GEM_DOMAIN_VRAM | 1402 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1403 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1404 if (r) { 1405 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1406 return r; 1407 } 1408 1409 memset(ring->mqd_ptr, 0, mqd_size); 1410 1411 /* prepare MQD backup */ 1412 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1413 if (!adev->mes.mqd_backup[pipe]) { 1414 dev_warn(adev->dev, 1415 "no memory to create MQD backup for ring %s\n", 1416 ring->name); 1417 return -ENOMEM; 1418 } 1419 1420 return 0; 1421 } 1422 1423 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1424 { 1425 struct amdgpu_device *adev = ip_block->adev; 1426 int pipe, r, bo_size; 1427 1428 adev->mes.funcs = &mes_v11_0_funcs; 1429 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1430 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1431 1432 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1433 1434 r = amdgpu_mes_init(adev); 1435 if (r) 1436 return r; 1437 1438 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1439 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1440 continue; 1441 1442 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1443 if (r) 1444 return r; 1445 1446 r = mes_v11_0_mqd_sw_init(adev, pipe); 1447 if (r) 1448 return r; 1449 } 1450 1451 if (adev->enable_mes_kiq) { 1452 r = mes_v11_0_kiq_ring_init(adev); 1453 if (r) 1454 return r; 1455 } 1456 1457 r = mes_v11_0_ring_init(adev); 1458 if (r) 1459 return r; 1460 1461 bo_size = AMDGPU_GPU_PAGE_SIZE; 1462 if (amdgpu_sriov_is_mes_info_enable(adev)) 1463 bo_size += MES11_HW_RESOURCE_1_SIZE; 1464 1465 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1466 r = amdgpu_bo_create_kernel(adev, 1467 bo_size, 1468 PAGE_SIZE, 1469 AMDGPU_GEM_DOMAIN_VRAM, 1470 &adev->mes.resource_1[0], 1471 &adev->mes.resource_1_gpu_addr[0], 1472 &adev->mes.resource_1_addr[0]); 1473 if (r) { 1474 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1475 return r; 1476 } 1477 1478 return 0; 1479 } 1480 1481 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1482 { 1483 struct amdgpu_device *adev = ip_block->adev; 1484 int pipe; 1485 1486 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1487 &adev->mes.resource_1_addr[0]); 1488 1489 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1490 kfree(adev->mes.mqd_backup[pipe]); 1491 1492 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1493 &adev->mes.eop_gpu_addr[pipe], 1494 NULL); 1495 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1496 } 1497 1498 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1499 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1500 &adev->gfx.kiq[0].ring.mqd_ptr); 1501 1502 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1503 &adev->mes.ring[0].mqd_gpu_addr, 1504 &adev->mes.ring[0].mqd_ptr); 1505 1506 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1507 amdgpu_ring_fini(&adev->mes.ring[0]); 1508 1509 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1510 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1511 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1512 } 1513 1514 amdgpu_mes_fini(adev); 1515 return 0; 1516 } 1517 1518 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1519 { 1520 uint32_t data; 1521 int i; 1522 struct amdgpu_device *adev = ring->adev; 1523 1524 mutex_lock(&adev->srbm_mutex); 1525 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1526 1527 /* disable the queue if it's active */ 1528 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1529 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1530 for (i = 0; i < adev->usec_timeout; i++) { 1531 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1532 break; 1533 udelay(1); 1534 } 1535 } 1536 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1537 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1538 DOORBELL_EN, 0); 1539 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1540 DOORBELL_HIT, 1); 1541 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1542 1543 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1544 1545 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1546 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1547 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1548 1549 soc21_grbm_select(adev, 0, 0, 0, 0); 1550 mutex_unlock(&adev->srbm_mutex); 1551 } 1552 1553 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1554 { 1555 uint32_t tmp; 1556 struct amdgpu_device *adev = ring->adev; 1557 1558 /* tell RLC which is KIQ queue */ 1559 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1560 tmp &= 0xffffff00; 1561 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1562 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1563 } 1564 1565 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1566 { 1567 uint32_t tmp; 1568 1569 /* tell RLC which is KIQ dequeue */ 1570 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1571 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1572 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1573 } 1574 1575 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1576 { 1577 int r = 0; 1578 struct amdgpu_ip_block *ip_block; 1579 1580 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1581 1582 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1583 if (r) { 1584 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1585 return r; 1586 } 1587 1588 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1589 if (r) { 1590 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1591 return r; 1592 } 1593 1594 } 1595 1596 mes_v11_0_enable(adev, true); 1597 1598 mes_v11_0_get_fw_version(adev); 1599 1600 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1601 1602 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1603 if (unlikely(!ip_block)) { 1604 dev_err(adev->dev, "Failed to get MES handle\n"); 1605 return -EINVAL; 1606 } 1607 1608 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1609 if (r) 1610 goto failure; 1611 1612 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1613 adev->mes.enable_legacy_queue_map = true; 1614 else 1615 adev->mes.enable_legacy_queue_map = false; 1616 1617 if (adev->mes.enable_legacy_queue_map) { 1618 r = mes_v11_0_hw_init(ip_block); 1619 if (r) 1620 goto failure; 1621 } 1622 1623 return r; 1624 1625 failure: 1626 mes_v11_0_hw_fini(ip_block); 1627 return r; 1628 } 1629 1630 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1631 { 1632 if (adev->mes.ring[0].sched.ready) { 1633 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1634 adev->mes.ring[0].sched.ready = false; 1635 } 1636 1637 if (amdgpu_sriov_vf(adev)) { 1638 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1639 mes_v11_0_kiq_clear(adev); 1640 } 1641 1642 mes_v11_0_enable(adev, false); 1643 1644 return 0; 1645 } 1646 1647 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1648 { 1649 int r; 1650 struct amdgpu_device *adev = ip_block->adev; 1651 1652 if (adev->mes.ring[0].sched.ready) 1653 goto out; 1654 1655 if (!adev->enable_mes_kiq) { 1656 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1657 r = mes_v11_0_load_microcode(adev, 1658 AMDGPU_MES_SCHED_PIPE, true); 1659 if (r) { 1660 DRM_ERROR("failed to MES fw, r=%d\n", r); 1661 return r; 1662 } 1663 } 1664 1665 mes_v11_0_enable(adev, true); 1666 } 1667 1668 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1669 if (r) 1670 goto failure; 1671 1672 r = mes_v11_0_set_hw_resources(&adev->mes); 1673 if (r) 1674 goto failure; 1675 1676 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) { 1677 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1678 if (r) { 1679 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1680 goto failure; 1681 } 1682 } 1683 1684 r = mes_v11_0_query_sched_status(&adev->mes); 1685 if (r) { 1686 DRM_ERROR("MES is busy\n"); 1687 goto failure; 1688 } 1689 1690 r = amdgpu_mes_update_enforce_isolation(adev); 1691 if (r) 1692 goto failure; 1693 1694 out: 1695 /* 1696 * Disable KIQ ring usage from the driver once MES is enabled. 1697 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1698 * with MES enabled. 1699 */ 1700 adev->gfx.kiq[0].ring.sched.ready = false; 1701 adev->mes.ring[0].sched.ready = true; 1702 1703 return 0; 1704 1705 failure: 1706 mes_v11_0_hw_fini(ip_block); 1707 return r; 1708 } 1709 1710 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1711 { 1712 return 0; 1713 } 1714 1715 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1716 { 1717 return mes_v11_0_hw_fini(ip_block); 1718 } 1719 1720 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1721 { 1722 return mes_v11_0_hw_init(ip_block); 1723 } 1724 1725 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1726 { 1727 struct amdgpu_device *adev = ip_block->adev; 1728 int pipe, r; 1729 1730 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1731 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1732 1733 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1734 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1735 continue; 1736 r = amdgpu_mes_init_microcode(adev, pipe); 1737 if (r) 1738 return r; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1745 .name = "mes_v11_0", 1746 .early_init = mes_v11_0_early_init, 1747 .late_init = NULL, 1748 .sw_init = mes_v11_0_sw_init, 1749 .sw_fini = mes_v11_0_sw_fini, 1750 .hw_init = mes_v11_0_hw_init, 1751 .hw_fini = mes_v11_0_hw_fini, 1752 .suspend = mes_v11_0_suspend, 1753 .resume = mes_v11_0_resume, 1754 }; 1755 1756 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1757 .type = AMD_IP_BLOCK_TYPE_MES, 1758 .major = 11, 1759 .minor = 0, 1760 .rev = 0, 1761 .funcs = &mes_v11_0_ip_funcs, 1762 }; 1763