1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 62 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 63 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 64 65 #define MES_EOP_SIZE 2048 66 #define GFX_MES_DRAM_SIZE 0x80000 67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 68 69 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 70 { 71 struct amdgpu_device *adev = ring->adev; 72 73 if (ring->use_doorbell) { 74 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 75 ring->wptr); 76 WDOORBELL64(ring->doorbell_index, ring->wptr); 77 } else { 78 BUG(); 79 } 80 } 81 82 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 83 { 84 return *ring->rptr_cpu_addr; 85 } 86 87 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 88 { 89 u64 wptr; 90 91 if (ring->use_doorbell) 92 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 93 else 94 BUG(); 95 return wptr; 96 } 97 98 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 99 .type = AMDGPU_RING_TYPE_MES, 100 .align_mask = 1, 101 .nop = 0, 102 .support_64bit_ptrs = true, 103 .get_rptr = mes_v11_0_ring_get_rptr, 104 .get_wptr = mes_v11_0_ring_get_wptr, 105 .set_wptr = mes_v11_0_ring_set_wptr, 106 .insert_nop = amdgpu_ring_insert_nop, 107 }; 108 109 static const char *mes_v11_0_opcodes[] = { 110 "SET_HW_RSRC", 111 "SET_SCHEDULING_CONFIG", 112 "ADD_QUEUE", 113 "REMOVE_QUEUE", 114 "PERFORM_YIELD", 115 "SET_GANG_PRIORITY_LEVEL", 116 "SUSPEND", 117 "RESUME", 118 "RESET", 119 "SET_LOG_BUFFER", 120 "CHANGE_GANG_PRORITY", 121 "QUERY_SCHEDULER_STATUS", 122 "PROGRAM_GDS", 123 "SET_DEBUG_VMID", 124 "MISC", 125 "UPDATE_ROOT_PAGE_TABLE", 126 "AMD_LOG", 127 "unused", 128 "unused", 129 "SET_HW_RSRC_1", 130 }; 131 132 static const char *mes_v11_0_misc_opcodes[] = { 133 "WRITE_REG", 134 "INV_GART", 135 "QUERY_STATUS", 136 "READ_REG", 137 "WAIT_REG_MEM", 138 "SET_SHADER_DEBUGGER", 139 }; 140 141 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 142 { 143 const char *op_str = NULL; 144 145 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 146 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 147 148 return op_str; 149 } 150 151 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 152 { 153 const char *op_str = NULL; 154 155 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 156 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 157 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 158 159 return op_str; 160 } 161 162 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 163 void *pkt, int size, 164 int api_status_off) 165 { 166 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 167 signed long timeout = 2100000; /* 2100 ms */ 168 struct amdgpu_device *adev = mes->adev; 169 struct amdgpu_ring *ring = &mes->ring[0]; 170 struct MES_API_STATUS *api_status; 171 union MESAPI__MISC *x_pkt = pkt; 172 const char *op_str, *misc_op_str; 173 unsigned long flags; 174 u64 status_gpu_addr; 175 u32 seq, status_offset; 176 u64 *status_ptr; 177 signed long r; 178 int ret; 179 180 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 181 return -EINVAL; 182 183 if (amdgpu_emu_mode) { 184 timeout *= 100; 185 } else if (amdgpu_sriov_vf(adev)) { 186 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 187 timeout = 15 * 600 * 1000; 188 } 189 190 ret = amdgpu_device_wb_get(adev, &status_offset); 191 if (ret) 192 return ret; 193 194 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 195 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 196 *status_ptr = 0; 197 198 spin_lock_irqsave(&mes->ring_lock[0], flags); 199 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 200 if (r) 201 goto error_unlock_free; 202 203 seq = ++ring->fence_drv.sync_seq; 204 r = amdgpu_fence_wait_polling(ring, 205 seq - ring->fence_drv.num_fences_mask, 206 timeout); 207 if (r < 1) 208 goto error_undo; 209 210 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 211 api_status->api_completion_fence_addr = status_gpu_addr; 212 api_status->api_completion_fence_value = 1; 213 214 amdgpu_ring_write_multiple(ring, pkt, size / 4); 215 216 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 217 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 218 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 219 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 220 mes_status_pkt.api_status.api_completion_fence_addr = 221 ring->fence_drv.gpu_addr; 222 mes_status_pkt.api_status.api_completion_fence_value = seq; 223 224 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 225 sizeof(mes_status_pkt) / 4); 226 227 amdgpu_ring_commit(ring); 228 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 229 230 op_str = mes_v11_0_get_op_string(x_pkt); 231 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 232 233 if (misc_op_str) 234 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 235 misc_op_str); 236 else if (op_str) 237 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 238 else 239 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 240 x_pkt->header.opcode); 241 242 r = amdgpu_fence_wait_polling(ring, seq, timeout); 243 if (r < 1 || !*status_ptr) { 244 245 if (misc_op_str) 246 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 247 op_str, misc_op_str); 248 else if (op_str) 249 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 250 op_str); 251 else 252 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 253 x_pkt->header.opcode); 254 255 while (halt_if_hws_hang) 256 schedule(); 257 258 r = -ETIMEDOUT; 259 goto error_wb_free; 260 } 261 262 amdgpu_device_wb_free(adev, status_offset); 263 return 0; 264 265 error_undo: 266 dev_err(adev->dev, "MES ring buffer is full.\n"); 267 amdgpu_ring_undo(ring); 268 269 error_unlock_free: 270 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 271 272 error_wb_free: 273 amdgpu_device_wb_free(adev, status_offset); 274 return r; 275 } 276 277 static int convert_to_mes_queue_type(int queue_type) 278 { 279 if (queue_type == AMDGPU_RING_TYPE_GFX) 280 return MES_QUEUE_TYPE_GFX; 281 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 282 return MES_QUEUE_TYPE_COMPUTE; 283 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 284 return MES_QUEUE_TYPE_SDMA; 285 else 286 BUG(); 287 return -1; 288 } 289 290 static int convert_to_mes_priority_level(int priority_level) 291 { 292 switch (priority_level) { 293 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 294 return AMD_PRIORITY_LEVEL_LOW; 295 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 296 default: 297 return AMD_PRIORITY_LEVEL_NORMAL; 298 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 299 return AMD_PRIORITY_LEVEL_MEDIUM; 300 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 301 return AMD_PRIORITY_LEVEL_HIGH; 302 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 303 return AMD_PRIORITY_LEVEL_REALTIME; 304 } 305 } 306 307 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 308 struct mes_add_queue_input *input) 309 { 310 struct amdgpu_device *adev = mes->adev; 311 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 312 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 313 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 314 315 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 316 317 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 318 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 319 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 320 321 mes_add_queue_pkt.process_id = input->process_id; 322 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 323 mes_add_queue_pkt.process_va_start = input->process_va_start; 324 mes_add_queue_pkt.process_va_end = input->process_va_end; 325 mes_add_queue_pkt.process_quantum = input->process_quantum; 326 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 327 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 328 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 329 mes_add_queue_pkt.inprocess_gang_priority = 330 convert_to_mes_priority_level(input->inprocess_gang_priority); 331 mes_add_queue_pkt.gang_global_priority_level = 332 convert_to_mes_priority_level(input->gang_global_priority_level); 333 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 334 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 335 336 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 337 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 338 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 339 else 340 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 341 342 mes_add_queue_pkt.queue_type = 343 convert_to_mes_queue_type(input->queue_type); 344 mes_add_queue_pkt.paging = input->paging; 345 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 346 mes_add_queue_pkt.gws_base = input->gws_base; 347 mes_add_queue_pkt.gws_size = input->gws_size; 348 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 349 mes_add_queue_pkt.tma_addr = input->tma_addr; 350 mes_add_queue_pkt.trap_en = input->trap_en; 351 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 352 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 353 354 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 355 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 356 mes_add_queue_pkt.gds_size = input->queue_size; 357 358 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 359 360 return mes_v11_0_submit_pkt_and_poll_completion(mes, 361 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 362 offsetof(union MESAPI__ADD_QUEUE, api_status)); 363 } 364 365 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 366 struct mes_remove_queue_input *input) 367 { 368 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 369 370 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 371 372 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 373 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 374 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 375 376 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 377 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 378 379 return mes_v11_0_submit_pkt_and_poll_completion(mes, 380 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 381 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 382 } 383 384 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 385 uint32_t me_id, uint32_t pipe_id, 386 uint32_t queue_id, uint32_t vmid) 387 { 388 struct amdgpu_device *adev = mes->adev; 389 uint32_t value, reg; 390 int i, r = 0; 391 392 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 393 394 if (queue_type == AMDGPU_RING_TYPE_GFX) { 395 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 396 me_id, pipe_id, queue_id, vmid); 397 398 mutex_lock(&adev->gfx.reset_sem_mutex); 399 gfx_v11_0_request_gfx_index_mutex(adev, true); 400 /* all se allow writes */ 401 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 402 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 403 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 404 if (pipe_id == 0) 405 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 406 else 407 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 408 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 409 gfx_v11_0_request_gfx_index_mutex(adev, false); 410 mutex_unlock(&adev->gfx.reset_sem_mutex); 411 412 mutex_lock(&adev->srbm_mutex); 413 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 414 /* wait till dequeue take effects */ 415 for (i = 0; i < adev->usec_timeout; i++) { 416 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 417 break; 418 udelay(1); 419 } 420 if (i >= adev->usec_timeout) { 421 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 422 r = -ETIMEDOUT; 423 } 424 425 soc21_grbm_select(adev, 0, 0, 0, 0); 426 mutex_unlock(&adev->srbm_mutex); 427 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 428 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 429 me_id, pipe_id, queue_id); 430 mutex_lock(&adev->srbm_mutex); 431 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 432 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 433 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 434 435 /* wait till dequeue take effects */ 436 for (i = 0; i < adev->usec_timeout; i++) { 437 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 438 break; 439 udelay(1); 440 } 441 if (i >= adev->usec_timeout) { 442 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 443 r = -ETIMEDOUT; 444 } 445 soc21_grbm_select(adev, 0, 0, 0, 0); 446 mutex_unlock(&adev->srbm_mutex); 447 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 448 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 449 me_id, pipe_id, queue_id); 450 switch (me_id) { 451 case 1: 452 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 453 break; 454 case 0: 455 default: 456 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 457 break; 458 } 459 460 value = 1 << queue_id; 461 WREG32(reg, value); 462 /* wait for queue reset done */ 463 for (i = 0; i < adev->usec_timeout; i++) { 464 if (!(RREG32(reg) & value)) 465 break; 466 udelay(1); 467 } 468 if (i >= adev->usec_timeout) { 469 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 470 r = -ETIMEDOUT; 471 } 472 } 473 474 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 475 return r; 476 } 477 478 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 479 struct mes_reset_queue_input *input) 480 { 481 if (input->use_mmio) 482 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 483 input->me_id, input->pipe_id, 484 input->queue_id, input->vmid); 485 486 union MESAPI__RESET mes_reset_queue_pkt; 487 488 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 489 490 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 491 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 492 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 493 494 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 495 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; 496 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 497 498 return mes_v11_0_submit_pkt_and_poll_completion(mes, 499 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 500 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 501 } 502 503 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 504 struct mes_map_legacy_queue_input *input) 505 { 506 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 507 508 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 509 510 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 511 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 512 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 513 514 mes_add_queue_pkt.pipe_id = input->pipe_id; 515 mes_add_queue_pkt.queue_id = input->queue_id; 516 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 517 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 518 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 519 mes_add_queue_pkt.queue_type = 520 convert_to_mes_queue_type(input->queue_type); 521 mes_add_queue_pkt.map_legacy_kq = 1; 522 523 return mes_v11_0_submit_pkt_and_poll_completion(mes, 524 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 525 offsetof(union MESAPI__ADD_QUEUE, api_status)); 526 } 527 528 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 529 struct mes_unmap_legacy_queue_input *input) 530 { 531 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 532 533 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 534 535 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 536 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 537 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 538 539 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 540 mes_remove_queue_pkt.gang_context_addr = 0; 541 542 mes_remove_queue_pkt.pipe_id = input->pipe_id; 543 mes_remove_queue_pkt.queue_id = input->queue_id; 544 545 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 546 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 547 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 548 mes_remove_queue_pkt.tf_data = 549 lower_32_bits(input->trail_fence_data); 550 } else { 551 mes_remove_queue_pkt.unmap_legacy_queue = 1; 552 mes_remove_queue_pkt.queue_type = 553 convert_to_mes_queue_type(input->queue_type); 554 } 555 556 return mes_v11_0_submit_pkt_and_poll_completion(mes, 557 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 558 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 559 } 560 561 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 562 struct mes_suspend_gang_input *input) 563 { 564 union MESAPI__SUSPEND mes_suspend_gang_pkt; 565 566 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 567 568 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 569 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 570 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 571 572 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 573 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 574 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 575 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 576 577 return mes_v11_0_submit_pkt_and_poll_completion(mes, 578 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 579 offsetof(union MESAPI__SUSPEND, api_status)); 580 } 581 582 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 583 struct mes_resume_gang_input *input) 584 { 585 union MESAPI__RESUME mes_resume_gang_pkt; 586 587 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 588 589 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 590 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 591 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 592 593 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 594 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 595 596 return mes_v11_0_submit_pkt_and_poll_completion(mes, 597 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 598 offsetof(union MESAPI__RESUME, api_status)); 599 } 600 601 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 602 { 603 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 604 605 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 606 607 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 608 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 609 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 610 611 return mes_v11_0_submit_pkt_and_poll_completion(mes, 612 &mes_status_pkt, sizeof(mes_status_pkt), 613 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 614 } 615 616 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 617 struct mes_misc_op_input *input) 618 { 619 union MESAPI__MISC misc_pkt; 620 621 memset(&misc_pkt, 0, sizeof(misc_pkt)); 622 623 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 624 misc_pkt.header.opcode = MES_SCH_API_MISC; 625 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 626 627 switch (input->op) { 628 case MES_MISC_OP_READ_REG: 629 misc_pkt.opcode = MESAPI_MISC__READ_REG; 630 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 631 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 632 break; 633 case MES_MISC_OP_WRITE_REG: 634 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 635 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 636 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 637 break; 638 case MES_MISC_OP_WRM_REG_WAIT: 639 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 640 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 641 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 642 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 643 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 644 misc_pkt.wait_reg_mem.reg_offset2 = 0; 645 break; 646 case MES_MISC_OP_WRM_REG_WR_WAIT: 647 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 648 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 649 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 650 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 651 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 652 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 653 break; 654 case MES_MISC_OP_SET_SHADER_DEBUGGER: 655 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 656 misc_pkt.set_shader_debugger.process_context_addr = 657 input->set_shader_debugger.process_context_addr; 658 misc_pkt.set_shader_debugger.flags.u32all = 659 input->set_shader_debugger.flags.u32all; 660 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 661 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 662 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 663 input->set_shader_debugger.tcp_watch_cntl, 664 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 665 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 666 break; 667 case MES_MISC_OP_CHANGE_CONFIG: 668 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 669 dev_err(mes->adev->dev, "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 670 return -EINVAL; 671 } 672 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 673 misc_pkt.change_config.opcode = 674 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 675 misc_pkt.change_config.option.bits.limit_single_process = 676 input->change_config.option.limit_single_process; 677 break; 678 679 default: 680 DRM_ERROR("unsupported misc op (%d) \n", input->op); 681 return -EINVAL; 682 } 683 684 return mes_v11_0_submit_pkt_and_poll_completion(mes, 685 &misc_pkt, sizeof(misc_pkt), 686 offsetof(union MESAPI__MISC, api_status)); 687 } 688 689 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 690 { 691 int i; 692 struct amdgpu_device *adev = mes->adev; 693 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 694 695 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 696 697 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 698 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 699 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 700 701 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 702 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 703 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 704 mes_set_hw_res_pkt.paging_vmid = 0; 705 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 706 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 707 mes->query_status_fence_gpu_addr[0]; 708 709 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 710 mes_set_hw_res_pkt.compute_hqd_mask[i] = 711 mes->compute_hqd_mask[i]; 712 713 for (i = 0; i < MAX_GFX_PIPES; i++) 714 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 715 mes->gfx_hqd_mask[i]; 716 717 for (i = 0; i < MAX_SDMA_PIPES; i++) 718 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 719 720 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 721 mes_set_hw_res_pkt.aggregated_doorbells[i] = 722 mes->aggregated_doorbells[i]; 723 724 for (i = 0; i < 5; i++) { 725 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 726 mes_set_hw_res_pkt.mmhub_base[i] = 727 adev->reg_offset[MMHUB_HWIP][0][i]; 728 mes_set_hw_res_pkt.osssys_base[i] = 729 adev->reg_offset[OSSSYS_HWIP][0][i]; 730 } 731 732 mes_set_hw_res_pkt.disable_reset = 1; 733 mes_set_hw_res_pkt.disable_mes_log = 1; 734 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 735 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 736 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 737 mes_set_hw_res_pkt.oversubscription_timer = 50; 738 if (amdgpu_mes_log_enable) { 739 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 740 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 741 mes->event_log_gpu_addr; 742 } 743 744 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 745 mes_set_hw_res_pkt.limit_single_process = 1; 746 747 return mes_v11_0_submit_pkt_and_poll_completion(mes, 748 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 749 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 750 } 751 752 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 753 { 754 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 755 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 756 757 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 758 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 759 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 760 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 761 762 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 763 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 764 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 765 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 766 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 767 } 768 769 return mes_v11_0_submit_pkt_and_poll_completion(mes, 770 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 771 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 772 } 773 774 static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes, 775 struct mes_reset_legacy_queue_input *input) 776 { 777 union MESAPI__RESET mes_reset_queue_pkt; 778 779 if (input->use_mmio) 780 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 781 input->me_id, input->pipe_id, 782 input->queue_id, input->vmid); 783 784 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 785 786 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 787 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 788 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 789 790 mes_reset_queue_pkt.queue_type = 791 convert_to_mes_queue_type(input->queue_type); 792 793 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 794 mes_reset_queue_pkt.reset_legacy_gfx = 1; 795 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 796 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 797 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 798 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 799 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 800 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 801 } else { 802 mes_reset_queue_pkt.reset_queue_only = 1; 803 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 804 } 805 806 return mes_v11_0_submit_pkt_and_poll_completion(mes, 807 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 808 offsetof(union MESAPI__RESET, api_status)); 809 } 810 811 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 812 .add_hw_queue = mes_v11_0_add_hw_queue, 813 .remove_hw_queue = mes_v11_0_remove_hw_queue, 814 .map_legacy_queue = mes_v11_0_map_legacy_queue, 815 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 816 .suspend_gang = mes_v11_0_suspend_gang, 817 .resume_gang = mes_v11_0_resume_gang, 818 .misc_op = mes_v11_0_misc_op, 819 .reset_legacy_queue = mes_v11_0_reset_legacy_queue, 820 .reset_hw_queue = mes_v11_0_reset_hw_queue, 821 }; 822 823 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 824 enum amdgpu_mes_pipe pipe) 825 { 826 int r; 827 const struct mes_firmware_header_v1_0 *mes_hdr; 828 const __le32 *fw_data; 829 unsigned fw_size; 830 831 mes_hdr = (const struct mes_firmware_header_v1_0 *) 832 adev->mes.fw[pipe]->data; 833 834 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 835 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 836 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 837 838 r = amdgpu_bo_create_reserved(adev, fw_size, 839 PAGE_SIZE, 840 AMDGPU_GEM_DOMAIN_VRAM | 841 AMDGPU_GEM_DOMAIN_GTT, 842 &adev->mes.ucode_fw_obj[pipe], 843 &adev->mes.ucode_fw_gpu_addr[pipe], 844 (void **)&adev->mes.ucode_fw_ptr[pipe]); 845 if (r) { 846 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 847 return r; 848 } 849 850 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 851 852 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 853 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 854 855 return 0; 856 } 857 858 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 859 enum amdgpu_mes_pipe pipe) 860 { 861 int r; 862 const struct mes_firmware_header_v1_0 *mes_hdr; 863 const __le32 *fw_data; 864 unsigned fw_size; 865 866 mes_hdr = (const struct mes_firmware_header_v1_0 *) 867 adev->mes.fw[pipe]->data; 868 869 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 870 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 871 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 872 873 if (fw_size > GFX_MES_DRAM_SIZE) { 874 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 875 pipe, fw_size, GFX_MES_DRAM_SIZE); 876 return -EINVAL; 877 } 878 879 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 880 64 * 1024, 881 AMDGPU_GEM_DOMAIN_VRAM | 882 AMDGPU_GEM_DOMAIN_GTT, 883 &adev->mes.data_fw_obj[pipe], 884 &adev->mes.data_fw_gpu_addr[pipe], 885 (void **)&adev->mes.data_fw_ptr[pipe]); 886 if (r) { 887 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 888 return r; 889 } 890 891 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 892 893 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 894 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 895 896 return 0; 897 } 898 899 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 900 enum amdgpu_mes_pipe pipe) 901 { 902 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 903 &adev->mes.data_fw_gpu_addr[pipe], 904 (void **)&adev->mes.data_fw_ptr[pipe]); 905 906 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 907 &adev->mes.ucode_fw_gpu_addr[pipe], 908 (void **)&adev->mes.ucode_fw_ptr[pipe]); 909 } 910 911 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 912 { 913 int pipe; 914 915 /* return early if we have already fetched these */ 916 if (adev->mes.sched_version && adev->mes.kiq_version) 917 return; 918 919 /* get MES scheduler/KIQ versions */ 920 mutex_lock(&adev->srbm_mutex); 921 922 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 923 soc21_grbm_select(adev, 3, pipe, 0, 0); 924 925 if (pipe == AMDGPU_MES_SCHED_PIPE) 926 adev->mes.sched_version = 927 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 928 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 929 adev->mes.kiq_version = 930 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 931 } 932 933 soc21_grbm_select(adev, 0, 0, 0, 0); 934 mutex_unlock(&adev->srbm_mutex); 935 } 936 937 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 938 { 939 uint64_t ucode_addr; 940 uint32_t pipe, data = 0; 941 942 if (enable) { 943 if (amdgpu_mes_log_enable) { 944 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 945 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 946 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 947 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 948 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 949 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 950 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 951 } 952 953 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 954 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 955 data = REG_SET_FIELD(data, CP_MES_CNTL, 956 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 957 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 958 959 mutex_lock(&adev->srbm_mutex); 960 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 961 if (!adev->enable_mes_kiq && 962 pipe == AMDGPU_MES_KIQ_PIPE) 963 continue; 964 965 soc21_grbm_select(adev, 3, pipe, 0, 0); 966 967 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 968 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 969 lower_32_bits(ucode_addr)); 970 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 971 upper_32_bits(ucode_addr)); 972 } 973 soc21_grbm_select(adev, 0, 0, 0, 0); 974 mutex_unlock(&adev->srbm_mutex); 975 976 /* unhalt MES and activate pipe0 */ 977 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 978 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 979 adev->enable_mes_kiq ? 1 : 0); 980 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 981 982 if (amdgpu_emu_mode) 983 msleep(100); 984 else 985 udelay(500); 986 } else { 987 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 988 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 989 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 990 data = REG_SET_FIELD(data, CP_MES_CNTL, 991 MES_INVALIDATE_ICACHE, 1); 992 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 993 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 994 adev->enable_mes_kiq ? 1 : 0); 995 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 996 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 997 } 998 } 999 1000 /* This function is for backdoor MES firmware */ 1001 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1002 enum amdgpu_mes_pipe pipe, bool prime_icache) 1003 { 1004 int r; 1005 uint32_t data; 1006 uint64_t ucode_addr; 1007 1008 mes_v11_0_enable(adev, false); 1009 1010 if (!adev->mes.fw[pipe]) 1011 return -EINVAL; 1012 1013 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1014 if (r) 1015 return r; 1016 1017 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1018 if (r) { 1019 mes_v11_0_free_ucode_buffers(adev, pipe); 1020 return r; 1021 } 1022 1023 mutex_lock(&adev->srbm_mutex); 1024 /* me=3, pipe=0, queue=0 */ 1025 soc21_grbm_select(adev, 3, pipe, 0, 0); 1026 1027 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1028 1029 /* set ucode start address */ 1030 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1031 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1032 lower_32_bits(ucode_addr)); 1033 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1034 upper_32_bits(ucode_addr)); 1035 1036 /* set ucode fimrware address */ 1037 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1038 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1039 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1040 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1041 1042 /* set ucode instruction cache boundary to 2M-1 */ 1043 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1044 1045 /* set ucode data firmware address */ 1046 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1047 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1048 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1049 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1050 1051 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1052 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1053 1054 if (prime_icache) { 1055 /* invalidate ICACHE */ 1056 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1057 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1058 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1059 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1060 1061 /* prime the ICACHE. */ 1062 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1063 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1064 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1065 } 1066 1067 soc21_grbm_select(adev, 0, 0, 0, 0); 1068 mutex_unlock(&adev->srbm_mutex); 1069 1070 return 0; 1071 } 1072 1073 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1074 enum amdgpu_mes_pipe pipe) 1075 { 1076 int r; 1077 u32 *eop; 1078 1079 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1080 AMDGPU_GEM_DOMAIN_GTT, 1081 &adev->mes.eop_gpu_obj[pipe], 1082 &adev->mes.eop_gpu_addr[pipe], 1083 (void **)&eop); 1084 if (r) { 1085 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1086 return r; 1087 } 1088 1089 memset(eop, 0, 1090 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1091 1092 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1093 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1094 1095 return 0; 1096 } 1097 1098 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1099 { 1100 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1101 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1102 uint32_t tmp; 1103 1104 memset(mqd, 0, sizeof(*mqd)); 1105 1106 mqd->header = 0xC0310800; 1107 mqd->compute_pipelinestat_enable = 0x00000001; 1108 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1109 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1110 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1111 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1112 mqd->compute_misc_reserved = 0x00000007; 1113 1114 eop_base_addr = ring->eop_gpu_addr >> 8; 1115 1116 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1117 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1118 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1119 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1120 1121 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1122 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1123 mqd->cp_hqd_eop_control = tmp; 1124 1125 /* disable the queue if it's active */ 1126 ring->wptr = 0; 1127 mqd->cp_hqd_pq_rptr = 0; 1128 mqd->cp_hqd_pq_wptr_lo = 0; 1129 mqd->cp_hqd_pq_wptr_hi = 0; 1130 1131 /* set the pointer to the MQD */ 1132 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1133 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1134 1135 /* set MQD vmid to 0 */ 1136 tmp = regCP_MQD_CONTROL_DEFAULT; 1137 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1138 mqd->cp_mqd_control = tmp; 1139 1140 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1141 hqd_gpu_addr = ring->gpu_addr >> 8; 1142 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1143 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1144 1145 /* set the wb address whether it's enabled or not */ 1146 wb_gpu_addr = ring->rptr_gpu_addr; 1147 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1148 mqd->cp_hqd_pq_rptr_report_addr_hi = 1149 upper_32_bits(wb_gpu_addr) & 0xffff; 1150 1151 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1152 wb_gpu_addr = ring->wptr_gpu_addr; 1153 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1154 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1155 1156 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1157 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1158 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1159 (order_base_2(ring->ring_size / 4) - 1)); 1160 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1161 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1162 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1163 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1164 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1165 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1166 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1167 mqd->cp_hqd_pq_control = tmp; 1168 1169 /* enable doorbell */ 1170 tmp = 0; 1171 if (ring->use_doorbell) { 1172 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1173 DOORBELL_OFFSET, ring->doorbell_index); 1174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1175 DOORBELL_EN, 1); 1176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1177 DOORBELL_SOURCE, 0); 1178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1179 DOORBELL_HIT, 0); 1180 } else 1181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1182 DOORBELL_EN, 0); 1183 mqd->cp_hqd_pq_doorbell_control = tmp; 1184 1185 mqd->cp_hqd_vmid = 0; 1186 /* activate the queue */ 1187 mqd->cp_hqd_active = 1; 1188 1189 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1190 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1191 PRELOAD_SIZE, 0x55); 1192 mqd->cp_hqd_persistent_state = tmp; 1193 1194 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1195 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1196 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1197 1198 amdgpu_device_flush_hdp(ring->adev, NULL); 1199 return 0; 1200 } 1201 1202 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1203 { 1204 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1205 struct amdgpu_device *adev = ring->adev; 1206 uint32_t data = 0; 1207 1208 mutex_lock(&adev->srbm_mutex); 1209 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1210 1211 /* set CP_HQD_VMID.VMID = 0. */ 1212 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1213 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1214 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1215 1216 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1217 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1218 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1219 DOORBELL_EN, 0); 1220 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1221 1222 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1223 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1224 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1225 1226 /* set CP_MQD_CONTROL.VMID=0 */ 1227 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1228 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1229 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1230 1231 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1234 1235 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1236 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1237 mqd->cp_hqd_pq_rptr_report_addr_lo); 1238 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1239 mqd->cp_hqd_pq_rptr_report_addr_hi); 1240 1241 /* set CP_HQD_PQ_CONTROL */ 1242 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1243 1244 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1245 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1246 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1247 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1248 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1249 1250 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1251 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1252 mqd->cp_hqd_pq_doorbell_control); 1253 1254 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1255 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1256 1257 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1258 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1259 1260 soc21_grbm_select(adev, 0, 0, 0, 0); 1261 mutex_unlock(&adev->srbm_mutex); 1262 } 1263 1264 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1265 { 1266 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1267 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1268 int r; 1269 1270 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1271 return -EINVAL; 1272 1273 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1274 if (r) { 1275 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1276 return r; 1277 } 1278 1279 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1280 1281 return amdgpu_ring_test_helper(kiq_ring); 1282 } 1283 1284 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1285 enum amdgpu_mes_pipe pipe) 1286 { 1287 struct amdgpu_ring *ring; 1288 int r; 1289 1290 if (pipe == AMDGPU_MES_KIQ_PIPE) 1291 ring = &adev->gfx.kiq[0].ring; 1292 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1293 ring = &adev->mes.ring[0]; 1294 else 1295 BUG(); 1296 1297 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1298 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1299 *(ring->wptr_cpu_addr) = 0; 1300 *(ring->rptr_cpu_addr) = 0; 1301 amdgpu_ring_clear_ring(ring); 1302 } 1303 1304 r = mes_v11_0_mqd_init(ring); 1305 if (r) 1306 return r; 1307 1308 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1309 r = mes_v11_0_kiq_enable_queue(adev); 1310 if (r) 1311 return r; 1312 } else { 1313 mes_v11_0_queue_init_register(ring); 1314 } 1315 1316 return 0; 1317 } 1318 1319 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1320 { 1321 struct amdgpu_ring *ring; 1322 1323 ring = &adev->mes.ring[0]; 1324 1325 ring->funcs = &mes_v11_0_ring_funcs; 1326 1327 ring->me = 3; 1328 ring->pipe = 0; 1329 ring->queue = 0; 1330 1331 ring->ring_obj = NULL; 1332 ring->use_doorbell = true; 1333 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1334 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1335 ring->no_scheduler = true; 1336 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1337 1338 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1339 AMDGPU_RING_PRIO_DEFAULT, NULL); 1340 } 1341 1342 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1343 { 1344 struct amdgpu_ring *ring; 1345 1346 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1347 1348 ring = &adev->gfx.kiq[0].ring; 1349 1350 ring->me = 3; 1351 ring->pipe = 1; 1352 ring->queue = 0; 1353 1354 ring->adev = NULL; 1355 ring->ring_obj = NULL; 1356 ring->use_doorbell = true; 1357 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1358 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1359 ring->no_scheduler = true; 1360 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1361 ring->me, ring->pipe, ring->queue); 1362 1363 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1364 AMDGPU_RING_PRIO_DEFAULT, NULL); 1365 } 1366 1367 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1368 enum amdgpu_mes_pipe pipe) 1369 { 1370 int r, mqd_size = sizeof(struct v11_compute_mqd); 1371 struct amdgpu_ring *ring; 1372 1373 if (pipe == AMDGPU_MES_KIQ_PIPE) 1374 ring = &adev->gfx.kiq[0].ring; 1375 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1376 ring = &adev->mes.ring[0]; 1377 else 1378 BUG(); 1379 1380 if (ring->mqd_obj) 1381 return 0; 1382 1383 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1384 AMDGPU_GEM_DOMAIN_VRAM | 1385 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1386 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1387 if (r) { 1388 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1389 return r; 1390 } 1391 1392 memset(ring->mqd_ptr, 0, mqd_size); 1393 1394 /* prepare MQD backup */ 1395 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1396 if (!adev->mes.mqd_backup[pipe]) { 1397 dev_warn(adev->dev, 1398 "no memory to create MQD backup for ring %s\n", 1399 ring->name); 1400 return -ENOMEM; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1407 { 1408 struct amdgpu_device *adev = ip_block->adev; 1409 int pipe, r, bo_size; 1410 1411 adev->mes.funcs = &mes_v11_0_funcs; 1412 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1413 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1414 1415 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1416 1417 r = amdgpu_mes_init(adev); 1418 if (r) 1419 return r; 1420 1421 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1422 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1423 continue; 1424 1425 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1426 if (r) 1427 return r; 1428 1429 r = mes_v11_0_mqd_sw_init(adev, pipe); 1430 if (r) 1431 return r; 1432 } 1433 1434 if (adev->enable_mes_kiq) { 1435 r = mes_v11_0_kiq_ring_init(adev); 1436 if (r) 1437 return r; 1438 } 1439 1440 r = mes_v11_0_ring_init(adev); 1441 if (r) 1442 return r; 1443 1444 bo_size = AMDGPU_GPU_PAGE_SIZE; 1445 if (amdgpu_sriov_is_mes_info_enable(adev)) 1446 bo_size += MES11_HW_RESOURCE_1_SIZE; 1447 1448 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1449 r = amdgpu_bo_create_kernel(adev, 1450 bo_size, 1451 PAGE_SIZE, 1452 AMDGPU_GEM_DOMAIN_VRAM, 1453 &adev->mes.resource_1[0], 1454 &adev->mes.resource_1_gpu_addr[0], 1455 &adev->mes.resource_1_addr[0]); 1456 if (r) { 1457 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1458 return r; 1459 } 1460 1461 return 0; 1462 } 1463 1464 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1465 { 1466 struct amdgpu_device *adev = ip_block->adev; 1467 int pipe; 1468 1469 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1470 &adev->mes.resource_1_addr[0]); 1471 1472 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1473 kfree(adev->mes.mqd_backup[pipe]); 1474 1475 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1476 &adev->mes.eop_gpu_addr[pipe], 1477 NULL); 1478 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1479 } 1480 1481 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1482 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1483 &adev->gfx.kiq[0].ring.mqd_ptr); 1484 1485 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1486 &adev->mes.ring[0].mqd_gpu_addr, 1487 &adev->mes.ring[0].mqd_ptr); 1488 1489 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1490 amdgpu_ring_fini(&adev->mes.ring[0]); 1491 1492 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1493 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1494 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1495 } 1496 1497 amdgpu_mes_fini(adev); 1498 return 0; 1499 } 1500 1501 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1502 { 1503 uint32_t data; 1504 int i; 1505 struct amdgpu_device *adev = ring->adev; 1506 1507 mutex_lock(&adev->srbm_mutex); 1508 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1509 1510 /* disable the queue if it's active */ 1511 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1512 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1513 for (i = 0; i < adev->usec_timeout; i++) { 1514 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1515 break; 1516 udelay(1); 1517 } 1518 } 1519 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1520 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1521 DOORBELL_EN, 0); 1522 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1523 DOORBELL_HIT, 1); 1524 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1525 1526 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1527 1528 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1529 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1530 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1531 1532 soc21_grbm_select(adev, 0, 0, 0, 0); 1533 mutex_unlock(&adev->srbm_mutex); 1534 } 1535 1536 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1537 { 1538 uint32_t tmp; 1539 struct amdgpu_device *adev = ring->adev; 1540 1541 /* tell RLC which is KIQ queue */ 1542 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1543 tmp &= 0xffffff00; 1544 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1545 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1546 } 1547 1548 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1549 { 1550 uint32_t tmp; 1551 1552 /* tell RLC which is KIQ dequeue */ 1553 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1554 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1555 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1556 } 1557 1558 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1559 { 1560 int r = 0; 1561 struct amdgpu_ip_block *ip_block; 1562 1563 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1564 1565 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1566 if (r) { 1567 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1568 return r; 1569 } 1570 1571 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1572 if (r) { 1573 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1574 return r; 1575 } 1576 1577 } 1578 1579 mes_v11_0_enable(adev, true); 1580 1581 mes_v11_0_get_fw_version(adev); 1582 1583 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1584 1585 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1586 if (unlikely(!ip_block)) { 1587 dev_err(adev->dev, "Failed to get MES handle\n"); 1588 return -EINVAL; 1589 } 1590 1591 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1592 if (r) 1593 goto failure; 1594 1595 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1596 adev->mes.enable_legacy_queue_map = true; 1597 else 1598 adev->mes.enable_legacy_queue_map = false; 1599 1600 if (adev->mes.enable_legacy_queue_map) { 1601 r = mes_v11_0_hw_init(ip_block); 1602 if (r) 1603 goto failure; 1604 } 1605 1606 return r; 1607 1608 failure: 1609 mes_v11_0_hw_fini(ip_block); 1610 return r; 1611 } 1612 1613 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1614 { 1615 if (adev->mes.ring[0].sched.ready) { 1616 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1617 adev->mes.ring[0].sched.ready = false; 1618 } 1619 1620 if (amdgpu_sriov_vf(adev)) { 1621 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1622 mes_v11_0_kiq_clear(adev); 1623 } 1624 1625 mes_v11_0_enable(adev, false); 1626 1627 return 0; 1628 } 1629 1630 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1631 { 1632 int r; 1633 struct amdgpu_device *adev = ip_block->adev; 1634 1635 if (adev->mes.ring[0].sched.ready) 1636 goto out; 1637 1638 if (!adev->enable_mes_kiq) { 1639 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1640 r = mes_v11_0_load_microcode(adev, 1641 AMDGPU_MES_SCHED_PIPE, true); 1642 if (r) { 1643 DRM_ERROR("failed to MES fw, r=%d\n", r); 1644 return r; 1645 } 1646 } 1647 1648 mes_v11_0_enable(adev, true); 1649 } 1650 1651 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1652 if (r) 1653 goto failure; 1654 1655 r = mes_v11_0_set_hw_resources(&adev->mes); 1656 if (r) 1657 goto failure; 1658 1659 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1660 if (r) { 1661 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1662 goto failure; 1663 } 1664 1665 r = mes_v11_0_query_sched_status(&adev->mes); 1666 if (r) { 1667 DRM_ERROR("MES is busy\n"); 1668 goto failure; 1669 } 1670 1671 r = amdgpu_mes_update_enforce_isolation(adev); 1672 if (r) 1673 goto failure; 1674 1675 out: 1676 /* 1677 * Disable KIQ ring usage from the driver once MES is enabled. 1678 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1679 * with MES enabled. 1680 */ 1681 adev->gfx.kiq[0].ring.sched.ready = false; 1682 adev->mes.ring[0].sched.ready = true; 1683 1684 return 0; 1685 1686 failure: 1687 mes_v11_0_hw_fini(ip_block); 1688 return r; 1689 } 1690 1691 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1692 { 1693 return 0; 1694 } 1695 1696 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1697 { 1698 return mes_v11_0_hw_fini(ip_block); 1699 } 1700 1701 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1702 { 1703 return mes_v11_0_hw_init(ip_block); 1704 } 1705 1706 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1707 { 1708 struct amdgpu_device *adev = ip_block->adev; 1709 int pipe, r; 1710 1711 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1712 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1713 continue; 1714 r = amdgpu_mes_init_microcode(adev, pipe); 1715 if (r) 1716 return r; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1723 .name = "mes_v11_0", 1724 .early_init = mes_v11_0_early_init, 1725 .late_init = NULL, 1726 .sw_init = mes_v11_0_sw_init, 1727 .sw_fini = mes_v11_0_sw_fini, 1728 .hw_init = mes_v11_0_hw_init, 1729 .hw_fini = mes_v11_0_hw_fini, 1730 .suspend = mes_v11_0_suspend, 1731 .resume = mes_v11_0_resume, 1732 }; 1733 1734 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1735 .type = AMD_IP_BLOCK_TYPE_MES, 1736 .major = 11, 1737 .minor = 0, 1738 .rev = 0, 1739 .funcs = &mes_v11_0_ip_funcs, 1740 }; 1741