1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 55 56 static int mes_v11_0_hw_fini(void *handle); 57 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 58 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 59 60 #define MES_EOP_SIZE 2048 61 #define GFX_MES_DRAM_SIZE 0x80000 62 63 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 if (ring->use_doorbell) { 68 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 69 ring->wptr); 70 WDOORBELL64(ring->doorbell_index, ring->wptr); 71 } else { 72 BUG(); 73 } 74 } 75 76 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 77 { 78 return *ring->rptr_cpu_addr; 79 } 80 81 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 82 { 83 u64 wptr; 84 85 if (ring->use_doorbell) 86 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 87 else 88 BUG(); 89 return wptr; 90 } 91 92 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 93 .type = AMDGPU_RING_TYPE_MES, 94 .align_mask = 1, 95 .nop = 0, 96 .support_64bit_ptrs = true, 97 .get_rptr = mes_v11_0_ring_get_rptr, 98 .get_wptr = mes_v11_0_ring_get_wptr, 99 .set_wptr = mes_v11_0_ring_set_wptr, 100 .insert_nop = amdgpu_ring_insert_nop, 101 }; 102 103 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 104 void *pkt, int size, 105 int api_status_off) 106 { 107 int ndw = size / 4; 108 signed long r; 109 union MESAPI__ADD_QUEUE *x_pkt = pkt; 110 struct MES_API_STATUS *api_status; 111 struct amdgpu_device *adev = mes->adev; 112 struct amdgpu_ring *ring = &mes->ring; 113 unsigned long flags; 114 signed long timeout = adev->usec_timeout; 115 116 if (amdgpu_emu_mode) { 117 timeout *= 100; 118 } else if (amdgpu_sriov_vf(adev)) { 119 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 120 timeout = 15 * 600 * 1000; 121 } 122 BUG_ON(size % 4 != 0); 123 124 spin_lock_irqsave(&mes->ring_lock, flags); 125 if (amdgpu_ring_alloc(ring, ndw)) { 126 spin_unlock_irqrestore(&mes->ring_lock, flags); 127 return -ENOMEM; 128 } 129 130 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 131 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 132 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 133 134 amdgpu_ring_write_multiple(ring, pkt, ndw); 135 amdgpu_ring_commit(ring); 136 spin_unlock_irqrestore(&mes->ring_lock, flags); 137 138 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 139 140 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 141 timeout); 142 if (r < 1) { 143 DRM_ERROR("MES failed to response msg=%d\n", 144 x_pkt->header.opcode); 145 146 while (halt_if_hws_hang) 147 schedule(); 148 149 return -ETIMEDOUT; 150 } 151 152 return 0; 153 } 154 155 static int convert_to_mes_queue_type(int queue_type) 156 { 157 if (queue_type == AMDGPU_RING_TYPE_GFX) 158 return MES_QUEUE_TYPE_GFX; 159 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 160 return MES_QUEUE_TYPE_COMPUTE; 161 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 162 return MES_QUEUE_TYPE_SDMA; 163 else 164 BUG(); 165 return -1; 166 } 167 168 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 169 struct mes_add_queue_input *input) 170 { 171 struct amdgpu_device *adev = mes->adev; 172 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 173 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 174 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 175 176 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 177 178 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 179 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 180 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 181 182 mes_add_queue_pkt.process_id = input->process_id; 183 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 184 mes_add_queue_pkt.process_va_start = input->process_va_start; 185 mes_add_queue_pkt.process_va_end = input->process_va_end; 186 mes_add_queue_pkt.process_quantum = input->process_quantum; 187 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 188 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 189 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 190 mes_add_queue_pkt.inprocess_gang_priority = 191 input->inprocess_gang_priority; 192 mes_add_queue_pkt.gang_global_priority_level = 193 input->gang_global_priority_level; 194 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 195 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 196 197 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 198 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 199 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 200 else 201 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 202 203 mes_add_queue_pkt.queue_type = 204 convert_to_mes_queue_type(input->queue_type); 205 mes_add_queue_pkt.paging = input->paging; 206 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 207 mes_add_queue_pkt.gws_base = input->gws_base; 208 mes_add_queue_pkt.gws_size = input->gws_size; 209 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 210 mes_add_queue_pkt.tma_addr = input->tma_addr; 211 mes_add_queue_pkt.trap_en = input->trap_en; 212 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 213 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 214 215 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 216 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 217 mes_add_queue_pkt.gds_size = input->queue_size; 218 219 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 220 221 return mes_v11_0_submit_pkt_and_poll_completion(mes, 222 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 223 offsetof(union MESAPI__ADD_QUEUE, api_status)); 224 } 225 226 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 227 struct mes_remove_queue_input *input) 228 { 229 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 230 231 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 232 233 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 234 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 235 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 236 237 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 238 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 239 240 return mes_v11_0_submit_pkt_and_poll_completion(mes, 241 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 242 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 243 } 244 245 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 246 struct mes_unmap_legacy_queue_input *input) 247 { 248 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 249 250 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 251 252 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 253 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 254 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 255 256 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 257 mes_remove_queue_pkt.gang_context_addr = 0; 258 259 mes_remove_queue_pkt.pipe_id = input->pipe_id; 260 mes_remove_queue_pkt.queue_id = input->queue_id; 261 262 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 263 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 264 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 265 mes_remove_queue_pkt.tf_data = 266 lower_32_bits(input->trail_fence_data); 267 } else { 268 mes_remove_queue_pkt.unmap_legacy_queue = 1; 269 mes_remove_queue_pkt.queue_type = 270 convert_to_mes_queue_type(input->queue_type); 271 } 272 273 return mes_v11_0_submit_pkt_and_poll_completion(mes, 274 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 275 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 276 } 277 278 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 279 struct mes_suspend_gang_input *input) 280 { 281 return 0; 282 } 283 284 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 285 struct mes_resume_gang_input *input) 286 { 287 return 0; 288 } 289 290 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 291 { 292 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 293 294 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 295 296 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 297 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 298 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 299 300 return mes_v11_0_submit_pkt_and_poll_completion(mes, 301 &mes_status_pkt, sizeof(mes_status_pkt), 302 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 303 } 304 305 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 306 struct mes_misc_op_input *input) 307 { 308 union MESAPI__MISC misc_pkt; 309 310 memset(&misc_pkt, 0, sizeof(misc_pkt)); 311 312 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 313 misc_pkt.header.opcode = MES_SCH_API_MISC; 314 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 315 316 switch (input->op) { 317 case MES_MISC_OP_READ_REG: 318 misc_pkt.opcode = MESAPI_MISC__READ_REG; 319 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 320 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 321 break; 322 case MES_MISC_OP_WRITE_REG: 323 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 324 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 325 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 326 break; 327 case MES_MISC_OP_WRM_REG_WAIT: 328 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 329 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 330 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 331 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 332 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 333 misc_pkt.wait_reg_mem.reg_offset2 = 0; 334 break; 335 case MES_MISC_OP_WRM_REG_WR_WAIT: 336 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 337 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 338 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 339 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 340 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 341 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 342 break; 343 case MES_MISC_OP_SET_SHADER_DEBUGGER: 344 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 345 misc_pkt.set_shader_debugger.process_context_addr = 346 input->set_shader_debugger.process_context_addr; 347 misc_pkt.set_shader_debugger.flags.u32all = 348 input->set_shader_debugger.flags.u32all; 349 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 350 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 351 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 352 input->set_shader_debugger.tcp_watch_cntl, 353 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 354 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 355 break; 356 default: 357 DRM_ERROR("unsupported misc op (%d) \n", input->op); 358 return -EINVAL; 359 } 360 361 return mes_v11_0_submit_pkt_and_poll_completion(mes, 362 &misc_pkt, sizeof(misc_pkt), 363 offsetof(union MESAPI__MISC, api_status)); 364 } 365 366 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 367 { 368 int i; 369 struct amdgpu_device *adev = mes->adev; 370 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 371 372 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 373 374 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 375 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 376 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 377 378 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 379 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 380 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 381 mes_set_hw_res_pkt.paging_vmid = 0; 382 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 383 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 384 mes->query_status_fence_gpu_addr; 385 386 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 387 mes_set_hw_res_pkt.compute_hqd_mask[i] = 388 mes->compute_hqd_mask[i]; 389 390 for (i = 0; i < MAX_GFX_PIPES; i++) 391 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 392 393 for (i = 0; i < MAX_SDMA_PIPES; i++) 394 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 395 396 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 397 mes_set_hw_res_pkt.aggregated_doorbells[i] = 398 mes->aggregated_doorbells[i]; 399 400 for (i = 0; i < 5; i++) { 401 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 402 mes_set_hw_res_pkt.mmhub_base[i] = 403 adev->reg_offset[MMHUB_HWIP][0][i]; 404 mes_set_hw_res_pkt.osssys_base[i] = 405 adev->reg_offset[OSSSYS_HWIP][0][i]; 406 } 407 408 mes_set_hw_res_pkt.disable_reset = 1; 409 mes_set_hw_res_pkt.disable_mes_log = 1; 410 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 411 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 412 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 413 mes_set_hw_res_pkt.oversubscription_timer = 50; 414 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 415 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; 416 417 return mes_v11_0_submit_pkt_and_poll_completion(mes, 418 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 419 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 420 } 421 422 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 423 .add_hw_queue = mes_v11_0_add_hw_queue, 424 .remove_hw_queue = mes_v11_0_remove_hw_queue, 425 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 426 .suspend_gang = mes_v11_0_suspend_gang, 427 .resume_gang = mes_v11_0_resume_gang, 428 .misc_op = mes_v11_0_misc_op, 429 }; 430 431 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 432 enum admgpu_mes_pipe pipe) 433 { 434 int r; 435 const struct mes_firmware_header_v1_0 *mes_hdr; 436 const __le32 *fw_data; 437 unsigned fw_size; 438 439 mes_hdr = (const struct mes_firmware_header_v1_0 *) 440 adev->mes.fw[pipe]->data; 441 442 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 443 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 444 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 445 446 r = amdgpu_bo_create_reserved(adev, fw_size, 447 PAGE_SIZE, 448 AMDGPU_GEM_DOMAIN_VRAM | 449 AMDGPU_GEM_DOMAIN_GTT, 450 &adev->mes.ucode_fw_obj[pipe], 451 &adev->mes.ucode_fw_gpu_addr[pipe], 452 (void **)&adev->mes.ucode_fw_ptr[pipe]); 453 if (r) { 454 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 455 return r; 456 } 457 458 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 459 460 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 461 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 462 463 return 0; 464 } 465 466 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 467 enum admgpu_mes_pipe pipe) 468 { 469 int r; 470 const struct mes_firmware_header_v1_0 *mes_hdr; 471 const __le32 *fw_data; 472 unsigned fw_size; 473 474 mes_hdr = (const struct mes_firmware_header_v1_0 *) 475 adev->mes.fw[pipe]->data; 476 477 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 478 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 479 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 480 481 if (fw_size > GFX_MES_DRAM_SIZE) { 482 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 483 pipe, fw_size, GFX_MES_DRAM_SIZE); 484 return -EINVAL; 485 } 486 487 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 488 64 * 1024, 489 AMDGPU_GEM_DOMAIN_VRAM | 490 AMDGPU_GEM_DOMAIN_GTT, 491 &adev->mes.data_fw_obj[pipe], 492 &adev->mes.data_fw_gpu_addr[pipe], 493 (void **)&adev->mes.data_fw_ptr[pipe]); 494 if (r) { 495 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 496 return r; 497 } 498 499 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 500 501 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 502 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 503 504 return 0; 505 } 506 507 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 508 enum admgpu_mes_pipe pipe) 509 { 510 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 511 &adev->mes.data_fw_gpu_addr[pipe], 512 (void **)&adev->mes.data_fw_ptr[pipe]); 513 514 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 515 &adev->mes.ucode_fw_gpu_addr[pipe], 516 (void **)&adev->mes.ucode_fw_ptr[pipe]); 517 } 518 519 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 520 { 521 uint64_t ucode_addr; 522 uint32_t pipe, data = 0; 523 524 if (enable) { 525 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 526 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 527 data = REG_SET_FIELD(data, CP_MES_CNTL, 528 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 529 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 530 531 mutex_lock(&adev->srbm_mutex); 532 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 533 if (!adev->enable_mes_kiq && 534 pipe == AMDGPU_MES_KIQ_PIPE) 535 continue; 536 537 soc21_grbm_select(adev, 3, pipe, 0, 0); 538 539 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 540 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 541 lower_32_bits(ucode_addr)); 542 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 543 upper_32_bits(ucode_addr)); 544 } 545 soc21_grbm_select(adev, 0, 0, 0, 0); 546 mutex_unlock(&adev->srbm_mutex); 547 548 /* unhalt MES and activate pipe0 */ 549 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 550 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 551 adev->enable_mes_kiq ? 1 : 0); 552 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 553 554 if (amdgpu_emu_mode) 555 msleep(100); 556 else 557 udelay(50); 558 } else { 559 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 560 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 561 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 562 data = REG_SET_FIELD(data, CP_MES_CNTL, 563 MES_INVALIDATE_ICACHE, 1); 564 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 565 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 566 adev->enable_mes_kiq ? 1 : 0); 567 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 568 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 569 } 570 } 571 572 /* This function is for backdoor MES firmware */ 573 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 574 enum admgpu_mes_pipe pipe, bool prime_icache) 575 { 576 int r; 577 uint32_t data; 578 uint64_t ucode_addr; 579 580 mes_v11_0_enable(adev, false); 581 582 if (!adev->mes.fw[pipe]) 583 return -EINVAL; 584 585 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 586 if (r) 587 return r; 588 589 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 590 if (r) { 591 mes_v11_0_free_ucode_buffers(adev, pipe); 592 return r; 593 } 594 595 mutex_lock(&adev->srbm_mutex); 596 /* me=3, pipe=0, queue=0 */ 597 soc21_grbm_select(adev, 3, pipe, 0, 0); 598 599 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 600 601 /* set ucode start address */ 602 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 603 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 604 lower_32_bits(ucode_addr)); 605 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 606 upper_32_bits(ucode_addr)); 607 608 /* set ucode fimrware address */ 609 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 610 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 611 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 612 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 613 614 /* set ucode instruction cache boundary to 2M-1 */ 615 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 616 617 /* set ucode data firmware address */ 618 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 619 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 620 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 621 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 622 623 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 624 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 625 626 if (prime_icache) { 627 /* invalidate ICACHE */ 628 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 629 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 630 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 631 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 632 633 /* prime the ICACHE. */ 634 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 635 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 636 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 637 } 638 639 soc21_grbm_select(adev, 0, 0, 0, 0); 640 mutex_unlock(&adev->srbm_mutex); 641 642 return 0; 643 } 644 645 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 646 enum admgpu_mes_pipe pipe) 647 { 648 int r; 649 u32 *eop; 650 651 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 652 AMDGPU_GEM_DOMAIN_GTT, 653 &adev->mes.eop_gpu_obj[pipe], 654 &adev->mes.eop_gpu_addr[pipe], 655 (void **)&eop); 656 if (r) { 657 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 658 return r; 659 } 660 661 memset(eop, 0, 662 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 663 664 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 665 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 666 667 return 0; 668 } 669 670 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 671 { 672 struct v11_compute_mqd *mqd = ring->mqd_ptr; 673 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 674 uint32_t tmp; 675 676 memset(mqd, 0, sizeof(*mqd)); 677 678 mqd->header = 0xC0310800; 679 mqd->compute_pipelinestat_enable = 0x00000001; 680 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 681 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 682 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 683 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 684 mqd->compute_misc_reserved = 0x00000007; 685 686 eop_base_addr = ring->eop_gpu_addr >> 8; 687 688 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 689 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 690 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 691 (order_base_2(MES_EOP_SIZE / 4) - 1)); 692 693 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 694 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 695 mqd->cp_hqd_eop_control = tmp; 696 697 /* disable the queue if it's active */ 698 ring->wptr = 0; 699 mqd->cp_hqd_pq_rptr = 0; 700 mqd->cp_hqd_pq_wptr_lo = 0; 701 mqd->cp_hqd_pq_wptr_hi = 0; 702 703 /* set the pointer to the MQD */ 704 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 705 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 706 707 /* set MQD vmid to 0 */ 708 tmp = regCP_MQD_CONTROL_DEFAULT; 709 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 710 mqd->cp_mqd_control = tmp; 711 712 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 713 hqd_gpu_addr = ring->gpu_addr >> 8; 714 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 715 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 716 717 /* set the wb address whether it's enabled or not */ 718 wb_gpu_addr = ring->rptr_gpu_addr; 719 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 720 mqd->cp_hqd_pq_rptr_report_addr_hi = 721 upper_32_bits(wb_gpu_addr) & 0xffff; 722 723 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 724 wb_gpu_addr = ring->wptr_gpu_addr; 725 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 726 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 727 728 /* set up the HQD, this is similar to CP_RB0_CNTL */ 729 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 730 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 731 (order_base_2(ring->ring_size / 4) - 1)); 732 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 733 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 734 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 735 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 736 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 737 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 739 mqd->cp_hqd_pq_control = tmp; 740 741 /* enable doorbell */ 742 tmp = 0; 743 if (ring->use_doorbell) { 744 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 745 DOORBELL_OFFSET, ring->doorbell_index); 746 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 747 DOORBELL_EN, 1); 748 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 749 DOORBELL_SOURCE, 0); 750 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 751 DOORBELL_HIT, 0); 752 } else 753 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 754 DOORBELL_EN, 0); 755 mqd->cp_hqd_pq_doorbell_control = tmp; 756 757 mqd->cp_hqd_vmid = 0; 758 /* activate the queue */ 759 mqd->cp_hqd_active = 1; 760 761 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 762 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 763 PRELOAD_SIZE, 0x55); 764 mqd->cp_hqd_persistent_state = tmp; 765 766 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 767 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 768 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 769 770 amdgpu_device_flush_hdp(ring->adev, NULL); 771 return 0; 772 } 773 774 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 775 { 776 struct v11_compute_mqd *mqd = ring->mqd_ptr; 777 struct amdgpu_device *adev = ring->adev; 778 uint32_t data = 0; 779 780 mutex_lock(&adev->srbm_mutex); 781 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 782 783 /* set CP_HQD_VMID.VMID = 0. */ 784 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 785 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 786 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 787 788 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 789 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 790 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 791 DOORBELL_EN, 0); 792 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 793 794 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 795 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 796 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 797 798 /* set CP_MQD_CONTROL.VMID=0 */ 799 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 800 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 801 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 802 803 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 804 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 805 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 806 807 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 808 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 809 mqd->cp_hqd_pq_rptr_report_addr_lo); 810 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 811 mqd->cp_hqd_pq_rptr_report_addr_hi); 812 813 /* set CP_HQD_PQ_CONTROL */ 814 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 815 816 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 817 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 818 mqd->cp_hqd_pq_wptr_poll_addr_lo); 819 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 820 mqd->cp_hqd_pq_wptr_poll_addr_hi); 821 822 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 823 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 824 mqd->cp_hqd_pq_doorbell_control); 825 826 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 827 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 828 829 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 830 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 831 832 soc21_grbm_select(adev, 0, 0, 0, 0); 833 mutex_unlock(&adev->srbm_mutex); 834 } 835 836 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 837 { 838 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 839 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 840 int r; 841 842 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 843 return -EINVAL; 844 845 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 846 if (r) { 847 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 848 return r; 849 } 850 851 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 852 853 return amdgpu_ring_test_helper(kiq_ring); 854 } 855 856 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 857 enum admgpu_mes_pipe pipe) 858 { 859 struct amdgpu_ring *ring; 860 int r; 861 862 if (pipe == AMDGPU_MES_KIQ_PIPE) 863 ring = &adev->gfx.kiq[0].ring; 864 else if (pipe == AMDGPU_MES_SCHED_PIPE) 865 ring = &adev->mes.ring; 866 else 867 BUG(); 868 869 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 870 (amdgpu_in_reset(adev) || adev->in_suspend)) { 871 *(ring->wptr_cpu_addr) = 0; 872 *(ring->rptr_cpu_addr) = 0; 873 amdgpu_ring_clear_ring(ring); 874 } 875 876 r = mes_v11_0_mqd_init(ring); 877 if (r) 878 return r; 879 880 if (pipe == AMDGPU_MES_SCHED_PIPE) { 881 r = mes_v11_0_kiq_enable_queue(adev); 882 if (r) 883 return r; 884 } else { 885 mes_v11_0_queue_init_register(ring); 886 } 887 888 /* get MES scheduler/KIQ versions */ 889 mutex_lock(&adev->srbm_mutex); 890 soc21_grbm_select(adev, 3, pipe, 0, 0); 891 892 if (pipe == AMDGPU_MES_SCHED_PIPE) 893 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 894 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 895 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 896 897 soc21_grbm_select(adev, 0, 0, 0, 0); 898 mutex_unlock(&adev->srbm_mutex); 899 900 return 0; 901 } 902 903 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 904 { 905 struct amdgpu_ring *ring; 906 907 ring = &adev->mes.ring; 908 909 ring->funcs = &mes_v11_0_ring_funcs; 910 911 ring->me = 3; 912 ring->pipe = 0; 913 ring->queue = 0; 914 915 ring->ring_obj = NULL; 916 ring->use_doorbell = true; 917 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 918 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 919 ring->no_scheduler = true; 920 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 921 922 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 923 AMDGPU_RING_PRIO_DEFAULT, NULL); 924 } 925 926 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 927 { 928 struct amdgpu_ring *ring; 929 930 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 931 932 ring = &adev->gfx.kiq[0].ring; 933 934 ring->me = 3; 935 ring->pipe = 1; 936 ring->queue = 0; 937 938 ring->adev = NULL; 939 ring->ring_obj = NULL; 940 ring->use_doorbell = true; 941 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 942 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 943 ring->no_scheduler = true; 944 sprintf(ring->name, "mes_kiq_%d.%d.%d", 945 ring->me, ring->pipe, ring->queue); 946 947 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 948 AMDGPU_RING_PRIO_DEFAULT, NULL); 949 } 950 951 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 952 enum admgpu_mes_pipe pipe) 953 { 954 int r, mqd_size = sizeof(struct v11_compute_mqd); 955 struct amdgpu_ring *ring; 956 957 if (pipe == AMDGPU_MES_KIQ_PIPE) 958 ring = &adev->gfx.kiq[0].ring; 959 else if (pipe == AMDGPU_MES_SCHED_PIPE) 960 ring = &adev->mes.ring; 961 else 962 BUG(); 963 964 if (ring->mqd_obj) 965 return 0; 966 967 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 968 AMDGPU_GEM_DOMAIN_VRAM | 969 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 970 &ring->mqd_gpu_addr, &ring->mqd_ptr); 971 if (r) { 972 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 973 return r; 974 } 975 976 memset(ring->mqd_ptr, 0, mqd_size); 977 978 /* prepare MQD backup */ 979 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 980 if (!adev->mes.mqd_backup[pipe]) { 981 dev_warn(adev->dev, 982 "no memory to create MQD backup for ring %s\n", 983 ring->name); 984 return -ENOMEM; 985 } 986 987 return 0; 988 } 989 990 static int mes_v11_0_sw_init(void *handle) 991 { 992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 993 int pipe, r; 994 995 adev->mes.funcs = &mes_v11_0_funcs; 996 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 997 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 998 999 r = amdgpu_mes_init(adev); 1000 if (r) 1001 return r; 1002 1003 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1004 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1005 continue; 1006 1007 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1008 if (r) 1009 return r; 1010 1011 r = mes_v11_0_mqd_sw_init(adev, pipe); 1012 if (r) 1013 return r; 1014 } 1015 1016 if (adev->enable_mes_kiq) { 1017 r = mes_v11_0_kiq_ring_init(adev); 1018 if (r) 1019 return r; 1020 } 1021 1022 r = mes_v11_0_ring_init(adev); 1023 if (r) 1024 return r; 1025 1026 return 0; 1027 } 1028 1029 static int mes_v11_0_sw_fini(void *handle) 1030 { 1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1032 int pipe; 1033 1034 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1035 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1036 1037 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1038 kfree(adev->mes.mqd_backup[pipe]); 1039 1040 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1041 &adev->mes.eop_gpu_addr[pipe], 1042 NULL); 1043 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1044 } 1045 1046 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1047 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1048 &adev->gfx.kiq[0].ring.mqd_ptr); 1049 1050 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1051 &adev->mes.ring.mqd_gpu_addr, 1052 &adev->mes.ring.mqd_ptr); 1053 1054 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1055 amdgpu_ring_fini(&adev->mes.ring); 1056 1057 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1058 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1059 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1060 } 1061 1062 amdgpu_mes_fini(adev); 1063 return 0; 1064 } 1065 1066 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1067 { 1068 uint32_t data; 1069 int i; 1070 struct amdgpu_device *adev = ring->adev; 1071 1072 mutex_lock(&adev->srbm_mutex); 1073 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1074 1075 /* disable the queue if it's active */ 1076 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1077 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1078 for (i = 0; i < adev->usec_timeout; i++) { 1079 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1080 break; 1081 udelay(1); 1082 } 1083 } 1084 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1085 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1086 DOORBELL_EN, 0); 1087 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1088 DOORBELL_HIT, 1); 1089 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1090 1091 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1092 1093 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1094 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1095 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1096 1097 soc21_grbm_select(adev, 0, 0, 0, 0); 1098 mutex_unlock(&adev->srbm_mutex); 1099 } 1100 1101 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1102 { 1103 uint32_t tmp; 1104 struct amdgpu_device *adev = ring->adev; 1105 1106 /* tell RLC which is KIQ queue */ 1107 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1108 tmp &= 0xffffff00; 1109 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1110 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1111 tmp |= 0x80; 1112 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1113 } 1114 1115 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1116 { 1117 uint32_t tmp; 1118 1119 /* tell RLC which is KIQ dequeue */ 1120 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1121 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1122 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1123 } 1124 1125 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1126 { 1127 int r = 0; 1128 1129 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1130 1131 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1132 if (r) { 1133 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1134 return r; 1135 } 1136 1137 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1138 if (r) { 1139 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1140 return r; 1141 } 1142 1143 } 1144 1145 mes_v11_0_enable(adev, true); 1146 1147 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1148 1149 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1150 if (r) 1151 goto failure; 1152 1153 return r; 1154 1155 failure: 1156 mes_v11_0_hw_fini(adev); 1157 return r; 1158 } 1159 1160 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1161 { 1162 if (adev->mes.ring.sched.ready) { 1163 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1164 adev->mes.ring.sched.ready = false; 1165 } 1166 1167 if (amdgpu_sriov_vf(adev)) { 1168 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1169 mes_v11_0_kiq_clear(adev); 1170 } 1171 1172 mes_v11_0_enable(adev, false); 1173 1174 return 0; 1175 } 1176 1177 static int mes_v11_0_hw_init(void *handle) 1178 { 1179 int r; 1180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1181 1182 if (!adev->enable_mes_kiq) { 1183 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1184 r = mes_v11_0_load_microcode(adev, 1185 AMDGPU_MES_SCHED_PIPE, true); 1186 if (r) { 1187 DRM_ERROR("failed to MES fw, r=%d\n", r); 1188 return r; 1189 } 1190 } 1191 1192 mes_v11_0_enable(adev, true); 1193 } 1194 1195 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1196 if (r) 1197 goto failure; 1198 1199 r = mes_v11_0_set_hw_resources(&adev->mes); 1200 if (r) 1201 goto failure; 1202 1203 r = mes_v11_0_query_sched_status(&adev->mes); 1204 if (r) { 1205 DRM_ERROR("MES is busy\n"); 1206 goto failure; 1207 } 1208 1209 /* 1210 * Disable KIQ ring usage from the driver once MES is enabled. 1211 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1212 * with MES enabled. 1213 */ 1214 adev->gfx.kiq[0].ring.sched.ready = false; 1215 adev->mes.ring.sched.ready = true; 1216 1217 return 0; 1218 1219 failure: 1220 mes_v11_0_hw_fini(adev); 1221 return r; 1222 } 1223 1224 static int mes_v11_0_hw_fini(void *handle) 1225 { 1226 return 0; 1227 } 1228 1229 static int mes_v11_0_suspend(void *handle) 1230 { 1231 int r; 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 r = amdgpu_mes_suspend(adev); 1235 if (r) 1236 return r; 1237 1238 return mes_v11_0_hw_fini(adev); 1239 } 1240 1241 static int mes_v11_0_resume(void *handle) 1242 { 1243 int r; 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 1246 r = mes_v11_0_hw_init(adev); 1247 if (r) 1248 return r; 1249 1250 return amdgpu_mes_resume(adev); 1251 } 1252 1253 static int mes_v11_0_early_init(void *handle) 1254 { 1255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1256 int pipe, r; 1257 1258 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1259 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1260 continue; 1261 r = amdgpu_mes_init_microcode(adev, pipe); 1262 if (r) 1263 return r; 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int mes_v11_0_late_init(void *handle) 1270 { 1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1272 1273 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1274 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1275 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1276 amdgpu_mes_self_test(adev); 1277 1278 return 0; 1279 } 1280 1281 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1282 .name = "mes_v11_0", 1283 .early_init = mes_v11_0_early_init, 1284 .late_init = mes_v11_0_late_init, 1285 .sw_init = mes_v11_0_sw_init, 1286 .sw_fini = mes_v11_0_sw_fini, 1287 .hw_init = mes_v11_0_hw_init, 1288 .hw_fini = mes_v11_0_hw_fini, 1289 .suspend = mes_v11_0_suspend, 1290 .resume = mes_v11_0_resume, 1291 }; 1292 1293 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1294 .type = AMD_IP_BLOCK_TYPE_MES, 1295 .major = 11, 1296 .minor = 0, 1297 .rev = 0, 1298 .funcs = &mes_v11_0_ip_funcs, 1299 }; 1300