1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin"); 67 68 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 69 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 72 73 #define MES_EOP_SIZE 2048 74 #define GFX_MES_DRAM_SIZE 0x80000 75 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 76 77 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 78 #define MES11_HUNG_HQD_INFO_OFFSET 4 79 80 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 81 { 82 struct amdgpu_device *adev = ring->adev; 83 84 if (ring->use_doorbell) { 85 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 86 ring->wptr); 87 WDOORBELL64(ring->doorbell_index, ring->wptr); 88 } else { 89 BUG(); 90 } 91 } 92 93 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 94 { 95 return *ring->rptr_cpu_addr; 96 } 97 98 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 99 { 100 u64 wptr; 101 102 if (ring->use_doorbell) 103 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 104 else 105 BUG(); 106 return wptr; 107 } 108 109 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 110 .type = AMDGPU_RING_TYPE_MES, 111 .align_mask = 1, 112 .nop = 0, 113 .support_64bit_ptrs = true, 114 .get_rptr = mes_v11_0_ring_get_rptr, 115 .get_wptr = mes_v11_0_ring_get_wptr, 116 .set_wptr = mes_v11_0_ring_set_wptr, 117 .insert_nop = amdgpu_ring_insert_nop, 118 }; 119 120 static const char *mes_v11_0_opcodes[] = { 121 "SET_HW_RSRC", 122 "SET_SCHEDULING_CONFIG", 123 "ADD_QUEUE", 124 "REMOVE_QUEUE", 125 "PERFORM_YIELD", 126 "SET_GANG_PRIORITY_LEVEL", 127 "SUSPEND", 128 "RESUME", 129 "RESET", 130 "SET_LOG_BUFFER", 131 "CHANGE_GANG_PRORITY", 132 "QUERY_SCHEDULER_STATUS", 133 "PROGRAM_GDS", 134 "SET_DEBUG_VMID", 135 "MISC", 136 "UPDATE_ROOT_PAGE_TABLE", 137 "AMD_LOG", 138 "unused", 139 "unused", 140 "SET_HW_RSRC_1", 141 }; 142 143 static const char *mes_v11_0_misc_opcodes[] = { 144 "WRITE_REG", 145 "INV_GART", 146 "QUERY_STATUS", 147 "READ_REG", 148 "WAIT_REG_MEM", 149 "SET_SHADER_DEBUGGER", 150 }; 151 152 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 153 { 154 const char *op_str = NULL; 155 156 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 157 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 158 159 return op_str; 160 } 161 162 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 163 { 164 const char *op_str = NULL; 165 166 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 167 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 168 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 169 170 return op_str; 171 } 172 173 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 174 void *pkt, int size, 175 int api_status_off) 176 { 177 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 178 signed long timeout = 2100000; /* 2100 ms */ 179 struct amdgpu_device *adev = mes->adev; 180 struct amdgpu_ring *ring = &mes->ring[0]; 181 struct MES_API_STATUS *api_status; 182 union MESAPI__MISC *x_pkt = pkt; 183 const char *op_str, *misc_op_str; 184 unsigned long flags; 185 u64 status_gpu_addr; 186 u32 seq, status_offset; 187 u64 *status_ptr; 188 signed long r; 189 int ret; 190 191 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 192 return -EINVAL; 193 194 if (amdgpu_emu_mode) { 195 timeout *= 100; 196 } else if (amdgpu_sriov_vf(adev)) { 197 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 198 timeout = 15 * 600 * 1000; 199 } 200 201 ret = amdgpu_wb_get(adev, &status_offset); 202 if (ret) 203 return ret; 204 205 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 206 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 207 *status_ptr = 0; 208 209 spin_lock_irqsave(&mes->ring_lock[0], flags); 210 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 211 if (r) 212 goto error_unlock_free; 213 214 seq = ++ring->fence_drv.sync_seq; 215 r = amdgpu_fence_wait_polling(ring, 216 seq - ring->fence_drv.num_fences_mask, 217 timeout); 218 if (r < 1) 219 goto error_undo; 220 221 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 222 api_status->api_completion_fence_addr = status_gpu_addr; 223 api_status->api_completion_fence_value = 1; 224 225 amdgpu_ring_write_multiple(ring, pkt, size / 4); 226 227 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 228 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 229 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 230 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 231 mes_status_pkt.api_status.api_completion_fence_addr = 232 ring->fence_drv.gpu_addr; 233 mes_status_pkt.api_status.api_completion_fence_value = seq; 234 235 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 236 sizeof(mes_status_pkt) / 4); 237 238 amdgpu_ring_commit(ring); 239 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 240 241 op_str = mes_v11_0_get_op_string(x_pkt); 242 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 243 244 if (misc_op_str) 245 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 246 misc_op_str); 247 else if (op_str) 248 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 249 else 250 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 251 x_pkt->header.opcode); 252 253 r = amdgpu_fence_wait_polling(ring, seq, timeout); 254 if (r < 1 || !*status_ptr) { 255 256 if (misc_op_str) 257 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 258 op_str, misc_op_str); 259 else if (op_str) 260 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 261 op_str); 262 else 263 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 264 x_pkt->header.opcode); 265 266 while (halt_if_hws_hang) 267 schedule(); 268 269 r = -ETIMEDOUT; 270 goto error_wb_free; 271 } 272 273 amdgpu_wb_free(adev, status_offset); 274 return 0; 275 276 error_undo: 277 dev_err(adev->dev, "MES ring buffer is full.\n"); 278 amdgpu_ring_undo(ring); 279 280 error_unlock_free: 281 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 282 283 error_wb_free: 284 amdgpu_wb_free(adev, status_offset); 285 return r; 286 } 287 288 static int convert_to_mes_queue_type(int queue_type) 289 { 290 if (queue_type == AMDGPU_RING_TYPE_GFX) 291 return MES_QUEUE_TYPE_GFX; 292 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 293 return MES_QUEUE_TYPE_COMPUTE; 294 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 295 return MES_QUEUE_TYPE_SDMA; 296 else 297 BUG(); 298 return -1; 299 } 300 301 static int convert_to_mes_priority_level(int priority_level) 302 { 303 switch (priority_level) { 304 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 305 return AMD_PRIORITY_LEVEL_LOW; 306 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 307 default: 308 return AMD_PRIORITY_LEVEL_NORMAL; 309 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 310 return AMD_PRIORITY_LEVEL_MEDIUM; 311 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 312 return AMD_PRIORITY_LEVEL_HIGH; 313 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 314 return AMD_PRIORITY_LEVEL_REALTIME; 315 } 316 } 317 318 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 319 struct mes_add_queue_input *input) 320 { 321 struct amdgpu_device *adev = mes->adev; 322 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 323 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 324 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 325 326 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 327 328 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 329 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 330 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 331 332 mes_add_queue_pkt.process_id = input->process_id; 333 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 334 mes_add_queue_pkt.process_va_start = input->process_va_start; 335 mes_add_queue_pkt.process_va_end = input->process_va_end; 336 mes_add_queue_pkt.process_quantum = input->process_quantum; 337 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 338 mes_add_queue_pkt.process_context_array_index = input->process_context_array_index; 339 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 340 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 341 mes_add_queue_pkt.gang_context_array_index = input->gang_context_array_index; 342 mes_add_queue_pkt.inprocess_gang_priority = 343 convert_to_mes_priority_level(input->inprocess_gang_priority); 344 mes_add_queue_pkt.gang_global_priority_level = 345 convert_to_mes_priority_level(input->gang_global_priority_level); 346 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 347 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 348 349 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 350 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 351 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 352 else 353 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 354 355 mes_add_queue_pkt.queue_type = 356 convert_to_mes_queue_type(input->queue_type); 357 mes_add_queue_pkt.paging = input->paging; 358 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 359 mes_add_queue_pkt.gws_base = input->gws_base; 360 mes_add_queue_pkt.gws_size = input->gws_size; 361 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 362 mes_add_queue_pkt.tma_addr = input->tma_addr; 363 mes_add_queue_pkt.trap_en = input->trap_en; 364 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 365 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 366 367 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 368 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 369 mes_add_queue_pkt.gds_size = input->queue_size; 370 371 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 372 373 return mes_v11_0_submit_pkt_and_poll_completion(mes, 374 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 375 offsetof(union MESAPI__ADD_QUEUE, api_status)); 376 } 377 378 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 379 struct mes_remove_queue_input *input) 380 { 381 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 382 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 383 384 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 385 386 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 387 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 388 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 389 390 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 391 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 392 mes_remove_queue_pkt.gang_context_array_index = input->gang_context_array_index; 393 mes_remove_queue_pkt.queue_type = 394 convert_to_mes_queue_type(input->queue_type); 395 396 if (mes_rev >= 0x60) 397 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 398 399 return mes_v11_0_submit_pkt_and_poll_completion(mes, 400 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 401 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 402 } 403 404 static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev) 405 { 406 /* Disable the pipe reset until the CPFW fully support it.*/ 407 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 408 return false; 409 } 410 static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 411 u32 me, u32 pipe, u32 queue) 412 { 413 uint32_t reset_pipe = 0, clean_pipe = 0; 414 int r; 415 416 if (!mes_v11_0_pipe_reset_support(adev)) 417 return -EOPNOTSUPP; 418 419 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 420 mutex_lock(&adev->srbm_mutex); 421 soc21_grbm_select(adev, me, pipe, queue, 0); 422 423 switch (pipe) { 424 case 0: 425 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 426 PFP_PIPE0_RESET, 1); 427 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 428 ME_PIPE0_RESET, 1); 429 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 430 PFP_PIPE0_RESET, 0); 431 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 432 ME_PIPE0_RESET, 0); 433 break; 434 case 1: 435 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 436 PFP_PIPE1_RESET, 1); 437 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 438 ME_PIPE1_RESET, 1); 439 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 440 PFP_PIPE1_RESET, 0); 441 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 442 ME_PIPE1_RESET, 0); 443 break; 444 default: 445 break; 446 } 447 448 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 449 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 450 451 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 452 RS64_FW_UC_START_ADDR_LO; 453 soc21_grbm_select(adev, 0, 0, 0, 0); 454 mutex_unlock(&adev->srbm_mutex); 455 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 456 457 dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n", 458 r == 0 ? "successfully" : "failed"); 459 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 460 * so the pipe reset status relies on the later gfx ring test result. 461 */ 462 return 0; 463 } 464 465 /* 466 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 467 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 468 * asserted; only then clear the pipe reset bit. 469 * Caller must hold adev->srbm_mutex. 470 */ 471 static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 472 u32 pipe) 473 { 474 unsigned int q; 475 476 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 477 soc21_grbm_select(adev, me, pipe, q, 0); 478 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 479 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 480 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 481 } 482 } 483 484 static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 485 u32 me, u32 pipe, u32 queue) 486 { 487 uint32_t reset_val, clean_val; 488 int r; 489 490 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 491 mutex_lock(&adev->srbm_mutex); 492 soc21_grbm_select(adev, me, pipe, queue, 0); 493 494 if (adev->gfx.rs64_enable) { 495 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 496 clean_val = reset_val; 497 498 switch (pipe) { 499 case 0: 500 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 501 MEC_PIPE0_RESET, 1); 502 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 503 MEC_PIPE0_RESET, 0); 504 break; 505 case 1: 506 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 507 MEC_PIPE1_RESET, 1); 508 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 509 MEC_PIPE1_RESET, 0); 510 break; 511 case 2: 512 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 513 MEC_PIPE2_RESET, 1); 514 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 515 MEC_PIPE2_RESET, 0); 516 break; 517 case 3: 518 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 519 MEC_PIPE3_RESET, 1); 520 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 521 MEC_PIPE3_RESET, 0); 522 break; 523 default: 524 break; 525 } 526 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 527 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 528 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 529 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 530 RS64_FW_UC_START_ADDR_LO; 531 } else { 532 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 533 clean_val = reset_val; 534 535 if (me == 1) { 536 switch (pipe) { 537 case 0: 538 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 539 MEC_ME1_PIPE0_RESET, 1); 540 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 541 MEC_ME1_PIPE0_RESET, 0); 542 break; 543 case 1: 544 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 545 MEC_ME1_PIPE1_RESET, 1); 546 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 547 MEC_ME1_PIPE1_RESET, 0); 548 break; 549 case 2: 550 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 551 MEC_ME1_PIPE2_RESET, 1); 552 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 553 MEC_ME1_PIPE2_RESET, 0); 554 break; 555 case 3: 556 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 557 MEC_ME1_PIPE3_RESET, 1); 558 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 559 MEC_ME1_PIPE3_RESET, 0); 560 break; 561 default: 562 break; 563 } 564 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 565 } else { 566 switch (pipe) { 567 case 0: 568 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 569 MEC_ME2_PIPE0_RESET, 1); 570 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 571 MEC_ME2_PIPE0_RESET, 0); 572 break; 573 case 1: 574 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 575 MEC_ME2_PIPE1_RESET, 1); 576 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 577 MEC_ME2_PIPE1_RESET, 0); 578 break; 579 case 2: 580 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 581 MEC_ME2_PIPE2_RESET, 1); 582 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 583 MEC_ME2_PIPE2_RESET, 0); 584 break; 585 case 3: 586 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 587 MEC_ME2_PIPE3_RESET, 1); 588 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 589 MEC_ME2_PIPE3_RESET, 0); 590 break; 591 default: 592 break; 593 } 594 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 595 } 596 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 597 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 598 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 599 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 600 } 601 602 soc21_grbm_select(adev, 0, 0, 0, 0); 603 mutex_unlock(&adev->srbm_mutex); 604 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 605 606 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 607 me, pipe, queue, r == 0 ? "successfully" : "failed"); 608 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 609 * reset status relies on the compute ring test result. 610 */ 611 return 0; 612 } 613 614 static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 615 uint32_t me_id, uint32_t pipe_id, 616 uint32_t queue_id, uint32_t vmid) 617 { 618 struct amdgpu_device *adev = mes->adev; 619 620 if (queue_type == AMDGPU_RING_TYPE_GFX) 621 return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 622 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 623 return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 624 else 625 return -EOPNOTSUPP; 626 } 627 628 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 629 uint32_t me_id, uint32_t pipe_id, 630 uint32_t queue_id, uint32_t vmid) 631 { 632 struct amdgpu_device *adev = mes->adev; 633 uint32_t value, reg; 634 int i, r = 0; 635 636 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 637 638 if (queue_type == AMDGPU_RING_TYPE_GFX) { 639 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 640 me_id, pipe_id, queue_id, vmid); 641 642 mutex_lock(&adev->gfx.reset_sem_mutex); 643 gfx_v11_0_request_gfx_index_mutex(adev, true); 644 /* all se allow writes */ 645 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 646 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 647 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 648 if (pipe_id == 0) 649 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 650 else 651 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 652 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 653 gfx_v11_0_request_gfx_index_mutex(adev, false); 654 mutex_unlock(&adev->gfx.reset_sem_mutex); 655 656 mutex_lock(&adev->srbm_mutex); 657 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 658 /* wait till dequeue take effects */ 659 for (i = 0; i < adev->usec_timeout; i++) { 660 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 661 break; 662 udelay(1); 663 } 664 if (i >= adev->usec_timeout) { 665 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 666 r = -ETIMEDOUT; 667 } 668 669 soc21_grbm_select(adev, 0, 0, 0, 0); 670 mutex_unlock(&adev->srbm_mutex); 671 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 672 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 673 me_id, pipe_id, queue_id); 674 mutex_lock(&adev->srbm_mutex); 675 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 676 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 677 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 678 679 /* wait till dequeue take effects */ 680 for (i = 0; i < adev->usec_timeout; i++) { 681 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 682 break; 683 udelay(1); 684 } 685 if (i >= adev->usec_timeout) { 686 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 687 r = -ETIMEDOUT; 688 } 689 soc21_grbm_select(adev, 0, 0, 0, 0); 690 mutex_unlock(&adev->srbm_mutex); 691 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 692 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 693 me_id, pipe_id, queue_id); 694 switch (me_id) { 695 case 1: 696 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 697 break; 698 case 0: 699 default: 700 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 701 break; 702 } 703 704 value = 1 << queue_id; 705 WREG32(reg, value); 706 /* wait for queue reset done */ 707 for (i = 0; i < adev->usec_timeout; i++) { 708 if (!(RREG32(reg) & value)) 709 break; 710 udelay(1); 711 } 712 if (i >= adev->usec_timeout) { 713 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 714 r = -ETIMEDOUT; 715 } 716 } 717 718 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 719 return r; 720 } 721 722 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 723 struct mes_map_legacy_queue_input *input) 724 { 725 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 726 727 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 728 729 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 730 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 731 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 732 733 mes_add_queue_pkt.pipe_id = input->pipe_id; 734 mes_add_queue_pkt.queue_id = input->queue_id; 735 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 736 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 737 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 738 mes_add_queue_pkt.queue_type = 739 convert_to_mes_queue_type(input->queue_type); 740 mes_add_queue_pkt.map_legacy_kq = 1; 741 742 return mes_v11_0_submit_pkt_and_poll_completion(mes, 743 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 744 offsetof(union MESAPI__ADD_QUEUE, api_status)); 745 } 746 747 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 748 struct mes_unmap_legacy_queue_input *input) 749 { 750 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 751 752 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 753 754 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 755 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 756 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 757 758 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 759 mes_remove_queue_pkt.gang_context_addr = 0; 760 761 mes_remove_queue_pkt.pipe_id = input->pipe_id; 762 mes_remove_queue_pkt.queue_id = input->queue_id; 763 764 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 765 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 766 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 767 mes_remove_queue_pkt.tf_data = 768 lower_32_bits(input->trail_fence_data); 769 } else { 770 mes_remove_queue_pkt.unmap_legacy_queue = 1; 771 mes_remove_queue_pkt.queue_type = 772 convert_to_mes_queue_type(input->queue_type); 773 } 774 775 if (input->action == RESET_QUEUES && 776 (mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x60) 777 mes_remove_queue_pkt.remove_queue_after_reset = 1; 778 779 780 return mes_v11_0_submit_pkt_and_poll_completion(mes, 781 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 782 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 783 } 784 785 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 786 struct mes_suspend_gang_input *input) 787 { 788 union MESAPI__SUSPEND mes_suspend_gang_pkt; 789 790 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 791 792 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 793 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 794 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 795 796 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 797 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 798 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 799 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 800 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 801 802 return mes_v11_0_submit_pkt_and_poll_completion(mes, 803 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 804 offsetof(union MESAPI__SUSPEND, api_status)); 805 } 806 807 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 808 struct mes_resume_gang_input *input) 809 { 810 union MESAPI__RESUME mes_resume_gang_pkt; 811 812 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 813 814 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 815 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 816 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 817 818 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 819 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 820 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 821 822 return mes_v11_0_submit_pkt_and_poll_completion(mes, 823 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 824 offsetof(union MESAPI__RESUME, api_status)); 825 } 826 827 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 828 { 829 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 830 831 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 832 833 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 834 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 835 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 836 837 return mes_v11_0_submit_pkt_and_poll_completion(mes, 838 &mes_status_pkt, sizeof(mes_status_pkt), 839 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 840 } 841 842 /* 843 * QUERY_SCHEDULER_STATUS: get proc/gang context array sizes 844 */ 845 static int mes_v11_0_query_ctx_array_sizes(struct amdgpu_mes *mes) 846 { 847 struct amdgpu_device *adev = mes->adev; 848 union MESAPI__QUERY_MES_STATUS mes_query_pkt; 849 int r; 850 851 if (!mes->ctx_array_size_cpu_ptr) 852 return -EINVAL; 853 854 /* Clear the output buffer */ 855 mes->ctx_array_size_cpu_ptr[0] = 0; /* proc_ctx_array_size */ 856 mes->ctx_array_size_cpu_ptr[1] = 0; /* gang_ctx_array_size */ 857 858 memset(&mes_query_pkt, 0, sizeof(mes_query_pkt)); 859 860 mes_query_pkt.header.type = MES_API_TYPE_SCHEDULER; 861 mes_query_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 862 mes_query_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 863 864 mes_query_pkt.subopcode = MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE; 865 866 /* 867 * MES FW will write the array sizes to these GPU addresses: 868 * proc_ctx_array_size_addr -> uint32_t N (e.g., 50) 869 * gang_ctx_array_size_addr -> uint32_t M (e.g., 300) 870 */ 871 mes_query_pkt.ctx_array_size.proc_ctx_array_size_addr = 872 mes->ctx_array_size_gpu_addr; 873 mes_query_pkt.ctx_array_size.gang_ctx_array_size_addr = 874 mes->ctx_array_size_gpu_addr + sizeof(uint32_t); 875 876 mes_query_pkt.api_status.api_completion_fence_addr = 877 mes->ring[0].fence_drv.gpu_addr; 878 mes_query_pkt.api_status.api_completion_fence_value = 879 ++mes->ring[0].fence_drv.sync_seq; 880 881 r = mes_v11_0_submit_pkt_and_poll_completion(mes, 882 &mes_query_pkt, sizeof(mes_query_pkt), 883 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 884 if (r) { 885 dev_err(adev->dev, 886 "MES QUERY_SCHEDULER_STATUS (GET_CTX_ARRAY_SIZE) failed, r=%d\n", r); 887 return r; 888 } 889 890 /* MES has written the sizes - now set up bitmaps */ 891 return amdgpu_mes_rs64mem_setup_bitmaps(mes); 892 } 893 894 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 895 struct mes_misc_op_input *input) 896 { 897 union MESAPI__MISC misc_pkt; 898 899 memset(&misc_pkt, 0, sizeof(misc_pkt)); 900 901 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 902 misc_pkt.header.opcode = MES_SCH_API_MISC; 903 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 904 905 switch (input->op) { 906 case MES_MISC_OP_READ_REG: 907 misc_pkt.opcode = MESAPI_MISC__READ_REG; 908 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 909 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 910 break; 911 case MES_MISC_OP_WRITE_REG: 912 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 913 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 914 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 915 break; 916 case MES_MISC_OP_WRM_REG_WAIT: 917 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 918 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 919 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 920 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 921 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 922 misc_pkt.wait_reg_mem.reg_offset2 = 0; 923 break; 924 case MES_MISC_OP_WRM_REG_WR_WAIT: 925 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 926 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 927 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 928 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 929 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 930 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 931 break; 932 case MES_MISC_OP_SET_SHADER_DEBUGGER: 933 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 934 misc_pkt.set_shader_debugger.process_context_addr = 935 input->set_shader_debugger.process_context_addr; 936 misc_pkt.set_shader_debugger.flags.u32all = 937 input->set_shader_debugger.flags.u32all; 938 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 939 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 940 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 941 input->set_shader_debugger.tcp_watch_cntl, 942 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 943 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 944 break; 945 case MES_MISC_OP_CHANGE_CONFIG: 946 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 947 dev_warn_once(mes->adev->dev, 948 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 949 return 0; 950 } 951 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 952 misc_pkt.change_config.opcode = 953 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 954 misc_pkt.change_config.option.bits.limit_single_process = 955 input->change_config.option.limit_single_process; 956 break; 957 958 default: 959 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 960 return -EINVAL; 961 } 962 963 return mes_v11_0_submit_pkt_and_poll_completion(mes, 964 &misc_pkt, sizeof(misc_pkt), 965 offsetof(union MESAPI__MISC, api_status)); 966 } 967 968 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 969 { 970 int i; 971 struct amdgpu_device *adev = mes->adev; 972 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 973 974 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 975 976 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 977 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 978 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 979 980 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 981 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 982 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 983 mes_set_hw_res_pkt.paging_vmid = 0; 984 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 985 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 986 mes->query_status_fence_gpu_addr[0]; 987 988 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 989 mes_set_hw_res_pkt.compute_hqd_mask[i] = 990 mes->compute_hqd_mask[i]; 991 992 for (i = 0; i < MAX_GFX_PIPES; i++) 993 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 994 mes->gfx_hqd_mask[i]; 995 996 for (i = 0; i < MAX_SDMA_PIPES; i++) 997 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 998 999 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 1000 mes_set_hw_res_pkt.aggregated_doorbells[i] = 1001 mes->aggregated_doorbells[i]; 1002 1003 for (i = 0; i < 5; i++) { 1004 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 1005 mes_set_hw_res_pkt.mmhub_base[i] = 1006 adev->reg_offset[MMHUB_HWIP][0][i]; 1007 mes_set_hw_res_pkt.osssys_base[i] = 1008 adev->reg_offset[OSSSYS_HWIP][0][i]; 1009 } 1010 1011 mes_set_hw_res_pkt.disable_reset = 1; 1012 mes_set_hw_res_pkt.disable_mes_log = 1; 1013 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 1014 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 1015 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 1016 mes_set_hw_res_pkt.oversubscription_timer = 50; 1017 1018 if (amdgpu_mes_log_enable) { 1019 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 1020 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 1021 mes->event_log_gpu_addr; 1022 } 1023 1024 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 1025 mes_set_hw_res_pkt.limit_single_process = 1; 1026 1027 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1028 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1029 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 1030 } 1031 1032 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 1033 { 1034 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 1035 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 1036 1037 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 1038 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 1039 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1040 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 1041 1042 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 1043 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 1044 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 1045 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 1046 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 1047 } 1048 1049 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1050 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1051 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 1052 } 1053 1054 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 1055 struct mes_reset_queue_input *input) 1056 { 1057 union MESAPI__RESET mes_reset_queue_pkt; 1058 1059 if (input->use_mmio) { 1060 int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type, 1061 input->me_id, input->pipe_id, 1062 input->queue_id, input->vmid); 1063 if (r) 1064 return mes_v11_0_reset_pipe_mmio(mes, input->queue_type, 1065 input->me_id, input->pipe_id, 1066 input->queue_id, input->vmid); 1067 return 0; 1068 } 1069 1070 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1071 1072 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1073 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1074 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1075 1076 mes_reset_queue_pkt.queue_type = 1077 convert_to_mes_queue_type(input->queue_type); 1078 1079 if (input->legacy_gfx) { 1080 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1081 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1082 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1083 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1084 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1085 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1086 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1087 } else { 1088 mes_reset_queue_pkt.reset_queue_only = 1; 1089 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1090 } 1091 1092 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1093 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1094 offsetof(union MESAPI__RESET, api_status)); 1095 } 1096 1097 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1098 struct mes_detect_and_reset_queue_input *input) 1099 { 1100 union MESAPI__RESET mes_reset_queue_pkt; 1101 1102 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1103 1104 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1105 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1106 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1107 1108 mes_reset_queue_pkt.queue_type = 1109 convert_to_mes_queue_type(input->queue_type); 1110 mes_reset_queue_pkt.doorbell_offset_addr = 1111 mes->hung_queue_db_array_gpu_addr[0]; 1112 1113 if (input->detect_only) 1114 mes_reset_queue_pkt.hang_detect_only = 1; 1115 else 1116 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1117 1118 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1119 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1120 offsetof(union MESAPI__RESET, api_status)); 1121 } 1122 1123 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 1124 .add_hw_queue = mes_v11_0_add_hw_queue, 1125 .remove_hw_queue = mes_v11_0_remove_hw_queue, 1126 .map_legacy_queue = mes_v11_0_map_legacy_queue, 1127 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 1128 .suspend_gang = mes_v11_0_suspend_gang, 1129 .resume_gang = mes_v11_0_resume_gang, 1130 .misc_op = mes_v11_0_misc_op, 1131 .reset_hw_queue = mes_v11_0_reset_hw_queue, 1132 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 1133 }; 1134 1135 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1136 enum amdgpu_mes_pipe pipe) 1137 { 1138 int r; 1139 const struct mes_firmware_header_v1_0 *mes_hdr; 1140 const __le32 *fw_data; 1141 unsigned fw_size; 1142 1143 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1144 adev->mes.fw[pipe]->data; 1145 1146 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1147 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1148 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1149 1150 r = amdgpu_bo_create_reserved(adev, fw_size, 1151 PAGE_SIZE, 1152 AMDGPU_GEM_DOMAIN_VRAM | 1153 AMDGPU_GEM_DOMAIN_GTT, 1154 &adev->mes.ucode_fw_obj[pipe], 1155 &adev->mes.ucode_fw_gpu_addr[pipe], 1156 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1157 if (r) { 1158 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1159 return r; 1160 } 1161 1162 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1163 1164 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1165 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1166 1167 return 0; 1168 } 1169 1170 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1171 enum amdgpu_mes_pipe pipe) 1172 { 1173 int r; 1174 const struct mes_firmware_header_v1_0 *mes_hdr; 1175 const __le32 *fw_data; 1176 unsigned fw_size; 1177 1178 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1179 adev->mes.fw[pipe]->data; 1180 1181 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1182 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1183 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1184 1185 if (fw_size > GFX_MES_DRAM_SIZE) { 1186 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 1187 pipe, fw_size, GFX_MES_DRAM_SIZE); 1188 return -EINVAL; 1189 } 1190 1191 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 1192 64 * 1024, 1193 AMDGPU_GEM_DOMAIN_VRAM | 1194 AMDGPU_GEM_DOMAIN_GTT, 1195 &adev->mes.data_fw_obj[pipe], 1196 &adev->mes.data_fw_gpu_addr[pipe], 1197 (void **)&adev->mes.data_fw_ptr[pipe]); 1198 if (r) { 1199 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1200 return r; 1201 } 1202 1203 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1204 1205 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1206 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1207 1208 return 0; 1209 } 1210 1211 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 1212 enum amdgpu_mes_pipe pipe) 1213 { 1214 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1215 &adev->mes.data_fw_gpu_addr[pipe], 1216 (void **)&adev->mes.data_fw_ptr[pipe]); 1217 1218 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1219 &adev->mes.ucode_fw_gpu_addr[pipe], 1220 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1221 } 1222 1223 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 1224 { 1225 int pipe; 1226 1227 /* return early if we have already fetched these */ 1228 if (adev->mes.sched_version && adev->mes.kiq_version) 1229 return; 1230 1231 /* get MES scheduler/KIQ versions */ 1232 mutex_lock(&adev->srbm_mutex); 1233 1234 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1235 soc21_grbm_select(adev, 3, pipe, 0, 0); 1236 1237 if (pipe == AMDGPU_MES_SCHED_PIPE) 1238 adev->mes.sched_version = 1239 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1240 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1241 adev->mes.kiq_version = 1242 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1243 } 1244 1245 soc21_grbm_select(adev, 0, 0, 0, 0); 1246 mutex_unlock(&adev->srbm_mutex); 1247 } 1248 1249 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 1250 { 1251 uint64_t ucode_addr; 1252 uint32_t pipe, data = 0; 1253 1254 if (enable) { 1255 if (amdgpu_mes_log_enable) { 1256 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1257 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1258 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1259 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1260 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1261 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1262 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1263 } 1264 1265 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1266 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1267 data = REG_SET_FIELD(data, CP_MES_CNTL, 1268 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 1269 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1270 1271 mutex_lock(&adev->srbm_mutex); 1272 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1273 if (!adev->enable_mes_kiq && 1274 pipe == AMDGPU_MES_KIQ_PIPE) 1275 continue; 1276 1277 soc21_grbm_select(adev, 3, pipe, 0, 0); 1278 1279 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1280 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1281 lower_32_bits(ucode_addr)); 1282 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1283 upper_32_bits(ucode_addr)); 1284 } 1285 soc21_grbm_select(adev, 0, 0, 0, 0); 1286 mutex_unlock(&adev->srbm_mutex); 1287 1288 /* unhalt MES and activate pipe0 */ 1289 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1290 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1291 adev->enable_mes_kiq ? 1 : 0); 1292 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1293 1294 if (amdgpu_emu_mode) 1295 msleep(100); 1296 else 1297 udelay(500); 1298 } else { 1299 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1300 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1301 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1302 data = REG_SET_FIELD(data, CP_MES_CNTL, 1303 MES_INVALIDATE_ICACHE, 1); 1304 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1305 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1306 adev->enable_mes_kiq ? 1 : 0); 1307 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1308 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1309 } 1310 } 1311 1312 /* This function is for backdoor MES firmware */ 1313 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1314 enum amdgpu_mes_pipe pipe, bool prime_icache) 1315 { 1316 int r; 1317 uint32_t data; 1318 uint64_t ucode_addr; 1319 1320 mes_v11_0_enable(adev, false); 1321 1322 if (!adev->mes.fw[pipe]) 1323 return -EINVAL; 1324 1325 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1326 if (r) 1327 return r; 1328 1329 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1330 if (r) { 1331 mes_v11_0_free_ucode_buffers(adev, pipe); 1332 return r; 1333 } 1334 1335 mutex_lock(&adev->srbm_mutex); 1336 /* me=3, pipe=0, queue=0 */ 1337 soc21_grbm_select(adev, 3, pipe, 0, 0); 1338 1339 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1340 1341 /* set ucode start address */ 1342 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1343 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1344 lower_32_bits(ucode_addr)); 1345 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1346 upper_32_bits(ucode_addr)); 1347 1348 /* set ucode fimrware address */ 1349 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1350 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1351 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1352 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1353 1354 /* set ucode instruction cache boundary to 2M-1 */ 1355 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1356 1357 /* set ucode data firmware address */ 1358 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1359 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1360 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1361 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1362 1363 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1364 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1365 1366 if (prime_icache) { 1367 /* invalidate ICACHE */ 1368 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1369 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1370 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1371 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1372 1373 /* prime the ICACHE. */ 1374 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1375 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1376 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1377 } 1378 1379 soc21_grbm_select(adev, 0, 0, 0, 0); 1380 mutex_unlock(&adev->srbm_mutex); 1381 1382 return 0; 1383 } 1384 1385 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1386 enum amdgpu_mes_pipe pipe) 1387 { 1388 int r; 1389 u32 *eop; 1390 1391 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1392 AMDGPU_GEM_DOMAIN_GTT, 1393 &adev->mes.eop_gpu_obj[pipe], 1394 &adev->mes.eop_gpu_addr[pipe], 1395 (void **)&eop); 1396 if (r) { 1397 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1398 return r; 1399 } 1400 1401 memset(eop, 0, 1402 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1403 1404 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1405 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1406 1407 return 0; 1408 } 1409 1410 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1411 { 1412 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1413 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1414 uint32_t tmp; 1415 1416 memset(mqd, 0, sizeof(*mqd)); 1417 1418 mqd->header = 0xC0310800; 1419 mqd->compute_pipelinestat_enable = 0x00000001; 1420 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1421 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1422 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1423 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1424 mqd->compute_misc_reserved = 0x00000007; 1425 1426 eop_base_addr = ring->eop_gpu_addr >> 8; 1427 1428 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1429 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1430 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1431 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1432 1433 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1434 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1435 mqd->cp_hqd_eop_control = tmp; 1436 1437 /* disable the queue if it's active */ 1438 ring->wptr = 0; 1439 mqd->cp_hqd_pq_rptr = 0; 1440 mqd->cp_hqd_pq_wptr_lo = 0; 1441 mqd->cp_hqd_pq_wptr_hi = 0; 1442 1443 /* set the pointer to the MQD */ 1444 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1445 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1446 1447 /* set MQD vmid to 0 */ 1448 tmp = regCP_MQD_CONTROL_DEFAULT; 1449 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1450 mqd->cp_mqd_control = tmp; 1451 1452 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1453 hqd_gpu_addr = ring->gpu_addr >> 8; 1454 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1455 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1456 1457 /* set the wb address whether it's enabled or not */ 1458 wb_gpu_addr = ring->rptr_gpu_addr; 1459 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1460 mqd->cp_hqd_pq_rptr_report_addr_hi = 1461 upper_32_bits(wb_gpu_addr) & 0xffff; 1462 1463 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1464 wb_gpu_addr = ring->wptr_gpu_addr; 1465 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1466 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1467 1468 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1469 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1470 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1471 (order_base_2(ring->ring_size / 4) - 1)); 1472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1473 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1474 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1476 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1477 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1478 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1479 mqd->cp_hqd_pq_control = tmp; 1480 1481 /* enable doorbell */ 1482 tmp = 0; 1483 if (ring->use_doorbell) { 1484 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1485 DOORBELL_OFFSET, ring->doorbell_index); 1486 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1487 DOORBELL_EN, 1); 1488 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1489 DOORBELL_SOURCE, 0); 1490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1491 DOORBELL_HIT, 0); 1492 } else 1493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1494 DOORBELL_EN, 0); 1495 mqd->cp_hqd_pq_doorbell_control = tmp; 1496 1497 mqd->cp_hqd_vmid = 0; 1498 /* activate the queue */ 1499 mqd->cp_hqd_active = 1; 1500 1501 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1502 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1503 PRELOAD_SIZE, 0x55); 1504 mqd->cp_hqd_persistent_state = tmp; 1505 1506 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1507 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1508 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1509 1510 amdgpu_device_flush_hdp(ring->adev, NULL); 1511 return 0; 1512 } 1513 1514 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1515 { 1516 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1517 struct amdgpu_device *adev = ring->adev; 1518 uint32_t data = 0; 1519 1520 mutex_lock(&adev->srbm_mutex); 1521 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1522 1523 /* set CP_HQD_VMID.VMID = 0. */ 1524 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1525 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1526 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1527 1528 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1529 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1530 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1531 DOORBELL_EN, 0); 1532 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1533 1534 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1535 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1536 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1537 1538 /* set CP_MQD_CONTROL.VMID=0 */ 1539 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1540 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1541 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1542 1543 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1544 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1545 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1546 1547 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1548 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1549 mqd->cp_hqd_pq_rptr_report_addr_lo); 1550 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1551 mqd->cp_hqd_pq_rptr_report_addr_hi); 1552 1553 /* set CP_HQD_PQ_CONTROL */ 1554 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1555 1556 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1557 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1558 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1559 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1560 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1561 1562 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1563 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1564 mqd->cp_hqd_pq_doorbell_control); 1565 1566 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1567 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1568 1569 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1570 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1571 1572 soc21_grbm_select(adev, 0, 0, 0, 0); 1573 mutex_unlock(&adev->srbm_mutex); 1574 } 1575 1576 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1577 { 1578 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1579 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1580 int r; 1581 1582 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1583 return -EINVAL; 1584 1585 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1586 if (r) { 1587 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1588 return r; 1589 } 1590 1591 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1592 1593 return amdgpu_ring_test_helper(kiq_ring); 1594 } 1595 1596 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1597 enum amdgpu_mes_pipe pipe) 1598 { 1599 struct amdgpu_ring *ring; 1600 int r; 1601 1602 if (pipe == AMDGPU_MES_KIQ_PIPE) 1603 ring = &adev->gfx.kiq[0].ring; 1604 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1605 ring = &adev->mes.ring[0]; 1606 else 1607 BUG(); 1608 1609 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1610 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1611 *(ring->wptr_cpu_addr) = 0; 1612 *(ring->rptr_cpu_addr) = 0; 1613 amdgpu_ring_clear_ring(ring); 1614 } 1615 1616 r = mes_v11_0_mqd_init(ring); 1617 if (r) 1618 return r; 1619 1620 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1621 r = mes_v11_0_kiq_enable_queue(adev); 1622 if (r) 1623 return r; 1624 } else { 1625 mes_v11_0_queue_init_register(ring); 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1632 { 1633 struct amdgpu_ring *ring; 1634 1635 ring = &adev->mes.ring[0]; 1636 1637 ring->funcs = &mes_v11_0_ring_funcs; 1638 1639 ring->me = 3; 1640 ring->pipe = 0; 1641 ring->queue = 0; 1642 1643 ring->ring_obj = NULL; 1644 ring->use_doorbell = true; 1645 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1646 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1647 ring->no_scheduler = true; 1648 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1649 1650 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1651 AMDGPU_RING_PRIO_DEFAULT, NULL); 1652 } 1653 1654 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1655 { 1656 struct amdgpu_ring *ring; 1657 1658 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1659 1660 ring = &adev->gfx.kiq[0].ring; 1661 1662 ring->me = 3; 1663 ring->pipe = 1; 1664 ring->queue = 0; 1665 1666 ring->adev = NULL; 1667 ring->ring_obj = NULL; 1668 ring->use_doorbell = true; 1669 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1670 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1671 ring->no_scheduler = true; 1672 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1673 ring->me, ring->pipe, ring->queue); 1674 1675 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1676 AMDGPU_RING_PRIO_DEFAULT, NULL); 1677 } 1678 1679 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1680 enum amdgpu_mes_pipe pipe) 1681 { 1682 int r, mqd_size = sizeof(struct v11_compute_mqd); 1683 struct amdgpu_ring *ring; 1684 1685 if (pipe == AMDGPU_MES_KIQ_PIPE) 1686 ring = &adev->gfx.kiq[0].ring; 1687 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1688 ring = &adev->mes.ring[0]; 1689 else 1690 BUG(); 1691 1692 if (ring->mqd_obj) 1693 return 0; 1694 1695 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1696 AMDGPU_GEM_DOMAIN_VRAM | 1697 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1698 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1699 if (r) { 1700 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1701 return r; 1702 } 1703 1704 memset(ring->mqd_ptr, 0, mqd_size); 1705 1706 /* prepare MQD backup */ 1707 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1708 if (!adev->mes.mqd_backup[pipe]) { 1709 dev_warn(adev->dev, 1710 "no memory to create MQD backup for ring %s\n", 1711 ring->name); 1712 return -ENOMEM; 1713 } 1714 1715 return 0; 1716 } 1717 1718 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1719 { 1720 struct amdgpu_device *adev = ip_block->adev; 1721 int pipe, r, bo_size; 1722 1723 adev->mes.funcs = &mes_v11_0_funcs; 1724 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1725 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1726 1727 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1728 1729 r = amdgpu_mes_init(adev); 1730 if (r) 1731 return r; 1732 1733 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1734 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1735 continue; 1736 1737 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1738 if (r) 1739 return r; 1740 1741 r = mes_v11_0_mqd_sw_init(adev, pipe); 1742 if (r) 1743 return r; 1744 } 1745 1746 if (adev->enable_mes_kiq) { 1747 r = mes_v11_0_kiq_ring_init(adev); 1748 if (r) 1749 return r; 1750 } 1751 1752 r = mes_v11_0_ring_init(adev); 1753 if (r) 1754 return r; 1755 1756 bo_size = AMDGPU_GPU_PAGE_SIZE; 1757 if (amdgpu_sriov_is_mes_info_enable(adev)) 1758 bo_size += MES11_HW_RESOURCE_1_SIZE; 1759 1760 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1761 r = amdgpu_bo_create_kernel(adev, 1762 bo_size, 1763 PAGE_SIZE, 1764 AMDGPU_GEM_DOMAIN_VRAM, 1765 &adev->mes.resource_1[0], 1766 &adev->mes.resource_1_gpu_addr[0], 1767 &adev->mes.resource_1_addr[0]); 1768 if (r) { 1769 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1770 return r; 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1777 { 1778 struct amdgpu_device *adev = ip_block->adev; 1779 int pipe; 1780 1781 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1782 &adev->mes.resource_1_addr[0]); 1783 1784 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1785 kfree(adev->mes.mqd_backup[pipe]); 1786 1787 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1788 &adev->mes.eop_gpu_addr[pipe], 1789 NULL); 1790 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1791 } 1792 1793 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1794 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1795 &adev->gfx.kiq[0].ring.mqd_ptr); 1796 1797 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1798 &adev->mes.ring[0].mqd_gpu_addr, 1799 &adev->mes.ring[0].mqd_ptr); 1800 1801 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1802 amdgpu_ring_fini(&adev->mes.ring[0]); 1803 1804 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1805 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1806 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1807 } 1808 1809 amdgpu_mes_fini(adev); 1810 return 0; 1811 } 1812 1813 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1814 { 1815 uint32_t data; 1816 int i; 1817 struct amdgpu_device *adev = ring->adev; 1818 1819 mutex_lock(&adev->srbm_mutex); 1820 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1821 1822 /* disable the queue if it's active */ 1823 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1824 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1825 for (i = 0; i < adev->usec_timeout; i++) { 1826 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1827 break; 1828 udelay(1); 1829 } 1830 } 1831 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1832 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1833 DOORBELL_EN, 0); 1834 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1835 DOORBELL_HIT, 1); 1836 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1837 1838 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1839 1840 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1841 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1842 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1843 1844 soc21_grbm_select(adev, 0, 0, 0, 0); 1845 mutex_unlock(&adev->srbm_mutex); 1846 } 1847 1848 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1849 { 1850 uint32_t tmp; 1851 struct amdgpu_device *adev = ring->adev; 1852 1853 /* tell RLC which is KIQ queue */ 1854 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1855 tmp &= 0xffffff00; 1856 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1857 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1858 } 1859 1860 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1861 { 1862 uint32_t tmp; 1863 1864 /* tell RLC which is KIQ dequeue */ 1865 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1866 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1867 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1868 } 1869 1870 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1871 { 1872 int r = 0; 1873 struct amdgpu_ip_block *ip_block; 1874 1875 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1876 1877 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1878 if (r) { 1879 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1880 return r; 1881 } 1882 1883 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1884 if (r) { 1885 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1886 return r; 1887 } 1888 1889 } 1890 1891 mes_v11_0_enable(adev, true); 1892 1893 mes_v11_0_get_fw_version(adev); 1894 1895 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1896 1897 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1898 if (unlikely(!ip_block)) { 1899 dev_err(adev->dev, "Failed to get MES handle\n"); 1900 return -EINVAL; 1901 } 1902 1903 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1904 if (r) 1905 goto failure; 1906 1907 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1908 adev->mes.enable_legacy_queue_map = true; 1909 else 1910 adev->mes.enable_legacy_queue_map = false; 1911 1912 if (adev->mes.enable_legacy_queue_map) { 1913 r = mes_v11_0_hw_init(ip_block); 1914 if (r) 1915 goto failure; 1916 } 1917 1918 return r; 1919 1920 failure: 1921 mes_v11_0_hw_fini(ip_block); 1922 return r; 1923 } 1924 1925 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1926 { 1927 if (adev->mes.ring[0].sched.ready) { 1928 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1929 adev->mes.ring[0].sched.ready = false; 1930 } 1931 1932 if (amdgpu_sriov_vf(adev)) { 1933 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1934 mes_v11_0_kiq_clear(adev); 1935 } 1936 1937 mes_v11_0_enable(adev, false); 1938 1939 return 0; 1940 } 1941 1942 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1943 { 1944 int r; 1945 struct amdgpu_device *adev = ip_block->adev; 1946 1947 if (adev->mes.ring[0].sched.ready) 1948 goto out; 1949 1950 if (!adev->enable_mes_kiq) { 1951 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1952 r = mes_v11_0_load_microcode(adev, 1953 AMDGPU_MES_SCHED_PIPE, true); 1954 if (r) { 1955 DRM_ERROR("failed to MES fw, r=%d\n", r); 1956 return r; 1957 } 1958 } 1959 1960 mes_v11_0_enable(adev, true); 1961 } 1962 1963 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1964 if (r) 1965 goto failure; 1966 1967 /* Allocate GPU buffer for array size query results */ 1968 r = amdgpu_mes_rs64mem_init(&adev->mes); 1969 if (r) 1970 dev_warn(adev->dev, 1971 "RS64 local memory init failed (%d)," 1972 "falling back to system memory path\n", r); 1973 1974 r = mes_v11_0_set_hw_resources(&adev->mes); 1975 1976 if (r) 1977 goto failure; 1978 1979 /* 1980 * QUERY_SCHEDULER_STATUS to get array sizes (N, M). 1981 * MES writes the sizes to the GPU buffer, then we allocate bitmaps. 1982 */ 1983 if (adev->mes.use_rs64mem) { 1984 r = mes_v11_0_query_ctx_array_sizes(&adev->mes); 1985 if (r) { 1986 dev_warn(adev->dev, 1987 "Failed to query ctx array sizes (%d)," 1988 "disabling RS64 local memory\n", r); 1989 /* Continue without optimization - not fatal */ 1990 } 1991 } 1992 1993 1994 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1995 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1996 if (r) { 1997 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1998 goto failure; 1999 } 2000 } 2001 2002 r = mes_v11_0_query_sched_status(&adev->mes); 2003 if (r) { 2004 DRM_ERROR("MES is busy\n"); 2005 goto failure; 2006 } 2007 2008 r = amdgpu_mes_update_enforce_isolation(adev); 2009 if (r) 2010 goto failure; 2011 2012 amdgpu_mes_validate_fw_version(adev); 2013 out: 2014 /* 2015 * Disable KIQ ring usage from the driver once MES is enabled. 2016 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 2017 * with MES enabled. 2018 */ 2019 adev->gfx.kiq[0].ring.sched.ready = false; 2020 adev->mes.ring[0].sched.ready = true; 2021 2022 return 0; 2023 2024 failure: 2025 mes_v11_0_hw_fini(ip_block); 2026 return r; 2027 } 2028 2029 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 2030 { 2031 struct amdgpu_device *adev = ip_block->adev; 2032 2033 if (adev->mes.use_rs64mem) 2034 amdgpu_mes_rs64mem_fini(&adev->mes); 2035 return 0; 2036 } 2037 2038 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 2039 { 2040 return mes_v11_0_hw_fini(ip_block); 2041 } 2042 2043 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 2044 { 2045 return mes_v11_0_hw_init(ip_block); 2046 } 2047 2048 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 2049 { 2050 struct amdgpu_device *adev = ip_block->adev; 2051 int pipe, r; 2052 2053 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 2054 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 2055 2056 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 2057 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 2058 continue; 2059 r = amdgpu_mes_init_microcode(adev, pipe); 2060 if (r) 2061 return r; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 2068 .name = "mes_v11_0", 2069 .early_init = mes_v11_0_early_init, 2070 .late_init = NULL, 2071 .sw_init = mes_v11_0_sw_init, 2072 .sw_fini = mes_v11_0_sw_fini, 2073 .hw_init = mes_v11_0_hw_init, 2074 .hw_fini = mes_v11_0_hw_fini, 2075 .suspend = mes_v11_0_suspend, 2076 .resume = mes_v11_0_resume, 2077 }; 2078 2079 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 2080 .type = AMD_IP_BLOCK_TYPE_MES, 2081 .major = 11, 2082 .minor = 0, 2083 .rev = 0, 2084 .funcs = &mes_v11_0_ip_funcs, 2085 }; 2086