1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 55 static int mes_v11_0_hw_init(void *handle); 56 static int mes_v11_0_hw_fini(void *handle); 57 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 58 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 59 60 #define MES_EOP_SIZE 2048 61 #define GFX_MES_DRAM_SIZE 0x80000 62 63 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 if (ring->use_doorbell) { 68 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 69 ring->wptr); 70 WDOORBELL64(ring->doorbell_index, ring->wptr); 71 } else { 72 BUG(); 73 } 74 } 75 76 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 77 { 78 return *ring->rptr_cpu_addr; 79 } 80 81 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 82 { 83 u64 wptr; 84 85 if (ring->use_doorbell) 86 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 87 else 88 BUG(); 89 return wptr; 90 } 91 92 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 93 .type = AMDGPU_RING_TYPE_MES, 94 .align_mask = 1, 95 .nop = 0, 96 .support_64bit_ptrs = true, 97 .get_rptr = mes_v11_0_ring_get_rptr, 98 .get_wptr = mes_v11_0_ring_get_wptr, 99 .set_wptr = mes_v11_0_ring_set_wptr, 100 .insert_nop = amdgpu_ring_insert_nop, 101 }; 102 103 static const char *mes_v11_0_opcodes[] = { 104 "SET_HW_RSRC", 105 "SET_SCHEDULING_CONFIG", 106 "ADD_QUEUE", 107 "REMOVE_QUEUE", 108 "PERFORM_YIELD", 109 "SET_GANG_PRIORITY_LEVEL", 110 "SUSPEND", 111 "RESUME", 112 "RESET", 113 "SET_LOG_BUFFER", 114 "CHANGE_GANG_PRORITY", 115 "QUERY_SCHEDULER_STATUS", 116 "PROGRAM_GDS", 117 "SET_DEBUG_VMID", 118 "MISC", 119 "UPDATE_ROOT_PAGE_TABLE", 120 "AMD_LOG", 121 }; 122 123 static const char *mes_v11_0_misc_opcodes[] = { 124 "WRITE_REG", 125 "INV_GART", 126 "QUERY_STATUS", 127 "READ_REG", 128 "WAIT_REG_MEM", 129 "SET_SHADER_DEBUGGER", 130 }; 131 132 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 133 { 134 const char *op_str = NULL; 135 136 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 137 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 138 139 return op_str; 140 } 141 142 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 143 { 144 const char *op_str = NULL; 145 146 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 147 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 148 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 149 150 return op_str; 151 } 152 153 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 154 void *pkt, int size, 155 int api_status_off) 156 { 157 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 158 signed long timeout = 3000000; /* 3000 ms */ 159 struct amdgpu_device *adev = mes->adev; 160 struct amdgpu_ring *ring = &mes->ring; 161 struct MES_API_STATUS *api_status; 162 union MESAPI__MISC *x_pkt = pkt; 163 const char *op_str, *misc_op_str; 164 unsigned long flags; 165 u64 status_gpu_addr; 166 u32 status_offset; 167 u64 *status_ptr; 168 signed long r; 169 int ret; 170 171 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 172 return -EINVAL; 173 174 if (amdgpu_emu_mode) { 175 timeout *= 100; 176 } else if (amdgpu_sriov_vf(adev)) { 177 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 178 timeout = 15 * 600 * 1000; 179 } 180 181 ret = amdgpu_device_wb_get(adev, &status_offset); 182 if (ret) 183 return ret; 184 185 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 186 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 187 *status_ptr = 0; 188 189 spin_lock_irqsave(&mes->ring_lock, flags); 190 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 191 if (r) 192 goto error_unlock_free; 193 194 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 195 api_status->api_completion_fence_addr = status_gpu_addr; 196 api_status->api_completion_fence_value = 1; 197 198 amdgpu_ring_write_multiple(ring, pkt, size / 4); 199 200 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 201 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 202 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 203 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 204 mes_status_pkt.api_status.api_completion_fence_addr = 205 ring->fence_drv.gpu_addr; 206 mes_status_pkt.api_status.api_completion_fence_value = 207 ++ring->fence_drv.sync_seq; 208 209 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 210 sizeof(mes_status_pkt) / 4); 211 212 amdgpu_ring_commit(ring); 213 spin_unlock_irqrestore(&mes->ring_lock, flags); 214 215 op_str = mes_v11_0_get_op_string(x_pkt); 216 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 217 218 if (misc_op_str) 219 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 220 misc_op_str); 221 else if (op_str) 222 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 223 else 224 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 225 x_pkt->header.opcode); 226 227 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, timeout); 228 if (r < 1 || !*status_ptr) { 229 230 if (misc_op_str) 231 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 232 op_str, misc_op_str); 233 else if (op_str) 234 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 235 op_str); 236 else 237 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 238 x_pkt->header.opcode); 239 240 while (halt_if_hws_hang) 241 schedule(); 242 243 r = -ETIMEDOUT; 244 goto error_wb_free; 245 } 246 247 amdgpu_device_wb_free(adev, status_offset); 248 return 0; 249 250 error_unlock_free: 251 spin_unlock_irqrestore(&mes->ring_lock, flags); 252 253 error_wb_free: 254 amdgpu_device_wb_free(adev, status_offset); 255 return r; 256 } 257 258 static int convert_to_mes_queue_type(int queue_type) 259 { 260 if (queue_type == AMDGPU_RING_TYPE_GFX) 261 return MES_QUEUE_TYPE_GFX; 262 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 263 return MES_QUEUE_TYPE_COMPUTE; 264 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 265 return MES_QUEUE_TYPE_SDMA; 266 else 267 BUG(); 268 return -1; 269 } 270 271 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 272 struct mes_add_queue_input *input) 273 { 274 struct amdgpu_device *adev = mes->adev; 275 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 276 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 277 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 278 279 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 280 281 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 282 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 283 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 284 285 mes_add_queue_pkt.process_id = input->process_id; 286 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 287 mes_add_queue_pkt.process_va_start = input->process_va_start; 288 mes_add_queue_pkt.process_va_end = input->process_va_end; 289 mes_add_queue_pkt.process_quantum = input->process_quantum; 290 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 291 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 292 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 293 mes_add_queue_pkt.inprocess_gang_priority = 294 input->inprocess_gang_priority; 295 mes_add_queue_pkt.gang_global_priority_level = 296 input->gang_global_priority_level; 297 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 298 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 299 300 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 301 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 302 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 303 else 304 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 305 306 mes_add_queue_pkt.queue_type = 307 convert_to_mes_queue_type(input->queue_type); 308 mes_add_queue_pkt.paging = input->paging; 309 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 310 mes_add_queue_pkt.gws_base = input->gws_base; 311 mes_add_queue_pkt.gws_size = input->gws_size; 312 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 313 mes_add_queue_pkt.tma_addr = input->tma_addr; 314 mes_add_queue_pkt.trap_en = input->trap_en; 315 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 316 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 317 318 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 319 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 320 mes_add_queue_pkt.gds_size = input->queue_size; 321 322 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 323 324 return mes_v11_0_submit_pkt_and_poll_completion(mes, 325 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 326 offsetof(union MESAPI__ADD_QUEUE, api_status)); 327 } 328 329 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 330 struct mes_remove_queue_input *input) 331 { 332 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 333 334 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 335 336 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 337 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 338 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 339 340 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 341 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 342 343 return mes_v11_0_submit_pkt_and_poll_completion(mes, 344 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 345 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 346 } 347 348 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 349 struct mes_map_legacy_queue_input *input) 350 { 351 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 352 353 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 354 355 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 356 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 357 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 358 359 mes_add_queue_pkt.pipe_id = input->pipe_id; 360 mes_add_queue_pkt.queue_id = input->queue_id; 361 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 362 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 363 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 364 mes_add_queue_pkt.queue_type = 365 convert_to_mes_queue_type(input->queue_type); 366 mes_add_queue_pkt.map_legacy_kq = 1; 367 368 return mes_v11_0_submit_pkt_and_poll_completion(mes, 369 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 370 offsetof(union MESAPI__ADD_QUEUE, api_status)); 371 } 372 373 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 374 struct mes_unmap_legacy_queue_input *input) 375 { 376 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 377 378 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 379 380 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 381 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 382 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 383 384 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 385 mes_remove_queue_pkt.gang_context_addr = 0; 386 387 mes_remove_queue_pkt.pipe_id = input->pipe_id; 388 mes_remove_queue_pkt.queue_id = input->queue_id; 389 390 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 391 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 392 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 393 mes_remove_queue_pkt.tf_data = 394 lower_32_bits(input->trail_fence_data); 395 } else { 396 mes_remove_queue_pkt.unmap_legacy_queue = 1; 397 mes_remove_queue_pkt.queue_type = 398 convert_to_mes_queue_type(input->queue_type); 399 } 400 401 return mes_v11_0_submit_pkt_and_poll_completion(mes, 402 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 403 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 404 } 405 406 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 407 struct mes_suspend_gang_input *input) 408 { 409 return 0; 410 } 411 412 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 413 struct mes_resume_gang_input *input) 414 { 415 return 0; 416 } 417 418 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 419 { 420 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 421 422 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 423 424 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 425 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 426 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 427 428 return mes_v11_0_submit_pkt_and_poll_completion(mes, 429 &mes_status_pkt, sizeof(mes_status_pkt), 430 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 431 } 432 433 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 434 struct mes_misc_op_input *input) 435 { 436 union MESAPI__MISC misc_pkt; 437 438 memset(&misc_pkt, 0, sizeof(misc_pkt)); 439 440 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 441 misc_pkt.header.opcode = MES_SCH_API_MISC; 442 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 443 444 switch (input->op) { 445 case MES_MISC_OP_READ_REG: 446 misc_pkt.opcode = MESAPI_MISC__READ_REG; 447 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 448 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 449 break; 450 case MES_MISC_OP_WRITE_REG: 451 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 452 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 453 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 454 break; 455 case MES_MISC_OP_WRM_REG_WAIT: 456 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 457 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 458 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 459 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 460 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 461 misc_pkt.wait_reg_mem.reg_offset2 = 0; 462 break; 463 case MES_MISC_OP_WRM_REG_WR_WAIT: 464 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 465 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 466 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 467 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 468 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 469 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 470 break; 471 case MES_MISC_OP_SET_SHADER_DEBUGGER: 472 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 473 misc_pkt.set_shader_debugger.process_context_addr = 474 input->set_shader_debugger.process_context_addr; 475 misc_pkt.set_shader_debugger.flags.u32all = 476 input->set_shader_debugger.flags.u32all; 477 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 478 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 479 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 480 input->set_shader_debugger.tcp_watch_cntl, 481 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 482 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 483 break; 484 default: 485 DRM_ERROR("unsupported misc op (%d) \n", input->op); 486 return -EINVAL; 487 } 488 489 return mes_v11_0_submit_pkt_and_poll_completion(mes, 490 &misc_pkt, sizeof(misc_pkt), 491 offsetof(union MESAPI__MISC, api_status)); 492 } 493 494 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 495 { 496 int i; 497 struct amdgpu_device *adev = mes->adev; 498 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 499 500 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 501 502 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 503 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 504 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 505 506 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 507 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 508 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 509 mes_set_hw_res_pkt.paging_vmid = 0; 510 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 511 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 512 mes->query_status_fence_gpu_addr; 513 514 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 515 mes_set_hw_res_pkt.compute_hqd_mask[i] = 516 mes->compute_hqd_mask[i]; 517 518 for (i = 0; i < MAX_GFX_PIPES; i++) 519 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 520 521 for (i = 0; i < MAX_SDMA_PIPES; i++) 522 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 523 524 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 525 mes_set_hw_res_pkt.aggregated_doorbells[i] = 526 mes->aggregated_doorbells[i]; 527 528 for (i = 0; i < 5; i++) { 529 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 530 mes_set_hw_res_pkt.mmhub_base[i] = 531 adev->reg_offset[MMHUB_HWIP][0][i]; 532 mes_set_hw_res_pkt.osssys_base[i] = 533 adev->reg_offset[OSSSYS_HWIP][0][i]; 534 } 535 536 mes_set_hw_res_pkt.disable_reset = 1; 537 mes_set_hw_res_pkt.disable_mes_log = 1; 538 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 539 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 540 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 541 mes_set_hw_res_pkt.oversubscription_timer = 50; 542 if (amdgpu_mes_log_enable) { 543 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 544 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 545 mes->event_log_gpu_addr; 546 } 547 548 return mes_v11_0_submit_pkt_and_poll_completion(mes, 549 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 550 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 551 } 552 553 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 554 { 555 int size = 128 * PAGE_SIZE; 556 int ret = 0; 557 struct amdgpu_device *adev = mes->adev; 558 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 559 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 560 561 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 562 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 563 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 564 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 565 566 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 567 AMDGPU_GEM_DOMAIN_VRAM, 568 &mes->resource_1, 569 &mes->resource_1_gpu_addr, 570 &mes->resource_1_addr); 571 if (ret) { 572 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 573 return ret; 574 } 575 576 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 577 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 578 return mes_v11_0_submit_pkt_and_poll_completion(mes, 579 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 580 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 581 } 582 583 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 584 .add_hw_queue = mes_v11_0_add_hw_queue, 585 .remove_hw_queue = mes_v11_0_remove_hw_queue, 586 .map_legacy_queue = mes_v11_0_map_legacy_queue, 587 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 588 .suspend_gang = mes_v11_0_suspend_gang, 589 .resume_gang = mes_v11_0_resume_gang, 590 .misc_op = mes_v11_0_misc_op, 591 }; 592 593 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 594 enum admgpu_mes_pipe pipe) 595 { 596 int r; 597 const struct mes_firmware_header_v1_0 *mes_hdr; 598 const __le32 *fw_data; 599 unsigned fw_size; 600 601 mes_hdr = (const struct mes_firmware_header_v1_0 *) 602 adev->mes.fw[pipe]->data; 603 604 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 605 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 606 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 607 608 r = amdgpu_bo_create_reserved(adev, fw_size, 609 PAGE_SIZE, 610 AMDGPU_GEM_DOMAIN_VRAM | 611 AMDGPU_GEM_DOMAIN_GTT, 612 &adev->mes.ucode_fw_obj[pipe], 613 &adev->mes.ucode_fw_gpu_addr[pipe], 614 (void **)&adev->mes.ucode_fw_ptr[pipe]); 615 if (r) { 616 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 617 return r; 618 } 619 620 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 621 622 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 623 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 624 625 return 0; 626 } 627 628 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 629 enum admgpu_mes_pipe pipe) 630 { 631 int r; 632 const struct mes_firmware_header_v1_0 *mes_hdr; 633 const __le32 *fw_data; 634 unsigned fw_size; 635 636 mes_hdr = (const struct mes_firmware_header_v1_0 *) 637 adev->mes.fw[pipe]->data; 638 639 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 640 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 641 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 642 643 if (fw_size > GFX_MES_DRAM_SIZE) { 644 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 645 pipe, fw_size, GFX_MES_DRAM_SIZE); 646 return -EINVAL; 647 } 648 649 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 650 64 * 1024, 651 AMDGPU_GEM_DOMAIN_VRAM | 652 AMDGPU_GEM_DOMAIN_GTT, 653 &adev->mes.data_fw_obj[pipe], 654 &adev->mes.data_fw_gpu_addr[pipe], 655 (void **)&adev->mes.data_fw_ptr[pipe]); 656 if (r) { 657 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 658 return r; 659 } 660 661 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 662 663 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 664 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 665 666 return 0; 667 } 668 669 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 670 enum admgpu_mes_pipe pipe) 671 { 672 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 673 &adev->mes.data_fw_gpu_addr[pipe], 674 (void **)&adev->mes.data_fw_ptr[pipe]); 675 676 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 677 &adev->mes.ucode_fw_gpu_addr[pipe], 678 (void **)&adev->mes.ucode_fw_ptr[pipe]); 679 } 680 681 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 682 { 683 uint64_t ucode_addr; 684 uint32_t pipe, data = 0; 685 686 if (enable) { 687 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 688 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 689 data = REG_SET_FIELD(data, CP_MES_CNTL, 690 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 691 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 692 693 mutex_lock(&adev->srbm_mutex); 694 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 695 if (!adev->enable_mes_kiq && 696 pipe == AMDGPU_MES_KIQ_PIPE) 697 continue; 698 699 soc21_grbm_select(adev, 3, pipe, 0, 0); 700 701 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 702 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 703 lower_32_bits(ucode_addr)); 704 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 705 upper_32_bits(ucode_addr)); 706 } 707 soc21_grbm_select(adev, 0, 0, 0, 0); 708 mutex_unlock(&adev->srbm_mutex); 709 710 /* unhalt MES and activate pipe0 */ 711 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 712 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 713 adev->enable_mes_kiq ? 1 : 0); 714 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 715 716 if (amdgpu_emu_mode) 717 msleep(100); 718 else 719 udelay(500); 720 } else { 721 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 722 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 723 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 724 data = REG_SET_FIELD(data, CP_MES_CNTL, 725 MES_INVALIDATE_ICACHE, 1); 726 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 727 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 728 adev->enable_mes_kiq ? 1 : 0); 729 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 730 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 731 } 732 } 733 734 /* This function is for backdoor MES firmware */ 735 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 736 enum admgpu_mes_pipe pipe, bool prime_icache) 737 { 738 int r; 739 uint32_t data; 740 uint64_t ucode_addr; 741 742 mes_v11_0_enable(adev, false); 743 744 if (!adev->mes.fw[pipe]) 745 return -EINVAL; 746 747 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 748 if (r) 749 return r; 750 751 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 752 if (r) { 753 mes_v11_0_free_ucode_buffers(adev, pipe); 754 return r; 755 } 756 757 mutex_lock(&adev->srbm_mutex); 758 /* me=3, pipe=0, queue=0 */ 759 soc21_grbm_select(adev, 3, pipe, 0, 0); 760 761 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 762 763 /* set ucode start address */ 764 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 765 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 766 lower_32_bits(ucode_addr)); 767 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 768 upper_32_bits(ucode_addr)); 769 770 /* set ucode fimrware address */ 771 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 772 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 773 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 774 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 775 776 /* set ucode instruction cache boundary to 2M-1 */ 777 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 778 779 /* set ucode data firmware address */ 780 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 781 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 782 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 783 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 784 785 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 786 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 787 788 if (prime_icache) { 789 /* invalidate ICACHE */ 790 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 791 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 792 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 793 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 794 795 /* prime the ICACHE. */ 796 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 797 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 798 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 799 } 800 801 soc21_grbm_select(adev, 0, 0, 0, 0); 802 mutex_unlock(&adev->srbm_mutex); 803 804 return 0; 805 } 806 807 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 808 enum admgpu_mes_pipe pipe) 809 { 810 int r; 811 u32 *eop; 812 813 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 814 AMDGPU_GEM_DOMAIN_GTT, 815 &adev->mes.eop_gpu_obj[pipe], 816 &adev->mes.eop_gpu_addr[pipe], 817 (void **)&eop); 818 if (r) { 819 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 820 return r; 821 } 822 823 memset(eop, 0, 824 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 825 826 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 827 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 828 829 return 0; 830 } 831 832 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 833 { 834 struct v11_compute_mqd *mqd = ring->mqd_ptr; 835 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 836 uint32_t tmp; 837 838 memset(mqd, 0, sizeof(*mqd)); 839 840 mqd->header = 0xC0310800; 841 mqd->compute_pipelinestat_enable = 0x00000001; 842 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 843 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 844 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 845 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 846 mqd->compute_misc_reserved = 0x00000007; 847 848 eop_base_addr = ring->eop_gpu_addr >> 8; 849 850 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 851 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 852 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 853 (order_base_2(MES_EOP_SIZE / 4) - 1)); 854 855 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 856 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 857 mqd->cp_hqd_eop_control = tmp; 858 859 /* disable the queue if it's active */ 860 ring->wptr = 0; 861 mqd->cp_hqd_pq_rptr = 0; 862 mqd->cp_hqd_pq_wptr_lo = 0; 863 mqd->cp_hqd_pq_wptr_hi = 0; 864 865 /* set the pointer to the MQD */ 866 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 867 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 868 869 /* set MQD vmid to 0 */ 870 tmp = regCP_MQD_CONTROL_DEFAULT; 871 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 872 mqd->cp_mqd_control = tmp; 873 874 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 875 hqd_gpu_addr = ring->gpu_addr >> 8; 876 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 877 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 878 879 /* set the wb address whether it's enabled or not */ 880 wb_gpu_addr = ring->rptr_gpu_addr; 881 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 882 mqd->cp_hqd_pq_rptr_report_addr_hi = 883 upper_32_bits(wb_gpu_addr) & 0xffff; 884 885 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 886 wb_gpu_addr = ring->wptr_gpu_addr; 887 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 888 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 889 890 /* set up the HQD, this is similar to CP_RB0_CNTL */ 891 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 892 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 893 (order_base_2(ring->ring_size / 4) - 1)); 894 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 895 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 896 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 897 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 898 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 899 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 900 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 901 mqd->cp_hqd_pq_control = tmp; 902 903 /* enable doorbell */ 904 tmp = 0; 905 if (ring->use_doorbell) { 906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 907 DOORBELL_OFFSET, ring->doorbell_index); 908 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 909 DOORBELL_EN, 1); 910 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 911 DOORBELL_SOURCE, 0); 912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 913 DOORBELL_HIT, 0); 914 } else 915 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 916 DOORBELL_EN, 0); 917 mqd->cp_hqd_pq_doorbell_control = tmp; 918 919 mqd->cp_hqd_vmid = 0; 920 /* activate the queue */ 921 mqd->cp_hqd_active = 1; 922 923 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 924 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 925 PRELOAD_SIZE, 0x55); 926 mqd->cp_hqd_persistent_state = tmp; 927 928 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 929 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 930 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 931 932 amdgpu_device_flush_hdp(ring->adev, NULL); 933 return 0; 934 } 935 936 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 937 { 938 struct v11_compute_mqd *mqd = ring->mqd_ptr; 939 struct amdgpu_device *adev = ring->adev; 940 uint32_t data = 0; 941 942 mutex_lock(&adev->srbm_mutex); 943 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 944 945 /* set CP_HQD_VMID.VMID = 0. */ 946 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 947 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 948 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 949 950 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 951 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 952 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 953 DOORBELL_EN, 0); 954 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 955 956 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 957 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 958 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 959 960 /* set CP_MQD_CONTROL.VMID=0 */ 961 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 962 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 963 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 964 965 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 966 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 967 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 968 969 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 970 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 971 mqd->cp_hqd_pq_rptr_report_addr_lo); 972 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 973 mqd->cp_hqd_pq_rptr_report_addr_hi); 974 975 /* set CP_HQD_PQ_CONTROL */ 976 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 977 978 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 979 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 980 mqd->cp_hqd_pq_wptr_poll_addr_lo); 981 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 982 mqd->cp_hqd_pq_wptr_poll_addr_hi); 983 984 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 985 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 986 mqd->cp_hqd_pq_doorbell_control); 987 988 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 989 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 990 991 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 992 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 993 994 soc21_grbm_select(adev, 0, 0, 0, 0); 995 mutex_unlock(&adev->srbm_mutex); 996 } 997 998 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 999 { 1000 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1001 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1002 int r; 1003 1004 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1005 return -EINVAL; 1006 1007 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1008 if (r) { 1009 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1010 return r; 1011 } 1012 1013 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 1014 1015 return amdgpu_ring_test_helper(kiq_ring); 1016 } 1017 1018 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1019 enum admgpu_mes_pipe pipe) 1020 { 1021 struct amdgpu_ring *ring; 1022 int r; 1023 1024 if (pipe == AMDGPU_MES_KIQ_PIPE) 1025 ring = &adev->gfx.kiq[0].ring; 1026 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1027 ring = &adev->mes.ring; 1028 else 1029 BUG(); 1030 1031 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1032 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1033 *(ring->wptr_cpu_addr) = 0; 1034 *(ring->rptr_cpu_addr) = 0; 1035 amdgpu_ring_clear_ring(ring); 1036 } 1037 1038 r = mes_v11_0_mqd_init(ring); 1039 if (r) 1040 return r; 1041 1042 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1043 r = mes_v11_0_kiq_enable_queue(adev); 1044 if (r) 1045 return r; 1046 } else { 1047 mes_v11_0_queue_init_register(ring); 1048 } 1049 1050 /* get MES scheduler/KIQ versions */ 1051 mutex_lock(&adev->srbm_mutex); 1052 soc21_grbm_select(adev, 3, pipe, 0, 0); 1053 1054 if (pipe == AMDGPU_MES_SCHED_PIPE) 1055 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1056 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1057 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1058 1059 soc21_grbm_select(adev, 0, 0, 0, 0); 1060 mutex_unlock(&adev->srbm_mutex); 1061 1062 return 0; 1063 } 1064 1065 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1066 { 1067 struct amdgpu_ring *ring; 1068 1069 ring = &adev->mes.ring; 1070 1071 ring->funcs = &mes_v11_0_ring_funcs; 1072 1073 ring->me = 3; 1074 ring->pipe = 0; 1075 ring->queue = 0; 1076 1077 ring->ring_obj = NULL; 1078 ring->use_doorbell = true; 1079 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1080 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1081 ring->no_scheduler = true; 1082 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1083 1084 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1085 AMDGPU_RING_PRIO_DEFAULT, NULL); 1086 } 1087 1088 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1089 { 1090 struct amdgpu_ring *ring; 1091 1092 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1093 1094 ring = &adev->gfx.kiq[0].ring; 1095 1096 ring->me = 3; 1097 ring->pipe = 1; 1098 ring->queue = 0; 1099 1100 ring->adev = NULL; 1101 ring->ring_obj = NULL; 1102 ring->use_doorbell = true; 1103 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1104 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1105 ring->no_scheduler = true; 1106 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1107 ring->me, ring->pipe, ring->queue); 1108 1109 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1110 AMDGPU_RING_PRIO_DEFAULT, NULL); 1111 } 1112 1113 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1114 enum admgpu_mes_pipe pipe) 1115 { 1116 int r, mqd_size = sizeof(struct v11_compute_mqd); 1117 struct amdgpu_ring *ring; 1118 1119 if (pipe == AMDGPU_MES_KIQ_PIPE) 1120 ring = &adev->gfx.kiq[0].ring; 1121 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1122 ring = &adev->mes.ring; 1123 else 1124 BUG(); 1125 1126 if (ring->mqd_obj) 1127 return 0; 1128 1129 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1130 AMDGPU_GEM_DOMAIN_VRAM | 1131 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1132 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1133 if (r) { 1134 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1135 return r; 1136 } 1137 1138 memset(ring->mqd_ptr, 0, mqd_size); 1139 1140 /* prepare MQD backup */ 1141 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1142 if (!adev->mes.mqd_backup[pipe]) { 1143 dev_warn(adev->dev, 1144 "no memory to create MQD backup for ring %s\n", 1145 ring->name); 1146 return -ENOMEM; 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int mes_v11_0_sw_init(void *handle) 1153 { 1154 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1155 int pipe, r; 1156 1157 adev->mes.funcs = &mes_v11_0_funcs; 1158 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1159 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1160 1161 r = amdgpu_mes_init(adev); 1162 if (r) 1163 return r; 1164 1165 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1166 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1167 continue; 1168 1169 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1170 if (r) 1171 return r; 1172 1173 r = mes_v11_0_mqd_sw_init(adev, pipe); 1174 if (r) 1175 return r; 1176 } 1177 1178 if (adev->enable_mes_kiq) { 1179 r = mes_v11_0_kiq_ring_init(adev); 1180 if (r) 1181 return r; 1182 } 1183 1184 r = mes_v11_0_ring_init(adev); 1185 if (r) 1186 return r; 1187 1188 return 0; 1189 } 1190 1191 static int mes_v11_0_sw_fini(void *handle) 1192 { 1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1194 int pipe; 1195 1196 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1197 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1198 1199 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1200 kfree(adev->mes.mqd_backup[pipe]); 1201 1202 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1203 &adev->mes.eop_gpu_addr[pipe], 1204 NULL); 1205 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1206 } 1207 1208 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1209 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1210 &adev->gfx.kiq[0].ring.mqd_ptr); 1211 1212 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1213 &adev->mes.ring.mqd_gpu_addr, 1214 &adev->mes.ring.mqd_ptr); 1215 1216 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1217 amdgpu_ring_fini(&adev->mes.ring); 1218 1219 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1220 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1221 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1222 } 1223 1224 amdgpu_mes_fini(adev); 1225 return 0; 1226 } 1227 1228 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1229 { 1230 uint32_t data; 1231 int i; 1232 struct amdgpu_device *adev = ring->adev; 1233 1234 mutex_lock(&adev->srbm_mutex); 1235 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1236 1237 /* disable the queue if it's active */ 1238 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1239 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1240 for (i = 0; i < adev->usec_timeout; i++) { 1241 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1242 break; 1243 udelay(1); 1244 } 1245 } 1246 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1247 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1248 DOORBELL_EN, 0); 1249 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1250 DOORBELL_HIT, 1); 1251 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1252 1253 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1254 1255 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1256 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1257 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1258 1259 soc21_grbm_select(adev, 0, 0, 0, 0); 1260 mutex_unlock(&adev->srbm_mutex); 1261 } 1262 1263 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1264 { 1265 uint32_t tmp; 1266 struct amdgpu_device *adev = ring->adev; 1267 1268 /* tell RLC which is KIQ queue */ 1269 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1270 tmp &= 0xffffff00; 1271 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1272 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1273 tmp |= 0x80; 1274 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1275 } 1276 1277 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1278 { 1279 uint32_t tmp; 1280 1281 /* tell RLC which is KIQ dequeue */ 1282 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1283 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1284 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1285 } 1286 1287 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1288 { 1289 int r = 0; 1290 1291 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1292 1293 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1294 if (r) { 1295 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1296 return r; 1297 } 1298 1299 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1300 if (r) { 1301 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1302 return r; 1303 } 1304 1305 } 1306 1307 mes_v11_0_enable(adev, true); 1308 1309 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1310 1311 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1312 if (r) 1313 goto failure; 1314 1315 r = mes_v11_0_hw_init(adev); 1316 if (r) 1317 goto failure; 1318 1319 return r; 1320 1321 failure: 1322 mes_v11_0_hw_fini(adev); 1323 return r; 1324 } 1325 1326 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1327 { 1328 if (adev->mes.ring.sched.ready) { 1329 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1330 adev->mes.ring.sched.ready = false; 1331 } 1332 1333 if (amdgpu_sriov_vf(adev)) { 1334 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1335 mes_v11_0_kiq_clear(adev); 1336 } 1337 1338 mes_v11_0_enable(adev, false); 1339 1340 return 0; 1341 } 1342 1343 static int mes_v11_0_hw_init(void *handle) 1344 { 1345 int r; 1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347 1348 if (adev->mes.ring.sched.ready) 1349 goto out; 1350 1351 if (!adev->enable_mes_kiq) { 1352 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1353 r = mes_v11_0_load_microcode(adev, 1354 AMDGPU_MES_SCHED_PIPE, true); 1355 if (r) { 1356 DRM_ERROR("failed to MES fw, r=%d\n", r); 1357 return r; 1358 } 1359 } 1360 1361 mes_v11_0_enable(adev, true); 1362 } 1363 1364 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1365 if (r) 1366 goto failure; 1367 1368 r = mes_v11_0_set_hw_resources(&adev->mes); 1369 if (r) 1370 goto failure; 1371 1372 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1373 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1374 if (r) { 1375 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1376 goto failure; 1377 } 1378 } 1379 1380 r = mes_v11_0_query_sched_status(&adev->mes); 1381 if (r) { 1382 DRM_ERROR("MES is busy\n"); 1383 goto failure; 1384 } 1385 1386 out: 1387 /* 1388 * Disable KIQ ring usage from the driver once MES is enabled. 1389 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1390 * with MES enabled. 1391 */ 1392 adev->gfx.kiq[0].ring.sched.ready = false; 1393 adev->mes.ring.sched.ready = true; 1394 1395 return 0; 1396 1397 failure: 1398 mes_v11_0_hw_fini(adev); 1399 return r; 1400 } 1401 1402 static int mes_v11_0_hw_fini(void *handle) 1403 { 1404 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1405 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1406 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1407 &adev->mes.resource_1_addr); 1408 } 1409 return 0; 1410 } 1411 1412 static int mes_v11_0_suspend(void *handle) 1413 { 1414 int r; 1415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1416 1417 r = amdgpu_mes_suspend(adev); 1418 if (r) 1419 return r; 1420 1421 return mes_v11_0_hw_fini(adev); 1422 } 1423 1424 static int mes_v11_0_resume(void *handle) 1425 { 1426 int r; 1427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1428 1429 r = mes_v11_0_hw_init(adev); 1430 if (r) 1431 return r; 1432 1433 return amdgpu_mes_resume(adev); 1434 } 1435 1436 static int mes_v11_0_early_init(void *handle) 1437 { 1438 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1439 int pipe, r; 1440 1441 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1442 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1443 continue; 1444 r = amdgpu_mes_init_microcode(adev, pipe); 1445 if (r) 1446 return r; 1447 } 1448 1449 return 0; 1450 } 1451 1452 static int mes_v11_0_late_init(void *handle) 1453 { 1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1455 1456 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1457 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1458 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1459 amdgpu_mes_self_test(adev); 1460 1461 return 0; 1462 } 1463 1464 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1465 .name = "mes_v11_0", 1466 .early_init = mes_v11_0_early_init, 1467 .late_init = mes_v11_0_late_init, 1468 .sw_init = mes_v11_0_sw_init, 1469 .sw_fini = mes_v11_0_sw_fini, 1470 .hw_init = mes_v11_0_hw_init, 1471 .hw_fini = mes_v11_0_hw_fini, 1472 .suspend = mes_v11_0_suspend, 1473 .resume = mes_v11_0_resume, 1474 .dump_ip_state = NULL, 1475 .print_ip_state = NULL, 1476 }; 1477 1478 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1479 .type = AMD_IP_BLOCK_TYPE_MES, 1480 .major = 11, 1481 .minor = 0, 1482 .rev = 0, 1483 .funcs = &mes_v11_0_ip_funcs, 1484 }; 1485