1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 45 46 static int mes_v11_0_hw_fini(void *handle); 47 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 48 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 49 50 #define MES_EOP_SIZE 2048 51 52 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 53 { 54 struct amdgpu_device *adev = ring->adev; 55 56 if (ring->use_doorbell) { 57 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 58 ring->wptr); 59 WDOORBELL64(ring->doorbell_index, ring->wptr); 60 } else { 61 BUG(); 62 } 63 } 64 65 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 66 { 67 return *ring->rptr_cpu_addr; 68 } 69 70 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 71 { 72 u64 wptr; 73 74 if (ring->use_doorbell) 75 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 76 else 77 BUG(); 78 return wptr; 79 } 80 81 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 82 .type = AMDGPU_RING_TYPE_MES, 83 .align_mask = 1, 84 .nop = 0, 85 .support_64bit_ptrs = true, 86 .get_rptr = mes_v11_0_ring_get_rptr, 87 .get_wptr = mes_v11_0_ring_get_wptr, 88 .set_wptr = mes_v11_0_ring_set_wptr, 89 .insert_nop = amdgpu_ring_insert_nop, 90 }; 91 92 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 93 void *pkt, int size, 94 int api_status_off) 95 { 96 int ndw = size / 4; 97 signed long r; 98 union MESAPI__ADD_QUEUE *x_pkt = pkt; 99 struct MES_API_STATUS *api_status; 100 struct amdgpu_device *adev = mes->adev; 101 struct amdgpu_ring *ring = &mes->ring; 102 unsigned long flags; 103 signed long timeout = adev->usec_timeout; 104 105 if (amdgpu_emu_mode) { 106 timeout *= 100; 107 } else if (amdgpu_sriov_vf(adev)) { 108 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 109 timeout = 15 * 600 * 1000; 110 } 111 BUG_ON(size % 4 != 0); 112 113 spin_lock_irqsave(&mes->ring_lock, flags); 114 if (amdgpu_ring_alloc(ring, ndw)) { 115 spin_unlock_irqrestore(&mes->ring_lock, flags); 116 return -ENOMEM; 117 } 118 119 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 120 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 121 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 122 123 amdgpu_ring_write_multiple(ring, pkt, ndw); 124 amdgpu_ring_commit(ring); 125 spin_unlock_irqrestore(&mes->ring_lock, flags); 126 127 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 128 129 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 130 timeout); 131 if (r < 1) { 132 DRM_ERROR("MES failed to response msg=%d\n", 133 x_pkt->header.opcode); 134 135 while (halt_if_hws_hang) 136 schedule(); 137 138 return -ETIMEDOUT; 139 } 140 141 return 0; 142 } 143 144 static int convert_to_mes_queue_type(int queue_type) 145 { 146 if (queue_type == AMDGPU_RING_TYPE_GFX) 147 return MES_QUEUE_TYPE_GFX; 148 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 149 return MES_QUEUE_TYPE_COMPUTE; 150 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 151 return MES_QUEUE_TYPE_SDMA; 152 else 153 BUG(); 154 return -1; 155 } 156 157 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 158 struct mes_add_queue_input *input) 159 { 160 struct amdgpu_device *adev = mes->adev; 161 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 162 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 163 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 164 165 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 166 167 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 168 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 169 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 170 171 mes_add_queue_pkt.process_id = input->process_id; 172 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 173 mes_add_queue_pkt.process_va_start = input->process_va_start; 174 mes_add_queue_pkt.process_va_end = input->process_va_end; 175 mes_add_queue_pkt.process_quantum = input->process_quantum; 176 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 177 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 178 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 179 mes_add_queue_pkt.inprocess_gang_priority = 180 input->inprocess_gang_priority; 181 mes_add_queue_pkt.gang_global_priority_level = 182 input->gang_global_priority_level; 183 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 184 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 185 186 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 187 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 188 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 189 else 190 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 191 192 mes_add_queue_pkt.queue_type = 193 convert_to_mes_queue_type(input->queue_type); 194 mes_add_queue_pkt.paging = input->paging; 195 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 196 mes_add_queue_pkt.gws_base = input->gws_base; 197 mes_add_queue_pkt.gws_size = input->gws_size; 198 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 199 mes_add_queue_pkt.tma_addr = input->tma_addr; 200 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 201 202 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 203 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 204 mes_add_queue_pkt.gds_size = input->queue_size; 205 206 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 207 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 208 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 209 mes_add_queue_pkt.trap_en = 1; 210 211 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 212 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 213 mes_add_queue_pkt.gds_size = input->queue_size; 214 215 return mes_v11_0_submit_pkt_and_poll_completion(mes, 216 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 217 offsetof(union MESAPI__ADD_QUEUE, api_status)); 218 } 219 220 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 221 struct mes_remove_queue_input *input) 222 { 223 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 224 225 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 226 227 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 228 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 229 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 230 231 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 232 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 233 234 return mes_v11_0_submit_pkt_and_poll_completion(mes, 235 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 236 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 237 } 238 239 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 240 struct mes_unmap_legacy_queue_input *input) 241 { 242 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 243 244 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 245 246 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 247 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 248 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 249 250 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 251 mes_remove_queue_pkt.gang_context_addr = 0; 252 253 mes_remove_queue_pkt.pipe_id = input->pipe_id; 254 mes_remove_queue_pkt.queue_id = input->queue_id; 255 256 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 257 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 258 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 259 mes_remove_queue_pkt.tf_data = 260 lower_32_bits(input->trail_fence_data); 261 } else { 262 mes_remove_queue_pkt.unmap_legacy_queue = 1; 263 mes_remove_queue_pkt.queue_type = 264 convert_to_mes_queue_type(input->queue_type); 265 } 266 267 return mes_v11_0_submit_pkt_and_poll_completion(mes, 268 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 269 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 270 } 271 272 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 273 struct mes_suspend_gang_input *input) 274 { 275 return 0; 276 } 277 278 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 279 struct mes_resume_gang_input *input) 280 { 281 return 0; 282 } 283 284 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 285 { 286 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 287 288 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 289 290 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 291 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 292 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 293 294 return mes_v11_0_submit_pkt_and_poll_completion(mes, 295 &mes_status_pkt, sizeof(mes_status_pkt), 296 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 297 } 298 299 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 300 struct mes_misc_op_input *input) 301 { 302 union MESAPI__MISC misc_pkt; 303 304 memset(&misc_pkt, 0, sizeof(misc_pkt)); 305 306 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 307 misc_pkt.header.opcode = MES_SCH_API_MISC; 308 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 309 310 switch (input->op) { 311 case MES_MISC_OP_READ_REG: 312 misc_pkt.opcode = MESAPI_MISC__READ_REG; 313 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 314 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 315 break; 316 case MES_MISC_OP_WRITE_REG: 317 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 318 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 319 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 320 break; 321 case MES_MISC_OP_WRM_REG_WAIT: 322 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 323 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 324 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 325 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 326 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 327 misc_pkt.wait_reg_mem.reg_offset2 = 0; 328 break; 329 case MES_MISC_OP_WRM_REG_WR_WAIT: 330 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 331 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 332 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 333 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 334 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 335 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 336 break; 337 default: 338 DRM_ERROR("unsupported misc op (%d) \n", input->op); 339 return -EINVAL; 340 } 341 342 return mes_v11_0_submit_pkt_and_poll_completion(mes, 343 &misc_pkt, sizeof(misc_pkt), 344 offsetof(union MESAPI__MISC, api_status)); 345 } 346 347 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 348 { 349 int i; 350 struct amdgpu_device *adev = mes->adev; 351 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 352 353 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 354 355 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 356 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 357 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 358 359 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 360 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 361 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 362 mes_set_hw_res_pkt.paging_vmid = 0; 363 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 364 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 365 mes->query_status_fence_gpu_addr; 366 367 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 368 mes_set_hw_res_pkt.compute_hqd_mask[i] = 369 mes->compute_hqd_mask[i]; 370 371 for (i = 0; i < MAX_GFX_PIPES; i++) 372 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 373 374 for (i = 0; i < MAX_SDMA_PIPES; i++) 375 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 376 377 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 378 mes_set_hw_res_pkt.aggregated_doorbells[i] = 379 mes->aggregated_doorbells[i]; 380 381 for (i = 0; i < 5; i++) { 382 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 383 mes_set_hw_res_pkt.mmhub_base[i] = 384 adev->reg_offset[MMHUB_HWIP][0][i]; 385 mes_set_hw_res_pkt.osssys_base[i] = 386 adev->reg_offset[OSSSYS_HWIP][0][i]; 387 } 388 389 mes_set_hw_res_pkt.disable_reset = 1; 390 mes_set_hw_res_pkt.disable_mes_log = 1; 391 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 392 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 393 mes_set_hw_res_pkt.oversubscription_timer = 50; 394 395 return mes_v11_0_submit_pkt_and_poll_completion(mes, 396 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 397 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 398 } 399 400 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 401 { 402 struct amdgpu_device *adev = mes->adev; 403 uint32_t data; 404 405 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 406 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 407 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 408 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 409 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 410 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 411 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 412 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 413 414 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 415 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 416 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 417 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 418 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 419 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 420 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 421 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 422 423 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 424 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 425 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 426 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 427 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 428 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 429 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 430 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 431 432 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 433 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 434 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 435 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 436 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 437 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 438 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 439 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 440 441 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 442 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 443 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 444 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 445 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 446 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 447 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 448 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 449 450 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 451 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 452 } 453 454 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 455 .add_hw_queue = mes_v11_0_add_hw_queue, 456 .remove_hw_queue = mes_v11_0_remove_hw_queue, 457 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 458 .suspend_gang = mes_v11_0_suspend_gang, 459 .resume_gang = mes_v11_0_resume_gang, 460 .misc_op = mes_v11_0_misc_op, 461 }; 462 463 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 464 enum admgpu_mes_pipe pipe) 465 { 466 char fw_name[30]; 467 char ucode_prefix[30]; 468 int err; 469 const struct mes_firmware_header_v1_0 *mes_hdr; 470 struct amdgpu_firmware_info *info; 471 472 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 473 474 if (pipe == AMDGPU_MES_SCHED_PIPE) 475 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 476 ucode_prefix); 477 else 478 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 479 ucode_prefix); 480 481 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 482 if (err) 483 return err; 484 485 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 486 if (err) { 487 release_firmware(adev->mes.fw[pipe]); 488 adev->mes.fw[pipe] = NULL; 489 return err; 490 } 491 492 mes_hdr = (const struct mes_firmware_header_v1_0 *) 493 adev->mes.fw[pipe]->data; 494 adev->mes.uc_start_addr[pipe] = 495 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 496 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 497 adev->mes.data_start_addr[pipe] = 498 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 499 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 500 501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 502 int ucode, ucode_data; 503 504 if (pipe == AMDGPU_MES_SCHED_PIPE) { 505 ucode = AMDGPU_UCODE_ID_CP_MES; 506 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 507 } else { 508 ucode = AMDGPU_UCODE_ID_CP_MES1; 509 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 510 } 511 512 info = &adev->firmware.ucode[ucode]; 513 info->ucode_id = ucode; 514 info->fw = adev->mes.fw[pipe]; 515 adev->firmware.fw_size += 516 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 517 PAGE_SIZE); 518 519 info = &adev->firmware.ucode[ucode_data]; 520 info->ucode_id = ucode_data; 521 info->fw = adev->mes.fw[pipe]; 522 adev->firmware.fw_size += 523 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 524 PAGE_SIZE); 525 } 526 527 return 0; 528 } 529 530 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 531 enum admgpu_mes_pipe pipe) 532 { 533 release_firmware(adev->mes.fw[pipe]); 534 adev->mes.fw[pipe] = NULL; 535 } 536 537 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 538 enum admgpu_mes_pipe pipe) 539 { 540 int r; 541 const struct mes_firmware_header_v1_0 *mes_hdr; 542 const __le32 *fw_data; 543 unsigned fw_size; 544 545 mes_hdr = (const struct mes_firmware_header_v1_0 *) 546 adev->mes.fw[pipe]->data; 547 548 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 549 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 550 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 551 552 r = amdgpu_bo_create_reserved(adev, fw_size, 553 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 554 &adev->mes.ucode_fw_obj[pipe], 555 &adev->mes.ucode_fw_gpu_addr[pipe], 556 (void **)&adev->mes.ucode_fw_ptr[pipe]); 557 if (r) { 558 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 559 return r; 560 } 561 562 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 563 564 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 565 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 566 567 return 0; 568 } 569 570 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 571 enum admgpu_mes_pipe pipe) 572 { 573 int r; 574 const struct mes_firmware_header_v1_0 *mes_hdr; 575 const __le32 *fw_data; 576 unsigned fw_size; 577 578 mes_hdr = (const struct mes_firmware_header_v1_0 *) 579 adev->mes.fw[pipe]->data; 580 581 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 582 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 583 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 584 585 r = amdgpu_bo_create_reserved(adev, fw_size, 586 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 587 &adev->mes.data_fw_obj[pipe], 588 &adev->mes.data_fw_gpu_addr[pipe], 589 (void **)&adev->mes.data_fw_ptr[pipe]); 590 if (r) { 591 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 592 return r; 593 } 594 595 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 596 597 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 598 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 599 600 return 0; 601 } 602 603 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 604 enum admgpu_mes_pipe pipe) 605 { 606 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 607 &adev->mes.data_fw_gpu_addr[pipe], 608 (void **)&adev->mes.data_fw_ptr[pipe]); 609 610 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 611 &adev->mes.ucode_fw_gpu_addr[pipe], 612 (void **)&adev->mes.ucode_fw_ptr[pipe]); 613 } 614 615 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 616 { 617 uint64_t ucode_addr; 618 uint32_t pipe, data = 0; 619 620 if (enable) { 621 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 622 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 623 data = REG_SET_FIELD(data, CP_MES_CNTL, 624 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 625 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 626 627 mutex_lock(&adev->srbm_mutex); 628 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 629 if (!adev->enable_mes_kiq && 630 pipe == AMDGPU_MES_KIQ_PIPE) 631 continue; 632 633 soc21_grbm_select(adev, 3, pipe, 0, 0); 634 635 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 636 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 637 lower_32_bits(ucode_addr)); 638 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 639 upper_32_bits(ucode_addr)); 640 } 641 soc21_grbm_select(adev, 0, 0, 0, 0); 642 mutex_unlock(&adev->srbm_mutex); 643 644 /* unhalt MES and activate pipe0 */ 645 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 646 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 647 adev->enable_mes_kiq ? 1 : 0); 648 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 649 650 if (amdgpu_emu_mode) 651 msleep(100); 652 else 653 udelay(50); 654 } else { 655 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 656 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 657 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 658 data = REG_SET_FIELD(data, CP_MES_CNTL, 659 MES_INVALIDATE_ICACHE, 1); 660 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 661 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 662 adev->enable_mes_kiq ? 1 : 0); 663 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 664 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 665 } 666 } 667 668 /* This function is for backdoor MES firmware */ 669 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 670 enum admgpu_mes_pipe pipe, bool prime_icache) 671 { 672 int r; 673 uint32_t data; 674 uint64_t ucode_addr; 675 676 mes_v11_0_enable(adev, false); 677 678 if (!adev->mes.fw[pipe]) 679 return -EINVAL; 680 681 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 682 if (r) 683 return r; 684 685 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 686 if (r) { 687 mes_v11_0_free_ucode_buffers(adev, pipe); 688 return r; 689 } 690 691 mutex_lock(&adev->srbm_mutex); 692 /* me=3, pipe=0, queue=0 */ 693 soc21_grbm_select(adev, 3, pipe, 0, 0); 694 695 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 696 697 /* set ucode start address */ 698 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 699 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 700 lower_32_bits(ucode_addr)); 701 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 702 upper_32_bits(ucode_addr)); 703 704 /* set ucode fimrware address */ 705 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 706 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 707 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 708 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 709 710 /* set ucode instruction cache boundary to 2M-1 */ 711 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 712 713 /* set ucode data firmware address */ 714 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 715 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 716 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 717 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 718 719 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 720 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 721 722 if (prime_icache) { 723 /* invalidate ICACHE */ 724 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 725 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 726 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 727 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 728 729 /* prime the ICACHE. */ 730 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 731 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 732 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 733 } 734 735 soc21_grbm_select(adev, 0, 0, 0, 0); 736 mutex_unlock(&adev->srbm_mutex); 737 738 return 0; 739 } 740 741 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 742 enum admgpu_mes_pipe pipe) 743 { 744 int r; 745 u32 *eop; 746 747 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 748 AMDGPU_GEM_DOMAIN_GTT, 749 &adev->mes.eop_gpu_obj[pipe], 750 &adev->mes.eop_gpu_addr[pipe], 751 (void **)&eop); 752 if (r) { 753 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 754 return r; 755 } 756 757 memset(eop, 0, 758 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 759 760 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 761 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 762 763 return 0; 764 } 765 766 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 767 { 768 struct v11_compute_mqd *mqd = ring->mqd_ptr; 769 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 770 uint32_t tmp; 771 772 mqd->header = 0xC0310800; 773 mqd->compute_pipelinestat_enable = 0x00000001; 774 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 775 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 776 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 777 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 778 mqd->compute_misc_reserved = 0x00000007; 779 780 eop_base_addr = ring->eop_gpu_addr >> 8; 781 782 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 783 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 784 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 785 (order_base_2(MES_EOP_SIZE / 4) - 1)); 786 787 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 788 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 789 mqd->cp_hqd_eop_control = tmp; 790 791 /* disable the queue if it's active */ 792 ring->wptr = 0; 793 mqd->cp_hqd_pq_rptr = 0; 794 mqd->cp_hqd_pq_wptr_lo = 0; 795 mqd->cp_hqd_pq_wptr_hi = 0; 796 797 /* set the pointer to the MQD */ 798 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 799 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 800 801 /* set MQD vmid to 0 */ 802 tmp = regCP_MQD_CONTROL_DEFAULT; 803 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 804 mqd->cp_mqd_control = tmp; 805 806 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 807 hqd_gpu_addr = ring->gpu_addr >> 8; 808 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 809 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 810 811 /* set the wb address whether it's enabled or not */ 812 wb_gpu_addr = ring->rptr_gpu_addr; 813 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 814 mqd->cp_hqd_pq_rptr_report_addr_hi = 815 upper_32_bits(wb_gpu_addr) & 0xffff; 816 817 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 818 wb_gpu_addr = ring->wptr_gpu_addr; 819 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 820 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 821 822 /* set up the HQD, this is similar to CP_RB0_CNTL */ 823 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 825 (order_base_2(ring->ring_size / 4) - 1)); 826 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 827 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 833 mqd->cp_hqd_pq_control = tmp; 834 835 /* enable doorbell */ 836 tmp = 0; 837 if (ring->use_doorbell) { 838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 839 DOORBELL_OFFSET, ring->doorbell_index); 840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 841 DOORBELL_EN, 1); 842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 843 DOORBELL_SOURCE, 0); 844 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 845 DOORBELL_HIT, 0); 846 } 847 else 848 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 849 DOORBELL_EN, 0); 850 mqd->cp_hqd_pq_doorbell_control = tmp; 851 852 mqd->cp_hqd_vmid = 0; 853 /* activate the queue */ 854 mqd->cp_hqd_active = 1; 855 856 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 857 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 858 PRELOAD_SIZE, 0x55); 859 mqd->cp_hqd_persistent_state = tmp; 860 861 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 862 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 863 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 864 865 return 0; 866 } 867 868 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 869 { 870 struct v11_compute_mqd *mqd = ring->mqd_ptr; 871 struct amdgpu_device *adev = ring->adev; 872 uint32_t data = 0; 873 874 mutex_lock(&adev->srbm_mutex); 875 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 876 877 /* set CP_HQD_VMID.VMID = 0. */ 878 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 879 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 880 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 881 882 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 883 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 884 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 885 DOORBELL_EN, 0); 886 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 887 888 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 889 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 890 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 891 892 /* set CP_MQD_CONTROL.VMID=0 */ 893 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 894 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 895 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 896 897 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 898 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 899 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 900 901 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 902 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 903 mqd->cp_hqd_pq_rptr_report_addr_lo); 904 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 905 mqd->cp_hqd_pq_rptr_report_addr_hi); 906 907 /* set CP_HQD_PQ_CONTROL */ 908 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 909 910 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 911 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 912 mqd->cp_hqd_pq_wptr_poll_addr_lo); 913 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 914 mqd->cp_hqd_pq_wptr_poll_addr_hi); 915 916 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 917 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 918 mqd->cp_hqd_pq_doorbell_control); 919 920 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 921 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 922 923 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 924 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 925 926 soc21_grbm_select(adev, 0, 0, 0, 0); 927 mutex_unlock(&adev->srbm_mutex); 928 } 929 930 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 931 { 932 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 933 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 934 int r; 935 936 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 937 return -EINVAL; 938 939 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 940 if (r) { 941 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 942 return r; 943 } 944 945 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 946 947 r = amdgpu_ring_test_ring(kiq_ring); 948 if (r) { 949 DRM_ERROR("kfq enable failed\n"); 950 kiq_ring->sched.ready = false; 951 } 952 return r; 953 } 954 955 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 956 enum admgpu_mes_pipe pipe) 957 { 958 struct amdgpu_ring *ring; 959 int r; 960 961 if (pipe == AMDGPU_MES_KIQ_PIPE) 962 ring = &adev->gfx.kiq.ring; 963 else if (pipe == AMDGPU_MES_SCHED_PIPE) 964 ring = &adev->mes.ring; 965 else 966 BUG(); 967 968 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 969 (amdgpu_in_reset(adev) || adev->in_suspend)) { 970 *(ring->wptr_cpu_addr) = 0; 971 *(ring->rptr_cpu_addr) = 0; 972 amdgpu_ring_clear_ring(ring); 973 } 974 975 r = mes_v11_0_mqd_init(ring); 976 if (r) 977 return r; 978 979 if (pipe == AMDGPU_MES_SCHED_PIPE) { 980 r = mes_v11_0_kiq_enable_queue(adev); 981 if (r) 982 return r; 983 } else { 984 mes_v11_0_queue_init_register(ring); 985 } 986 987 /* get MES scheduler/KIQ versions */ 988 mutex_lock(&adev->srbm_mutex); 989 soc21_grbm_select(adev, 3, pipe, 0, 0); 990 991 if (pipe == AMDGPU_MES_SCHED_PIPE) 992 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 993 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 994 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 995 996 soc21_grbm_select(adev, 0, 0, 0, 0); 997 mutex_unlock(&adev->srbm_mutex); 998 999 return 0; 1000 } 1001 1002 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1003 { 1004 struct amdgpu_ring *ring; 1005 1006 ring = &adev->mes.ring; 1007 1008 ring->funcs = &mes_v11_0_ring_funcs; 1009 1010 ring->me = 3; 1011 ring->pipe = 0; 1012 ring->queue = 0; 1013 1014 ring->ring_obj = NULL; 1015 ring->use_doorbell = true; 1016 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1017 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1018 ring->no_scheduler = true; 1019 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1020 1021 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1022 AMDGPU_RING_PRIO_DEFAULT, NULL); 1023 } 1024 1025 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1026 { 1027 struct amdgpu_ring *ring; 1028 1029 spin_lock_init(&adev->gfx.kiq.ring_lock); 1030 1031 ring = &adev->gfx.kiq.ring; 1032 1033 ring->me = 3; 1034 ring->pipe = 1; 1035 ring->queue = 0; 1036 1037 ring->adev = NULL; 1038 ring->ring_obj = NULL; 1039 ring->use_doorbell = true; 1040 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1041 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1042 ring->no_scheduler = true; 1043 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1044 ring->me, ring->pipe, ring->queue); 1045 1046 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1047 AMDGPU_RING_PRIO_DEFAULT, NULL); 1048 } 1049 1050 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1051 enum admgpu_mes_pipe pipe) 1052 { 1053 int r, mqd_size = sizeof(struct v11_compute_mqd); 1054 struct amdgpu_ring *ring; 1055 1056 if (pipe == AMDGPU_MES_KIQ_PIPE) 1057 ring = &adev->gfx.kiq.ring; 1058 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1059 ring = &adev->mes.ring; 1060 else 1061 BUG(); 1062 1063 if (ring->mqd_obj) 1064 return 0; 1065 1066 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1067 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1068 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1069 if (r) { 1070 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1071 return r; 1072 } 1073 1074 memset(ring->mqd_ptr, 0, mqd_size); 1075 1076 /* prepare MQD backup */ 1077 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1078 if (!adev->mes.mqd_backup[pipe]) 1079 dev_warn(adev->dev, 1080 "no memory to create MQD backup for ring %s\n", 1081 ring->name); 1082 1083 return 0; 1084 } 1085 1086 static int mes_v11_0_sw_init(void *handle) 1087 { 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1089 int pipe, r; 1090 1091 adev->mes.adev = adev; 1092 adev->mes.funcs = &mes_v11_0_funcs; 1093 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1094 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1095 1096 r = amdgpu_mes_init(adev); 1097 if (r) 1098 return r; 1099 1100 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1101 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1102 continue; 1103 1104 r = mes_v11_0_init_microcode(adev, pipe); 1105 if (r) 1106 return r; 1107 1108 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1109 if (r) 1110 return r; 1111 1112 r = mes_v11_0_mqd_sw_init(adev, pipe); 1113 if (r) 1114 return r; 1115 } 1116 1117 if (adev->enable_mes_kiq) { 1118 r = mes_v11_0_kiq_ring_init(adev); 1119 if (r) 1120 return r; 1121 } 1122 1123 r = mes_v11_0_ring_init(adev); 1124 if (r) 1125 return r; 1126 1127 return 0; 1128 } 1129 1130 static int mes_v11_0_sw_fini(void *handle) 1131 { 1132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1133 int pipe; 1134 1135 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1136 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1137 1138 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1139 kfree(adev->mes.mqd_backup[pipe]); 1140 1141 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1142 &adev->mes.eop_gpu_addr[pipe], 1143 NULL); 1144 1145 mes_v11_0_free_microcode(adev, pipe); 1146 } 1147 1148 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1149 &adev->gfx.kiq.ring.mqd_gpu_addr, 1150 &adev->gfx.kiq.ring.mqd_ptr); 1151 1152 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1153 &adev->mes.ring.mqd_gpu_addr, 1154 &adev->mes.ring.mqd_ptr); 1155 1156 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1157 amdgpu_ring_fini(&adev->mes.ring); 1158 1159 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1160 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1161 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1162 } 1163 1164 amdgpu_mes_fini(adev); 1165 return 0; 1166 } 1167 1168 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1169 { 1170 uint32_t data; 1171 int i; 1172 1173 mutex_lock(&adev->srbm_mutex); 1174 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1175 1176 /* disable the queue if it's active */ 1177 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1178 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1179 for (i = 0; i < adev->usec_timeout; i++) { 1180 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1181 break; 1182 udelay(1); 1183 } 1184 } 1185 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1186 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1187 DOORBELL_EN, 0); 1188 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1189 DOORBELL_HIT, 1); 1190 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1191 1192 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1193 1194 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1195 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1196 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1197 1198 soc21_grbm_select(adev, 0, 0, 0, 0); 1199 mutex_unlock(&adev->srbm_mutex); 1200 1201 adev->mes.ring.sched.ready = false; 1202 } 1203 1204 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1205 { 1206 uint32_t tmp; 1207 struct amdgpu_device *adev = ring->adev; 1208 1209 /* tell RLC which is KIQ queue */ 1210 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1211 tmp &= 0xffffff00; 1212 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1213 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1214 tmp |= 0x80; 1215 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1216 } 1217 1218 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1219 { 1220 int r = 0; 1221 1222 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1223 1224 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1225 if (r) { 1226 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1227 return r; 1228 } 1229 1230 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1231 if (r) { 1232 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1233 return r; 1234 } 1235 1236 } 1237 1238 mes_v11_0_enable(adev, true); 1239 1240 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1241 1242 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1243 if (r) 1244 goto failure; 1245 1246 return r; 1247 1248 failure: 1249 mes_v11_0_hw_fini(adev); 1250 return r; 1251 } 1252 1253 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1254 { 1255 if (adev->mes.ring.sched.ready) 1256 mes_v11_0_kiq_dequeue_sched(adev); 1257 1258 if (!amdgpu_sriov_vf(adev)) 1259 mes_v11_0_enable(adev, false); 1260 1261 return 0; 1262 } 1263 1264 static int mes_v11_0_hw_init(void *handle) 1265 { 1266 int r; 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 1269 if (!adev->enable_mes_kiq) { 1270 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1271 r = mes_v11_0_load_microcode(adev, 1272 AMDGPU_MES_SCHED_PIPE, true); 1273 if (r) { 1274 DRM_ERROR("failed to MES fw, r=%d\n", r); 1275 return r; 1276 } 1277 } 1278 1279 mes_v11_0_enable(adev, true); 1280 } 1281 1282 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1283 if (r) 1284 goto failure; 1285 1286 r = mes_v11_0_set_hw_resources(&adev->mes); 1287 if (r) 1288 goto failure; 1289 1290 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1291 1292 r = mes_v11_0_query_sched_status(&adev->mes); 1293 if (r) { 1294 DRM_ERROR("MES is busy\n"); 1295 goto failure; 1296 } 1297 1298 /* 1299 * Disable KIQ ring usage from the driver once MES is enabled. 1300 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1301 * with MES enabled. 1302 */ 1303 adev->gfx.kiq.ring.sched.ready = false; 1304 adev->mes.ring.sched.ready = true; 1305 1306 return 0; 1307 1308 failure: 1309 mes_v11_0_hw_fini(adev); 1310 return r; 1311 } 1312 1313 static int mes_v11_0_hw_fini(void *handle) 1314 { 1315 return 0; 1316 } 1317 1318 static int mes_v11_0_suspend(void *handle) 1319 { 1320 int r; 1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1322 1323 r = amdgpu_mes_suspend(adev); 1324 if (r) 1325 return r; 1326 1327 return mes_v11_0_hw_fini(adev); 1328 } 1329 1330 static int mes_v11_0_resume(void *handle) 1331 { 1332 int r; 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1334 1335 r = mes_v11_0_hw_init(adev); 1336 if (r) 1337 return r; 1338 1339 return amdgpu_mes_resume(adev); 1340 } 1341 1342 static int mes_v11_0_late_init(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 1346 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1347 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && 1348 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1349 amdgpu_mes_self_test(adev); 1350 1351 return 0; 1352 } 1353 1354 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1355 .name = "mes_v11_0", 1356 .late_init = mes_v11_0_late_init, 1357 .sw_init = mes_v11_0_sw_init, 1358 .sw_fini = mes_v11_0_sw_fini, 1359 .hw_init = mes_v11_0_hw_init, 1360 .hw_fini = mes_v11_0_hw_fini, 1361 .suspend = mes_v11_0_suspend, 1362 .resume = mes_v11_0_resume, 1363 }; 1364 1365 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1366 .type = AMD_IP_BLOCK_TYPE_MES, 1367 .major = 11, 1368 .minor = 0, 1369 .rev = 0, 1370 .funcs = &mes_v11_0_ip_funcs, 1371 }; 1372