1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 56 57 static int mes_v11_0_hw_init(void *handle); 58 static int mes_v11_0_hw_fini(void *handle); 59 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 60 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 61 62 #define MES_EOP_SIZE 2048 63 #define GFX_MES_DRAM_SIZE 0x80000 64 65 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 66 { 67 struct amdgpu_device *adev = ring->adev; 68 69 if (ring->use_doorbell) { 70 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 71 ring->wptr); 72 WDOORBELL64(ring->doorbell_index, ring->wptr); 73 } else { 74 BUG(); 75 } 76 } 77 78 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 79 { 80 return *ring->rptr_cpu_addr; 81 } 82 83 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 84 { 85 u64 wptr; 86 87 if (ring->use_doorbell) 88 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 89 else 90 BUG(); 91 return wptr; 92 } 93 94 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 95 .type = AMDGPU_RING_TYPE_MES, 96 .align_mask = 1, 97 .nop = 0, 98 .support_64bit_ptrs = true, 99 .get_rptr = mes_v11_0_ring_get_rptr, 100 .get_wptr = mes_v11_0_ring_get_wptr, 101 .set_wptr = mes_v11_0_ring_set_wptr, 102 .insert_nop = amdgpu_ring_insert_nop, 103 }; 104 105 static const char *mes_v11_0_opcodes[] = { 106 "SET_HW_RSRC", 107 "SET_SCHEDULING_CONFIG", 108 "ADD_QUEUE", 109 "REMOVE_QUEUE", 110 "PERFORM_YIELD", 111 "SET_GANG_PRIORITY_LEVEL", 112 "SUSPEND", 113 "RESUME", 114 "RESET", 115 "SET_LOG_BUFFER", 116 "CHANGE_GANG_PRORITY", 117 "QUERY_SCHEDULER_STATUS", 118 "PROGRAM_GDS", 119 "SET_DEBUG_VMID", 120 "MISC", 121 "UPDATE_ROOT_PAGE_TABLE", 122 "AMD_LOG", 123 "unused", 124 "unused", 125 "SET_HW_RSRC_1", 126 }; 127 128 static const char *mes_v11_0_misc_opcodes[] = { 129 "WRITE_REG", 130 "INV_GART", 131 "QUERY_STATUS", 132 "READ_REG", 133 "WAIT_REG_MEM", 134 "SET_SHADER_DEBUGGER", 135 }; 136 137 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 138 { 139 const char *op_str = NULL; 140 141 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 142 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 143 144 return op_str; 145 } 146 147 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 148 { 149 const char *op_str = NULL; 150 151 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 152 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 153 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 154 155 return op_str; 156 } 157 158 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 159 void *pkt, int size, 160 int api_status_off) 161 { 162 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 163 signed long timeout = 3000000; /* 3000 ms */ 164 struct amdgpu_device *adev = mes->adev; 165 struct amdgpu_ring *ring = &mes->ring[0]; 166 struct MES_API_STATUS *api_status; 167 union MESAPI__MISC *x_pkt = pkt; 168 const char *op_str, *misc_op_str; 169 unsigned long flags; 170 u64 status_gpu_addr; 171 u32 seq, status_offset; 172 u64 *status_ptr; 173 signed long r; 174 int ret; 175 176 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 177 return -EINVAL; 178 179 if (amdgpu_emu_mode) { 180 timeout *= 100; 181 } else if (amdgpu_sriov_vf(adev)) { 182 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 183 timeout = 15 * 600 * 1000; 184 } 185 186 ret = amdgpu_device_wb_get(adev, &status_offset); 187 if (ret) 188 return ret; 189 190 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 191 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 192 *status_ptr = 0; 193 194 spin_lock_irqsave(&mes->ring_lock[0], flags); 195 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 196 if (r) 197 goto error_unlock_free; 198 199 seq = ++ring->fence_drv.sync_seq; 200 r = amdgpu_fence_wait_polling(ring, 201 seq - ring->fence_drv.num_fences_mask, 202 timeout); 203 if (r < 1) 204 goto error_undo; 205 206 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 207 api_status->api_completion_fence_addr = status_gpu_addr; 208 api_status->api_completion_fence_value = 1; 209 210 amdgpu_ring_write_multiple(ring, pkt, size / 4); 211 212 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 213 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 214 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 215 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 216 mes_status_pkt.api_status.api_completion_fence_addr = 217 ring->fence_drv.gpu_addr; 218 mes_status_pkt.api_status.api_completion_fence_value = seq; 219 220 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 221 sizeof(mes_status_pkt) / 4); 222 223 amdgpu_ring_commit(ring); 224 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 225 226 op_str = mes_v11_0_get_op_string(x_pkt); 227 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 228 229 if (misc_op_str) 230 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 231 misc_op_str); 232 else if (op_str) 233 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 234 else 235 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 236 x_pkt->header.opcode); 237 238 r = amdgpu_fence_wait_polling(ring, seq, timeout); 239 if (r < 1 || !*status_ptr) { 240 241 if (misc_op_str) 242 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 243 op_str, misc_op_str); 244 else if (op_str) 245 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 246 op_str); 247 else 248 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 249 x_pkt->header.opcode); 250 251 while (halt_if_hws_hang) 252 schedule(); 253 254 r = -ETIMEDOUT; 255 goto error_wb_free; 256 } 257 258 amdgpu_device_wb_free(adev, status_offset); 259 return 0; 260 261 error_undo: 262 dev_err(adev->dev, "MES ring buffer is full.\n"); 263 amdgpu_ring_undo(ring); 264 265 error_unlock_free: 266 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 267 268 error_wb_free: 269 amdgpu_device_wb_free(adev, status_offset); 270 return r; 271 } 272 273 static int convert_to_mes_queue_type(int queue_type) 274 { 275 if (queue_type == AMDGPU_RING_TYPE_GFX) 276 return MES_QUEUE_TYPE_GFX; 277 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 278 return MES_QUEUE_TYPE_COMPUTE; 279 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 280 return MES_QUEUE_TYPE_SDMA; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 287 struct mes_add_queue_input *input) 288 { 289 struct amdgpu_device *adev = mes->adev; 290 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 291 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 292 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 293 294 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 295 296 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 297 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 298 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 299 300 mes_add_queue_pkt.process_id = input->process_id; 301 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 302 mes_add_queue_pkt.process_va_start = input->process_va_start; 303 mes_add_queue_pkt.process_va_end = input->process_va_end; 304 mes_add_queue_pkt.process_quantum = input->process_quantum; 305 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 306 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 307 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 308 mes_add_queue_pkt.inprocess_gang_priority = 309 input->inprocess_gang_priority; 310 mes_add_queue_pkt.gang_global_priority_level = 311 input->gang_global_priority_level; 312 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 313 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 314 315 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 316 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 317 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 318 else 319 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 320 321 mes_add_queue_pkt.queue_type = 322 convert_to_mes_queue_type(input->queue_type); 323 mes_add_queue_pkt.paging = input->paging; 324 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 325 mes_add_queue_pkt.gws_base = input->gws_base; 326 mes_add_queue_pkt.gws_size = input->gws_size; 327 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 328 mes_add_queue_pkt.tma_addr = input->tma_addr; 329 mes_add_queue_pkt.trap_en = input->trap_en; 330 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 331 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 332 333 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 334 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 335 mes_add_queue_pkt.gds_size = input->queue_size; 336 337 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 338 339 return mes_v11_0_submit_pkt_and_poll_completion(mes, 340 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 341 offsetof(union MESAPI__ADD_QUEUE, api_status)); 342 } 343 344 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 345 struct mes_remove_queue_input *input) 346 { 347 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 348 349 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 350 351 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 352 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 353 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 354 355 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 356 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 357 358 return mes_v11_0_submit_pkt_and_poll_completion(mes, 359 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 360 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 361 } 362 363 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 364 struct mes_reset_queue_input *input) 365 { 366 union MESAPI__RESET mes_reset_queue_pkt; 367 368 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 369 370 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 371 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 372 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 373 374 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 375 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; 376 /*mes_reset_queue_pkt.reset_queue_only = 1;*/ 377 378 return mes_v11_0_submit_pkt_and_poll_completion(mes, 379 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 380 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 381 } 382 383 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 384 struct mes_map_legacy_queue_input *input) 385 { 386 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 387 388 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 389 390 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 391 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 392 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 393 394 mes_add_queue_pkt.pipe_id = input->pipe_id; 395 mes_add_queue_pkt.queue_id = input->queue_id; 396 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 397 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 398 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 399 mes_add_queue_pkt.queue_type = 400 convert_to_mes_queue_type(input->queue_type); 401 mes_add_queue_pkt.map_legacy_kq = 1; 402 403 return mes_v11_0_submit_pkt_and_poll_completion(mes, 404 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 405 offsetof(union MESAPI__ADD_QUEUE, api_status)); 406 } 407 408 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 409 struct mes_unmap_legacy_queue_input *input) 410 { 411 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 412 413 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 414 415 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 416 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 417 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 418 419 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 420 mes_remove_queue_pkt.gang_context_addr = 0; 421 422 mes_remove_queue_pkt.pipe_id = input->pipe_id; 423 mes_remove_queue_pkt.queue_id = input->queue_id; 424 425 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 426 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 427 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 428 mes_remove_queue_pkt.tf_data = 429 lower_32_bits(input->trail_fence_data); 430 } else { 431 mes_remove_queue_pkt.unmap_legacy_queue = 1; 432 mes_remove_queue_pkt.queue_type = 433 convert_to_mes_queue_type(input->queue_type); 434 } 435 436 return mes_v11_0_submit_pkt_and_poll_completion(mes, 437 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 438 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 439 } 440 441 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 442 struct mes_suspend_gang_input *input) 443 { 444 union MESAPI__SUSPEND mes_suspend_gang_pkt; 445 446 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 447 448 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 449 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 450 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 451 452 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 453 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 454 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 455 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 456 457 return mes_v11_0_submit_pkt_and_poll_completion(mes, 458 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 459 offsetof(union MESAPI__SUSPEND, api_status)); 460 } 461 462 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 463 struct mes_resume_gang_input *input) 464 { 465 union MESAPI__RESUME mes_resume_gang_pkt; 466 467 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 468 469 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 470 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 471 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 472 473 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 474 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 475 476 return mes_v11_0_submit_pkt_and_poll_completion(mes, 477 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 478 offsetof(union MESAPI__RESUME, api_status)); 479 } 480 481 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 482 { 483 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 484 485 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 486 487 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 488 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 489 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 490 491 return mes_v11_0_submit_pkt_and_poll_completion(mes, 492 &mes_status_pkt, sizeof(mes_status_pkt), 493 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 494 } 495 496 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 497 struct mes_misc_op_input *input) 498 { 499 union MESAPI__MISC misc_pkt; 500 501 memset(&misc_pkt, 0, sizeof(misc_pkt)); 502 503 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 504 misc_pkt.header.opcode = MES_SCH_API_MISC; 505 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 506 507 switch (input->op) { 508 case MES_MISC_OP_READ_REG: 509 misc_pkt.opcode = MESAPI_MISC__READ_REG; 510 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 511 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 512 break; 513 case MES_MISC_OP_WRITE_REG: 514 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 515 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 516 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 517 break; 518 case MES_MISC_OP_WRM_REG_WAIT: 519 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 520 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 521 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 522 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 523 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 524 misc_pkt.wait_reg_mem.reg_offset2 = 0; 525 break; 526 case MES_MISC_OP_WRM_REG_WR_WAIT: 527 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 528 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 529 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 530 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 531 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 532 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 533 break; 534 case MES_MISC_OP_SET_SHADER_DEBUGGER: 535 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 536 misc_pkt.set_shader_debugger.process_context_addr = 537 input->set_shader_debugger.process_context_addr; 538 misc_pkt.set_shader_debugger.flags.u32all = 539 input->set_shader_debugger.flags.u32all; 540 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 541 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 542 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 543 input->set_shader_debugger.tcp_watch_cntl, 544 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 545 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 546 break; 547 default: 548 DRM_ERROR("unsupported misc op (%d) \n", input->op); 549 return -EINVAL; 550 } 551 552 return mes_v11_0_submit_pkt_and_poll_completion(mes, 553 &misc_pkt, sizeof(misc_pkt), 554 offsetof(union MESAPI__MISC, api_status)); 555 } 556 557 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 558 { 559 int i; 560 struct amdgpu_device *adev = mes->adev; 561 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 562 563 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 564 565 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 566 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 567 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 568 569 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 570 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 571 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 572 mes_set_hw_res_pkt.paging_vmid = 0; 573 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 574 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 575 mes->query_status_fence_gpu_addr[0]; 576 577 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 578 mes_set_hw_res_pkt.compute_hqd_mask[i] = 579 mes->compute_hqd_mask[i]; 580 581 for (i = 0; i < MAX_GFX_PIPES; i++) 582 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 583 584 for (i = 0; i < MAX_SDMA_PIPES; i++) 585 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 586 587 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 588 mes_set_hw_res_pkt.aggregated_doorbells[i] = 589 mes->aggregated_doorbells[i]; 590 591 for (i = 0; i < 5; i++) { 592 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 593 mes_set_hw_res_pkt.mmhub_base[i] = 594 adev->reg_offset[MMHUB_HWIP][0][i]; 595 mes_set_hw_res_pkt.osssys_base[i] = 596 adev->reg_offset[OSSSYS_HWIP][0][i]; 597 } 598 599 mes_set_hw_res_pkt.disable_reset = 1; 600 mes_set_hw_res_pkt.disable_mes_log = 1; 601 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 602 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 603 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 604 mes_set_hw_res_pkt.oversubscription_timer = 50; 605 if (amdgpu_mes_log_enable) { 606 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 607 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 608 mes->event_log_gpu_addr; 609 } 610 611 return mes_v11_0_submit_pkt_and_poll_completion(mes, 612 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 613 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 614 } 615 616 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 617 { 618 int size = 128 * PAGE_SIZE; 619 int ret = 0; 620 struct amdgpu_device *adev = mes->adev; 621 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 622 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 623 624 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 625 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 626 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 627 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 628 629 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 630 AMDGPU_GEM_DOMAIN_VRAM, 631 &mes->resource_1, 632 &mes->resource_1_gpu_addr, 633 &mes->resource_1_addr); 634 if (ret) { 635 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 636 return ret; 637 } 638 639 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 640 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 641 return mes_v11_0_submit_pkt_and_poll_completion(mes, 642 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 643 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 644 } 645 646 static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes, 647 struct mes_reset_legacy_queue_input *input) 648 { 649 union MESAPI__RESET mes_reset_queue_pkt; 650 651 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 652 653 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 654 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 655 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 656 657 mes_reset_queue_pkt.queue_type = 658 convert_to_mes_queue_type(input->queue_type); 659 660 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { 661 mes_reset_queue_pkt.reset_legacy_gfx = 1; 662 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 663 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 664 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 665 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 666 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 667 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 668 } else { 669 mes_reset_queue_pkt.reset_queue_only = 1; 670 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 671 } 672 673 return mes_v11_0_submit_pkt_and_poll_completion(mes, 674 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 675 offsetof(union MESAPI__RESET, api_status)); 676 } 677 678 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 679 .add_hw_queue = mes_v11_0_add_hw_queue, 680 .remove_hw_queue = mes_v11_0_remove_hw_queue, 681 .map_legacy_queue = mes_v11_0_map_legacy_queue, 682 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 683 .suspend_gang = mes_v11_0_suspend_gang, 684 .resume_gang = mes_v11_0_resume_gang, 685 .misc_op = mes_v11_0_misc_op, 686 .reset_legacy_queue = mes_v11_0_reset_legacy_queue, 687 .reset_hw_queue = mes_v11_0_reset_hw_queue, 688 }; 689 690 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 691 enum admgpu_mes_pipe pipe) 692 { 693 int r; 694 const struct mes_firmware_header_v1_0 *mes_hdr; 695 const __le32 *fw_data; 696 unsigned fw_size; 697 698 mes_hdr = (const struct mes_firmware_header_v1_0 *) 699 adev->mes.fw[pipe]->data; 700 701 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 702 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 703 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 704 705 r = amdgpu_bo_create_reserved(adev, fw_size, 706 PAGE_SIZE, 707 AMDGPU_GEM_DOMAIN_VRAM | 708 AMDGPU_GEM_DOMAIN_GTT, 709 &adev->mes.ucode_fw_obj[pipe], 710 &adev->mes.ucode_fw_gpu_addr[pipe], 711 (void **)&adev->mes.ucode_fw_ptr[pipe]); 712 if (r) { 713 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 714 return r; 715 } 716 717 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 718 719 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 720 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 721 722 return 0; 723 } 724 725 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 726 enum admgpu_mes_pipe pipe) 727 { 728 int r; 729 const struct mes_firmware_header_v1_0 *mes_hdr; 730 const __le32 *fw_data; 731 unsigned fw_size; 732 733 mes_hdr = (const struct mes_firmware_header_v1_0 *) 734 adev->mes.fw[pipe]->data; 735 736 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 737 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 738 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 739 740 if (fw_size > GFX_MES_DRAM_SIZE) { 741 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 742 pipe, fw_size, GFX_MES_DRAM_SIZE); 743 return -EINVAL; 744 } 745 746 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 747 64 * 1024, 748 AMDGPU_GEM_DOMAIN_VRAM | 749 AMDGPU_GEM_DOMAIN_GTT, 750 &adev->mes.data_fw_obj[pipe], 751 &adev->mes.data_fw_gpu_addr[pipe], 752 (void **)&adev->mes.data_fw_ptr[pipe]); 753 if (r) { 754 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 755 return r; 756 } 757 758 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 759 760 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 761 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 762 763 return 0; 764 } 765 766 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 767 enum admgpu_mes_pipe pipe) 768 { 769 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 770 &adev->mes.data_fw_gpu_addr[pipe], 771 (void **)&adev->mes.data_fw_ptr[pipe]); 772 773 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 774 &adev->mes.ucode_fw_gpu_addr[pipe], 775 (void **)&adev->mes.ucode_fw_ptr[pipe]); 776 } 777 778 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 779 { 780 uint64_t ucode_addr; 781 uint32_t pipe, data = 0; 782 783 if (enable) { 784 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 785 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 786 data = REG_SET_FIELD(data, CP_MES_CNTL, 787 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 788 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 789 790 mutex_lock(&adev->srbm_mutex); 791 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 792 if (!adev->enable_mes_kiq && 793 pipe == AMDGPU_MES_KIQ_PIPE) 794 continue; 795 796 soc21_grbm_select(adev, 3, pipe, 0, 0); 797 798 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 799 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 800 lower_32_bits(ucode_addr)); 801 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 802 upper_32_bits(ucode_addr)); 803 } 804 soc21_grbm_select(adev, 0, 0, 0, 0); 805 mutex_unlock(&adev->srbm_mutex); 806 807 /* unhalt MES and activate pipe0 */ 808 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 809 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 810 adev->enable_mes_kiq ? 1 : 0); 811 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 812 813 if (amdgpu_emu_mode) 814 msleep(100); 815 else 816 udelay(500); 817 } else { 818 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 819 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 820 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 821 data = REG_SET_FIELD(data, CP_MES_CNTL, 822 MES_INVALIDATE_ICACHE, 1); 823 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 824 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 825 adev->enable_mes_kiq ? 1 : 0); 826 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 827 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 828 } 829 } 830 831 /* This function is for backdoor MES firmware */ 832 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 833 enum admgpu_mes_pipe pipe, bool prime_icache) 834 { 835 int r; 836 uint32_t data; 837 uint64_t ucode_addr; 838 839 mes_v11_0_enable(adev, false); 840 841 if (!adev->mes.fw[pipe]) 842 return -EINVAL; 843 844 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 845 if (r) 846 return r; 847 848 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 849 if (r) { 850 mes_v11_0_free_ucode_buffers(adev, pipe); 851 return r; 852 } 853 854 mutex_lock(&adev->srbm_mutex); 855 /* me=3, pipe=0, queue=0 */ 856 soc21_grbm_select(adev, 3, pipe, 0, 0); 857 858 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 859 860 /* set ucode start address */ 861 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 862 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 863 lower_32_bits(ucode_addr)); 864 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 865 upper_32_bits(ucode_addr)); 866 867 /* set ucode fimrware address */ 868 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 869 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 870 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 871 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 872 873 /* set ucode instruction cache boundary to 2M-1 */ 874 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 875 876 /* set ucode data firmware address */ 877 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 878 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 879 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 880 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 881 882 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 883 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 884 885 if (prime_icache) { 886 /* invalidate ICACHE */ 887 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 888 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 889 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 890 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 891 892 /* prime the ICACHE. */ 893 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 894 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 895 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 896 } 897 898 soc21_grbm_select(adev, 0, 0, 0, 0); 899 mutex_unlock(&adev->srbm_mutex); 900 901 return 0; 902 } 903 904 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 905 enum admgpu_mes_pipe pipe) 906 { 907 int r; 908 u32 *eop; 909 910 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 911 AMDGPU_GEM_DOMAIN_GTT, 912 &adev->mes.eop_gpu_obj[pipe], 913 &adev->mes.eop_gpu_addr[pipe], 914 (void **)&eop); 915 if (r) { 916 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 917 return r; 918 } 919 920 memset(eop, 0, 921 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 922 923 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 924 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 925 926 return 0; 927 } 928 929 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 930 { 931 struct v11_compute_mqd *mqd = ring->mqd_ptr; 932 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 933 uint32_t tmp; 934 935 memset(mqd, 0, sizeof(*mqd)); 936 937 mqd->header = 0xC0310800; 938 mqd->compute_pipelinestat_enable = 0x00000001; 939 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 940 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 941 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 942 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 943 mqd->compute_misc_reserved = 0x00000007; 944 945 eop_base_addr = ring->eop_gpu_addr >> 8; 946 947 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 948 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 949 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 950 (order_base_2(MES_EOP_SIZE / 4) - 1)); 951 952 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 953 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 954 mqd->cp_hqd_eop_control = tmp; 955 956 /* disable the queue if it's active */ 957 ring->wptr = 0; 958 mqd->cp_hqd_pq_rptr = 0; 959 mqd->cp_hqd_pq_wptr_lo = 0; 960 mqd->cp_hqd_pq_wptr_hi = 0; 961 962 /* set the pointer to the MQD */ 963 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 964 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 965 966 /* set MQD vmid to 0 */ 967 tmp = regCP_MQD_CONTROL_DEFAULT; 968 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 969 mqd->cp_mqd_control = tmp; 970 971 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 972 hqd_gpu_addr = ring->gpu_addr >> 8; 973 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 974 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 975 976 /* set the wb address whether it's enabled or not */ 977 wb_gpu_addr = ring->rptr_gpu_addr; 978 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 979 mqd->cp_hqd_pq_rptr_report_addr_hi = 980 upper_32_bits(wb_gpu_addr) & 0xffff; 981 982 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 983 wb_gpu_addr = ring->wptr_gpu_addr; 984 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 985 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 986 987 /* set up the HQD, this is similar to CP_RB0_CNTL */ 988 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 989 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 990 (order_base_2(ring->ring_size / 4) - 1)); 991 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 992 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 993 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 994 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 995 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 996 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 997 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 998 mqd->cp_hqd_pq_control = tmp; 999 1000 /* enable doorbell */ 1001 tmp = 0; 1002 if (ring->use_doorbell) { 1003 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1004 DOORBELL_OFFSET, ring->doorbell_index); 1005 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1006 DOORBELL_EN, 1); 1007 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1008 DOORBELL_SOURCE, 0); 1009 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1010 DOORBELL_HIT, 0); 1011 } else 1012 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1013 DOORBELL_EN, 0); 1014 mqd->cp_hqd_pq_doorbell_control = tmp; 1015 1016 mqd->cp_hqd_vmid = 0; 1017 /* activate the queue */ 1018 mqd->cp_hqd_active = 1; 1019 1020 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1021 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1022 PRELOAD_SIZE, 0x55); 1023 mqd->cp_hqd_persistent_state = tmp; 1024 1025 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1026 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1027 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1028 1029 amdgpu_device_flush_hdp(ring->adev, NULL); 1030 return 0; 1031 } 1032 1033 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1034 { 1035 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1036 struct amdgpu_device *adev = ring->adev; 1037 uint32_t data = 0; 1038 1039 mutex_lock(&adev->srbm_mutex); 1040 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1041 1042 /* set CP_HQD_VMID.VMID = 0. */ 1043 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1044 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1045 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1046 1047 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1048 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1049 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1050 DOORBELL_EN, 0); 1051 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1052 1053 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1054 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1055 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1056 1057 /* set CP_MQD_CONTROL.VMID=0 */ 1058 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1059 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1060 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1061 1062 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1063 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1064 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1065 1066 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1067 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1068 mqd->cp_hqd_pq_rptr_report_addr_lo); 1069 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1070 mqd->cp_hqd_pq_rptr_report_addr_hi); 1071 1072 /* set CP_HQD_PQ_CONTROL */ 1073 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1074 1075 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1076 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1077 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1078 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1079 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1080 1081 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1082 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1083 mqd->cp_hqd_pq_doorbell_control); 1084 1085 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1086 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1087 1088 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1089 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1090 1091 soc21_grbm_select(adev, 0, 0, 0, 0); 1092 mutex_unlock(&adev->srbm_mutex); 1093 } 1094 1095 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1096 { 1097 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1098 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1099 int r; 1100 1101 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1102 return -EINVAL; 1103 1104 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1105 if (r) { 1106 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1107 return r; 1108 } 1109 1110 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1111 1112 return amdgpu_ring_test_helper(kiq_ring); 1113 } 1114 1115 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1116 enum admgpu_mes_pipe pipe) 1117 { 1118 struct amdgpu_ring *ring; 1119 int r; 1120 1121 if (pipe == AMDGPU_MES_KIQ_PIPE) 1122 ring = &adev->gfx.kiq[0].ring; 1123 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1124 ring = &adev->mes.ring[0]; 1125 else 1126 BUG(); 1127 1128 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1129 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1130 *(ring->wptr_cpu_addr) = 0; 1131 *(ring->rptr_cpu_addr) = 0; 1132 amdgpu_ring_clear_ring(ring); 1133 } 1134 1135 r = mes_v11_0_mqd_init(ring); 1136 if (r) 1137 return r; 1138 1139 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1140 r = mes_v11_0_kiq_enable_queue(adev); 1141 if (r) 1142 return r; 1143 } else { 1144 mes_v11_0_queue_init_register(ring); 1145 } 1146 1147 /* get MES scheduler/KIQ versions */ 1148 mutex_lock(&adev->srbm_mutex); 1149 soc21_grbm_select(adev, 3, pipe, 0, 0); 1150 1151 if (pipe == AMDGPU_MES_SCHED_PIPE) 1152 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1153 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1154 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1155 1156 soc21_grbm_select(adev, 0, 0, 0, 0); 1157 mutex_unlock(&adev->srbm_mutex); 1158 1159 return 0; 1160 } 1161 1162 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1163 { 1164 struct amdgpu_ring *ring; 1165 1166 ring = &adev->mes.ring[0]; 1167 1168 ring->funcs = &mes_v11_0_ring_funcs; 1169 1170 ring->me = 3; 1171 ring->pipe = 0; 1172 ring->queue = 0; 1173 1174 ring->ring_obj = NULL; 1175 ring->use_doorbell = true; 1176 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1177 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1178 ring->no_scheduler = true; 1179 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1180 1181 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1182 AMDGPU_RING_PRIO_DEFAULT, NULL); 1183 } 1184 1185 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1186 { 1187 struct amdgpu_ring *ring; 1188 1189 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1190 1191 ring = &adev->gfx.kiq[0].ring; 1192 1193 ring->me = 3; 1194 ring->pipe = 1; 1195 ring->queue = 0; 1196 1197 ring->adev = NULL; 1198 ring->ring_obj = NULL; 1199 ring->use_doorbell = true; 1200 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1201 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1202 ring->no_scheduler = true; 1203 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1204 ring->me, ring->pipe, ring->queue); 1205 1206 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1207 AMDGPU_RING_PRIO_DEFAULT, NULL); 1208 } 1209 1210 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1211 enum admgpu_mes_pipe pipe) 1212 { 1213 int r, mqd_size = sizeof(struct v11_compute_mqd); 1214 struct amdgpu_ring *ring; 1215 1216 if (pipe == AMDGPU_MES_KIQ_PIPE) 1217 ring = &adev->gfx.kiq[0].ring; 1218 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1219 ring = &adev->mes.ring[0]; 1220 else 1221 BUG(); 1222 1223 if (ring->mqd_obj) 1224 return 0; 1225 1226 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1227 AMDGPU_GEM_DOMAIN_VRAM | 1228 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1229 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1230 if (r) { 1231 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1232 return r; 1233 } 1234 1235 memset(ring->mqd_ptr, 0, mqd_size); 1236 1237 /* prepare MQD backup */ 1238 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1239 if (!adev->mes.mqd_backup[pipe]) { 1240 dev_warn(adev->dev, 1241 "no memory to create MQD backup for ring %s\n", 1242 ring->name); 1243 return -ENOMEM; 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int mes_v11_0_sw_init(void *handle) 1250 { 1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1252 int pipe, r; 1253 1254 adev->mes.funcs = &mes_v11_0_funcs; 1255 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1256 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1257 1258 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; 1259 1260 r = amdgpu_mes_init(adev); 1261 if (r) 1262 return r; 1263 1264 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1265 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1266 continue; 1267 1268 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1269 if (r) 1270 return r; 1271 1272 r = mes_v11_0_mqd_sw_init(adev, pipe); 1273 if (r) 1274 return r; 1275 } 1276 1277 if (adev->enable_mes_kiq) { 1278 r = mes_v11_0_kiq_ring_init(adev); 1279 if (r) 1280 return r; 1281 } 1282 1283 r = mes_v11_0_ring_init(adev); 1284 if (r) 1285 return r; 1286 1287 return 0; 1288 } 1289 1290 static int mes_v11_0_sw_fini(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 int pipe; 1294 1295 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1296 kfree(adev->mes.mqd_backup[pipe]); 1297 1298 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1299 &adev->mes.eop_gpu_addr[pipe], 1300 NULL); 1301 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1302 } 1303 1304 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1305 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1306 &adev->gfx.kiq[0].ring.mqd_ptr); 1307 1308 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1309 &adev->mes.ring[0].mqd_gpu_addr, 1310 &adev->mes.ring[0].mqd_ptr); 1311 1312 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1313 amdgpu_ring_fini(&adev->mes.ring[0]); 1314 1315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1316 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1317 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1318 } 1319 1320 amdgpu_mes_fini(adev); 1321 return 0; 1322 } 1323 1324 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1325 { 1326 uint32_t data; 1327 int i; 1328 struct amdgpu_device *adev = ring->adev; 1329 1330 mutex_lock(&adev->srbm_mutex); 1331 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1332 1333 /* disable the queue if it's active */ 1334 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1335 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1336 for (i = 0; i < adev->usec_timeout; i++) { 1337 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1338 break; 1339 udelay(1); 1340 } 1341 } 1342 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1343 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1344 DOORBELL_EN, 0); 1345 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1346 DOORBELL_HIT, 1); 1347 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1348 1349 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1350 1351 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1352 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1353 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1354 1355 soc21_grbm_select(adev, 0, 0, 0, 0); 1356 mutex_unlock(&adev->srbm_mutex); 1357 } 1358 1359 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1360 { 1361 uint32_t tmp; 1362 struct amdgpu_device *adev = ring->adev; 1363 1364 /* tell RLC which is KIQ queue */ 1365 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1366 tmp &= 0xffffff00; 1367 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1368 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1369 tmp |= 0x80; 1370 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1371 } 1372 1373 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1374 { 1375 uint32_t tmp; 1376 1377 /* tell RLC which is KIQ dequeue */ 1378 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1379 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1380 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1381 } 1382 1383 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1384 { 1385 int r = 0; 1386 1387 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1388 1389 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1390 if (r) { 1391 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1392 return r; 1393 } 1394 1395 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1396 if (r) { 1397 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1398 return r; 1399 } 1400 1401 } 1402 1403 mes_v11_0_enable(adev, true); 1404 1405 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1406 1407 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1408 if (r) 1409 goto failure; 1410 1411 r = mes_v11_0_hw_init(adev); 1412 if (r) 1413 goto failure; 1414 1415 return r; 1416 1417 failure: 1418 mes_v11_0_hw_fini(adev); 1419 return r; 1420 } 1421 1422 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1423 { 1424 if (adev->mes.ring[0].sched.ready) { 1425 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1426 adev->mes.ring[0].sched.ready = false; 1427 } 1428 1429 if (amdgpu_sriov_vf(adev)) { 1430 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1431 mes_v11_0_kiq_clear(adev); 1432 } 1433 1434 mes_v11_0_enable(adev, false); 1435 1436 return 0; 1437 } 1438 1439 static int mes_v11_0_hw_init(void *handle) 1440 { 1441 int r; 1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1443 1444 if (adev->mes.ring[0].sched.ready) 1445 goto out; 1446 1447 if (!adev->enable_mes_kiq) { 1448 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1449 r = mes_v11_0_load_microcode(adev, 1450 AMDGPU_MES_SCHED_PIPE, true); 1451 if (r) { 1452 DRM_ERROR("failed to MES fw, r=%d\n", r); 1453 return r; 1454 } 1455 } 1456 1457 mes_v11_0_enable(adev, true); 1458 } 1459 1460 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1461 if (r) 1462 goto failure; 1463 1464 r = mes_v11_0_set_hw_resources(&adev->mes); 1465 if (r) 1466 goto failure; 1467 1468 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1469 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1470 if (r) { 1471 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1472 goto failure; 1473 } 1474 } 1475 1476 r = mes_v11_0_query_sched_status(&adev->mes); 1477 if (r) { 1478 DRM_ERROR("MES is busy\n"); 1479 goto failure; 1480 } 1481 1482 out: 1483 /* 1484 * Disable KIQ ring usage from the driver once MES is enabled. 1485 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1486 * with MES enabled. 1487 */ 1488 adev->gfx.kiq[0].ring.sched.ready = false; 1489 adev->mes.ring[0].sched.ready = true; 1490 1491 return 0; 1492 1493 failure: 1494 mes_v11_0_hw_fini(adev); 1495 return r; 1496 } 1497 1498 static int mes_v11_0_hw_fini(void *handle) 1499 { 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1501 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1502 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1503 &adev->mes.resource_1_addr); 1504 } 1505 return 0; 1506 } 1507 1508 static int mes_v11_0_suspend(void *handle) 1509 { 1510 int r; 1511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1512 1513 r = amdgpu_mes_suspend(adev); 1514 if (r) 1515 return r; 1516 1517 return mes_v11_0_hw_fini(adev); 1518 } 1519 1520 static int mes_v11_0_resume(void *handle) 1521 { 1522 int r; 1523 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1524 1525 r = mes_v11_0_hw_init(adev); 1526 if (r) 1527 return r; 1528 1529 return amdgpu_mes_resume(adev); 1530 } 1531 1532 static int mes_v11_0_early_init(void *handle) 1533 { 1534 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1535 int pipe, r; 1536 1537 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1538 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1539 continue; 1540 r = amdgpu_mes_init_microcode(adev, pipe); 1541 if (r) 1542 return r; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static int mes_v11_0_late_init(void *handle) 1549 { 1550 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1551 1552 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1553 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1554 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1555 amdgpu_mes_self_test(adev); 1556 1557 return 0; 1558 } 1559 1560 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1561 .name = "mes_v11_0", 1562 .early_init = mes_v11_0_early_init, 1563 .late_init = mes_v11_0_late_init, 1564 .sw_init = mes_v11_0_sw_init, 1565 .sw_fini = mes_v11_0_sw_fini, 1566 .hw_init = mes_v11_0_hw_init, 1567 .hw_fini = mes_v11_0_hw_fini, 1568 .suspend = mes_v11_0_suspend, 1569 .resume = mes_v11_0_resume, 1570 .dump_ip_state = NULL, 1571 .print_ip_state = NULL, 1572 }; 1573 1574 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1575 .type = AMD_IP_BLOCK_TYPE_MES, 1576 .major = 11, 1577 .minor = 0, 1578 .rev = 0, 1579 .funcs = &mes_v11_0_ip_funcs, 1580 }; 1581