1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 56 57 static int mes_v11_0_hw_init(void *handle); 58 static int mes_v11_0_hw_fini(void *handle); 59 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 60 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 61 62 #define MES_EOP_SIZE 2048 63 #define GFX_MES_DRAM_SIZE 0x80000 64 65 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 66 { 67 struct amdgpu_device *adev = ring->adev; 68 69 if (ring->use_doorbell) { 70 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 71 ring->wptr); 72 WDOORBELL64(ring->doorbell_index, ring->wptr); 73 } else { 74 BUG(); 75 } 76 } 77 78 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 79 { 80 return *ring->rptr_cpu_addr; 81 } 82 83 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 84 { 85 u64 wptr; 86 87 if (ring->use_doorbell) 88 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 89 else 90 BUG(); 91 return wptr; 92 } 93 94 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 95 .type = AMDGPU_RING_TYPE_MES, 96 .align_mask = 1, 97 .nop = 0, 98 .support_64bit_ptrs = true, 99 .get_rptr = mes_v11_0_ring_get_rptr, 100 .get_wptr = mes_v11_0_ring_get_wptr, 101 .set_wptr = mes_v11_0_ring_set_wptr, 102 .insert_nop = amdgpu_ring_insert_nop, 103 }; 104 105 static const char *mes_v11_0_opcodes[] = { 106 "SET_HW_RSRC", 107 "SET_SCHEDULING_CONFIG", 108 "ADD_QUEUE", 109 "REMOVE_QUEUE", 110 "PERFORM_YIELD", 111 "SET_GANG_PRIORITY_LEVEL", 112 "SUSPEND", 113 "RESUME", 114 "RESET", 115 "SET_LOG_BUFFER", 116 "CHANGE_GANG_PRORITY", 117 "QUERY_SCHEDULER_STATUS", 118 "PROGRAM_GDS", 119 "SET_DEBUG_VMID", 120 "MISC", 121 "UPDATE_ROOT_PAGE_TABLE", 122 "AMD_LOG", 123 "unused", 124 "unused", 125 "SET_HW_RSRC_1", 126 }; 127 128 static const char *mes_v11_0_misc_opcodes[] = { 129 "WRITE_REG", 130 "INV_GART", 131 "QUERY_STATUS", 132 "READ_REG", 133 "WAIT_REG_MEM", 134 "SET_SHADER_DEBUGGER", 135 }; 136 137 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 138 { 139 const char *op_str = NULL; 140 141 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 142 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 143 144 return op_str; 145 } 146 147 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 148 { 149 const char *op_str = NULL; 150 151 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 152 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 153 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 154 155 return op_str; 156 } 157 158 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 159 void *pkt, int size, 160 int api_status_off) 161 { 162 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 163 signed long timeout = 3000000; /* 3000 ms */ 164 struct amdgpu_device *adev = mes->adev; 165 struct amdgpu_ring *ring = &mes->ring[0]; 166 struct MES_API_STATUS *api_status; 167 union MESAPI__MISC *x_pkt = pkt; 168 const char *op_str, *misc_op_str; 169 unsigned long flags; 170 u64 status_gpu_addr; 171 u32 seq, status_offset; 172 u64 *status_ptr; 173 signed long r; 174 int ret; 175 176 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 177 return -EINVAL; 178 179 if (amdgpu_emu_mode) { 180 timeout *= 100; 181 } else if (amdgpu_sriov_vf(adev)) { 182 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 183 timeout = 15 * 600 * 1000; 184 } 185 186 ret = amdgpu_device_wb_get(adev, &status_offset); 187 if (ret) 188 return ret; 189 190 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 191 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 192 *status_ptr = 0; 193 194 spin_lock_irqsave(&mes->ring_lock[0], flags); 195 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 196 if (r) 197 goto error_unlock_free; 198 199 seq = ++ring->fence_drv.sync_seq; 200 r = amdgpu_fence_wait_polling(ring, 201 seq - ring->fence_drv.num_fences_mask, 202 timeout); 203 if (r < 1) 204 goto error_undo; 205 206 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 207 api_status->api_completion_fence_addr = status_gpu_addr; 208 api_status->api_completion_fence_value = 1; 209 210 amdgpu_ring_write_multiple(ring, pkt, size / 4); 211 212 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 213 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 214 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 215 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 216 mes_status_pkt.api_status.api_completion_fence_addr = 217 ring->fence_drv.gpu_addr; 218 mes_status_pkt.api_status.api_completion_fence_value = seq; 219 220 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 221 sizeof(mes_status_pkt) / 4); 222 223 amdgpu_ring_commit(ring); 224 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 225 226 op_str = mes_v11_0_get_op_string(x_pkt); 227 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 228 229 if (misc_op_str) 230 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 231 misc_op_str); 232 else if (op_str) 233 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 234 else 235 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 236 x_pkt->header.opcode); 237 238 r = amdgpu_fence_wait_polling(ring, seq, timeout); 239 if (r < 1 || !*status_ptr) { 240 241 if (misc_op_str) 242 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 243 op_str, misc_op_str); 244 else if (op_str) 245 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 246 op_str); 247 else 248 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 249 x_pkt->header.opcode); 250 251 while (halt_if_hws_hang) 252 schedule(); 253 254 r = -ETIMEDOUT; 255 goto error_wb_free; 256 } 257 258 amdgpu_device_wb_free(adev, status_offset); 259 return 0; 260 261 error_undo: 262 dev_err(adev->dev, "MES ring buffer is full.\n"); 263 amdgpu_ring_undo(ring); 264 265 error_unlock_free: 266 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 267 268 error_wb_free: 269 amdgpu_device_wb_free(adev, status_offset); 270 return r; 271 } 272 273 static int convert_to_mes_queue_type(int queue_type) 274 { 275 if (queue_type == AMDGPU_RING_TYPE_GFX) 276 return MES_QUEUE_TYPE_GFX; 277 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 278 return MES_QUEUE_TYPE_COMPUTE; 279 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 280 return MES_QUEUE_TYPE_SDMA; 281 else 282 BUG(); 283 return -1; 284 } 285 286 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 287 struct mes_add_queue_input *input) 288 { 289 struct amdgpu_device *adev = mes->adev; 290 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 291 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 292 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 293 294 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 295 296 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 297 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 298 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 299 300 mes_add_queue_pkt.process_id = input->process_id; 301 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 302 mes_add_queue_pkt.process_va_start = input->process_va_start; 303 mes_add_queue_pkt.process_va_end = input->process_va_end; 304 mes_add_queue_pkt.process_quantum = input->process_quantum; 305 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 306 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 307 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 308 mes_add_queue_pkt.inprocess_gang_priority = 309 input->inprocess_gang_priority; 310 mes_add_queue_pkt.gang_global_priority_level = 311 input->gang_global_priority_level; 312 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 313 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 314 315 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 316 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 317 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 318 else 319 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 320 321 mes_add_queue_pkt.queue_type = 322 convert_to_mes_queue_type(input->queue_type); 323 mes_add_queue_pkt.paging = input->paging; 324 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 325 mes_add_queue_pkt.gws_base = input->gws_base; 326 mes_add_queue_pkt.gws_size = input->gws_size; 327 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 328 mes_add_queue_pkt.tma_addr = input->tma_addr; 329 mes_add_queue_pkt.trap_en = input->trap_en; 330 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 331 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 332 333 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 334 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 335 mes_add_queue_pkt.gds_size = input->queue_size; 336 337 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 338 339 return mes_v11_0_submit_pkt_and_poll_completion(mes, 340 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 341 offsetof(union MESAPI__ADD_QUEUE, api_status)); 342 } 343 344 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 345 struct mes_remove_queue_input *input) 346 { 347 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 348 349 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 350 351 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 352 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 353 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 354 355 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 356 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 357 358 return mes_v11_0_submit_pkt_and_poll_completion(mes, 359 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 360 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 361 } 362 363 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 364 struct mes_map_legacy_queue_input *input) 365 { 366 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 367 368 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 369 370 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 371 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 372 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 373 374 mes_add_queue_pkt.pipe_id = input->pipe_id; 375 mes_add_queue_pkt.queue_id = input->queue_id; 376 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 377 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 378 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 379 mes_add_queue_pkt.queue_type = 380 convert_to_mes_queue_type(input->queue_type); 381 mes_add_queue_pkt.map_legacy_kq = 1; 382 383 return mes_v11_0_submit_pkt_and_poll_completion(mes, 384 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 385 offsetof(union MESAPI__ADD_QUEUE, api_status)); 386 } 387 388 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 389 struct mes_unmap_legacy_queue_input *input) 390 { 391 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 392 393 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 394 395 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 396 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 397 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 398 399 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 400 mes_remove_queue_pkt.gang_context_addr = 0; 401 402 mes_remove_queue_pkt.pipe_id = input->pipe_id; 403 mes_remove_queue_pkt.queue_id = input->queue_id; 404 405 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 406 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 407 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 408 mes_remove_queue_pkt.tf_data = 409 lower_32_bits(input->trail_fence_data); 410 } else { 411 mes_remove_queue_pkt.unmap_legacy_queue = 1; 412 mes_remove_queue_pkt.queue_type = 413 convert_to_mes_queue_type(input->queue_type); 414 } 415 416 return mes_v11_0_submit_pkt_and_poll_completion(mes, 417 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 418 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 419 } 420 421 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 422 struct mes_suspend_gang_input *input) 423 { 424 return 0; 425 } 426 427 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 428 struct mes_resume_gang_input *input) 429 { 430 return 0; 431 } 432 433 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 434 { 435 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 436 437 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 438 439 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 440 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 441 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 442 443 return mes_v11_0_submit_pkt_and_poll_completion(mes, 444 &mes_status_pkt, sizeof(mes_status_pkt), 445 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 446 } 447 448 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 449 struct mes_misc_op_input *input) 450 { 451 union MESAPI__MISC misc_pkt; 452 453 memset(&misc_pkt, 0, sizeof(misc_pkt)); 454 455 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 456 misc_pkt.header.opcode = MES_SCH_API_MISC; 457 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 458 459 switch (input->op) { 460 case MES_MISC_OP_READ_REG: 461 misc_pkt.opcode = MESAPI_MISC__READ_REG; 462 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 463 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 464 break; 465 case MES_MISC_OP_WRITE_REG: 466 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 467 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 468 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 469 break; 470 case MES_MISC_OP_WRM_REG_WAIT: 471 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 472 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 473 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 474 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 475 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 476 misc_pkt.wait_reg_mem.reg_offset2 = 0; 477 break; 478 case MES_MISC_OP_WRM_REG_WR_WAIT: 479 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 480 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 481 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 482 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 483 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 484 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 485 break; 486 case MES_MISC_OP_SET_SHADER_DEBUGGER: 487 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 488 misc_pkt.set_shader_debugger.process_context_addr = 489 input->set_shader_debugger.process_context_addr; 490 misc_pkt.set_shader_debugger.flags.u32all = 491 input->set_shader_debugger.flags.u32all; 492 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 493 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 494 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 495 input->set_shader_debugger.tcp_watch_cntl, 496 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 497 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 498 break; 499 default: 500 DRM_ERROR("unsupported misc op (%d) \n", input->op); 501 return -EINVAL; 502 } 503 504 return mes_v11_0_submit_pkt_and_poll_completion(mes, 505 &misc_pkt, sizeof(misc_pkt), 506 offsetof(union MESAPI__MISC, api_status)); 507 } 508 509 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 510 { 511 int i; 512 struct amdgpu_device *adev = mes->adev; 513 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 514 515 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 516 517 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 518 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 519 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 520 521 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 522 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 523 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 524 mes_set_hw_res_pkt.paging_vmid = 0; 525 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 526 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 527 mes->query_status_fence_gpu_addr[0]; 528 529 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 530 mes_set_hw_res_pkt.compute_hqd_mask[i] = 531 mes->compute_hqd_mask[i]; 532 533 for (i = 0; i < MAX_GFX_PIPES; i++) 534 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 535 536 for (i = 0; i < MAX_SDMA_PIPES; i++) 537 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 538 539 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 540 mes_set_hw_res_pkt.aggregated_doorbells[i] = 541 mes->aggregated_doorbells[i]; 542 543 for (i = 0; i < 5; i++) { 544 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 545 mes_set_hw_res_pkt.mmhub_base[i] = 546 adev->reg_offset[MMHUB_HWIP][0][i]; 547 mes_set_hw_res_pkt.osssys_base[i] = 548 adev->reg_offset[OSSSYS_HWIP][0][i]; 549 } 550 551 mes_set_hw_res_pkt.disable_reset = 1; 552 mes_set_hw_res_pkt.disable_mes_log = 1; 553 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 554 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 555 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 556 mes_set_hw_res_pkt.oversubscription_timer = 50; 557 if (amdgpu_mes_log_enable) { 558 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 559 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 560 mes->event_log_gpu_addr; 561 } 562 563 return mes_v11_0_submit_pkt_and_poll_completion(mes, 564 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 565 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 566 } 567 568 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 569 { 570 int size = 128 * PAGE_SIZE; 571 int ret = 0; 572 struct amdgpu_device *adev = mes->adev; 573 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 574 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 575 576 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 577 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 578 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 579 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 580 581 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 582 AMDGPU_GEM_DOMAIN_VRAM, 583 &mes->resource_1, 584 &mes->resource_1_gpu_addr, 585 &mes->resource_1_addr); 586 if (ret) { 587 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 588 return ret; 589 } 590 591 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 592 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 593 return mes_v11_0_submit_pkt_and_poll_completion(mes, 594 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 595 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 596 } 597 598 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 599 .add_hw_queue = mes_v11_0_add_hw_queue, 600 .remove_hw_queue = mes_v11_0_remove_hw_queue, 601 .map_legacy_queue = mes_v11_0_map_legacy_queue, 602 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 603 .suspend_gang = mes_v11_0_suspend_gang, 604 .resume_gang = mes_v11_0_resume_gang, 605 .misc_op = mes_v11_0_misc_op, 606 }; 607 608 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 609 enum admgpu_mes_pipe pipe) 610 { 611 int r; 612 const struct mes_firmware_header_v1_0 *mes_hdr; 613 const __le32 *fw_data; 614 unsigned fw_size; 615 616 mes_hdr = (const struct mes_firmware_header_v1_0 *) 617 adev->mes.fw[pipe]->data; 618 619 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 620 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 621 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 622 623 r = amdgpu_bo_create_reserved(adev, fw_size, 624 PAGE_SIZE, 625 AMDGPU_GEM_DOMAIN_VRAM | 626 AMDGPU_GEM_DOMAIN_GTT, 627 &adev->mes.ucode_fw_obj[pipe], 628 &adev->mes.ucode_fw_gpu_addr[pipe], 629 (void **)&adev->mes.ucode_fw_ptr[pipe]); 630 if (r) { 631 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 632 return r; 633 } 634 635 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 636 637 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 638 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 639 640 return 0; 641 } 642 643 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 644 enum admgpu_mes_pipe pipe) 645 { 646 int r; 647 const struct mes_firmware_header_v1_0 *mes_hdr; 648 const __le32 *fw_data; 649 unsigned fw_size; 650 651 mes_hdr = (const struct mes_firmware_header_v1_0 *) 652 adev->mes.fw[pipe]->data; 653 654 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 655 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 656 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 657 658 if (fw_size > GFX_MES_DRAM_SIZE) { 659 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 660 pipe, fw_size, GFX_MES_DRAM_SIZE); 661 return -EINVAL; 662 } 663 664 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 665 64 * 1024, 666 AMDGPU_GEM_DOMAIN_VRAM | 667 AMDGPU_GEM_DOMAIN_GTT, 668 &adev->mes.data_fw_obj[pipe], 669 &adev->mes.data_fw_gpu_addr[pipe], 670 (void **)&adev->mes.data_fw_ptr[pipe]); 671 if (r) { 672 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 673 return r; 674 } 675 676 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 677 678 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 679 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 680 681 return 0; 682 } 683 684 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 685 enum admgpu_mes_pipe pipe) 686 { 687 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 688 &adev->mes.data_fw_gpu_addr[pipe], 689 (void **)&adev->mes.data_fw_ptr[pipe]); 690 691 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 692 &adev->mes.ucode_fw_gpu_addr[pipe], 693 (void **)&adev->mes.ucode_fw_ptr[pipe]); 694 } 695 696 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 697 { 698 uint64_t ucode_addr; 699 uint32_t pipe, data = 0; 700 701 if (enable) { 702 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 703 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 704 data = REG_SET_FIELD(data, CP_MES_CNTL, 705 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 706 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 707 708 mutex_lock(&adev->srbm_mutex); 709 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 710 if (!adev->enable_mes_kiq && 711 pipe == AMDGPU_MES_KIQ_PIPE) 712 continue; 713 714 soc21_grbm_select(adev, 3, pipe, 0, 0); 715 716 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 717 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 718 lower_32_bits(ucode_addr)); 719 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 720 upper_32_bits(ucode_addr)); 721 } 722 soc21_grbm_select(adev, 0, 0, 0, 0); 723 mutex_unlock(&adev->srbm_mutex); 724 725 /* unhalt MES and activate pipe0 */ 726 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 727 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 728 adev->enable_mes_kiq ? 1 : 0); 729 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 730 731 if (amdgpu_emu_mode) 732 msleep(100); 733 else 734 udelay(500); 735 } else { 736 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 737 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 738 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 739 data = REG_SET_FIELD(data, CP_MES_CNTL, 740 MES_INVALIDATE_ICACHE, 1); 741 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 742 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 743 adev->enable_mes_kiq ? 1 : 0); 744 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 745 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 746 } 747 } 748 749 /* This function is for backdoor MES firmware */ 750 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 751 enum admgpu_mes_pipe pipe, bool prime_icache) 752 { 753 int r; 754 uint32_t data; 755 uint64_t ucode_addr; 756 757 mes_v11_0_enable(adev, false); 758 759 if (!adev->mes.fw[pipe]) 760 return -EINVAL; 761 762 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 763 if (r) 764 return r; 765 766 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 767 if (r) { 768 mes_v11_0_free_ucode_buffers(adev, pipe); 769 return r; 770 } 771 772 mutex_lock(&adev->srbm_mutex); 773 /* me=3, pipe=0, queue=0 */ 774 soc21_grbm_select(adev, 3, pipe, 0, 0); 775 776 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 777 778 /* set ucode start address */ 779 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 780 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 781 lower_32_bits(ucode_addr)); 782 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 783 upper_32_bits(ucode_addr)); 784 785 /* set ucode fimrware address */ 786 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 787 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 788 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 789 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 790 791 /* set ucode instruction cache boundary to 2M-1 */ 792 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 793 794 /* set ucode data firmware address */ 795 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 796 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 797 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 798 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 799 800 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 801 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 802 803 if (prime_icache) { 804 /* invalidate ICACHE */ 805 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 806 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 807 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 808 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 809 810 /* prime the ICACHE. */ 811 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 812 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 813 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 814 } 815 816 soc21_grbm_select(adev, 0, 0, 0, 0); 817 mutex_unlock(&adev->srbm_mutex); 818 819 return 0; 820 } 821 822 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 823 enum admgpu_mes_pipe pipe) 824 { 825 int r; 826 u32 *eop; 827 828 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 829 AMDGPU_GEM_DOMAIN_GTT, 830 &adev->mes.eop_gpu_obj[pipe], 831 &adev->mes.eop_gpu_addr[pipe], 832 (void **)&eop); 833 if (r) { 834 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 835 return r; 836 } 837 838 memset(eop, 0, 839 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 840 841 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 842 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 843 844 return 0; 845 } 846 847 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 848 { 849 struct v11_compute_mqd *mqd = ring->mqd_ptr; 850 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 851 uint32_t tmp; 852 853 memset(mqd, 0, sizeof(*mqd)); 854 855 mqd->header = 0xC0310800; 856 mqd->compute_pipelinestat_enable = 0x00000001; 857 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 858 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 859 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 860 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 861 mqd->compute_misc_reserved = 0x00000007; 862 863 eop_base_addr = ring->eop_gpu_addr >> 8; 864 865 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 866 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 867 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 868 (order_base_2(MES_EOP_SIZE / 4) - 1)); 869 870 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 871 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 872 mqd->cp_hqd_eop_control = tmp; 873 874 /* disable the queue if it's active */ 875 ring->wptr = 0; 876 mqd->cp_hqd_pq_rptr = 0; 877 mqd->cp_hqd_pq_wptr_lo = 0; 878 mqd->cp_hqd_pq_wptr_hi = 0; 879 880 /* set the pointer to the MQD */ 881 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 882 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 883 884 /* set MQD vmid to 0 */ 885 tmp = regCP_MQD_CONTROL_DEFAULT; 886 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 887 mqd->cp_mqd_control = tmp; 888 889 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 890 hqd_gpu_addr = ring->gpu_addr >> 8; 891 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 892 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 893 894 /* set the wb address whether it's enabled or not */ 895 wb_gpu_addr = ring->rptr_gpu_addr; 896 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 897 mqd->cp_hqd_pq_rptr_report_addr_hi = 898 upper_32_bits(wb_gpu_addr) & 0xffff; 899 900 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 901 wb_gpu_addr = ring->wptr_gpu_addr; 902 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 903 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 904 905 /* set up the HQD, this is similar to CP_RB0_CNTL */ 906 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 907 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 908 (order_base_2(ring->ring_size / 4) - 1)); 909 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 910 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 914 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 915 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 916 mqd->cp_hqd_pq_control = tmp; 917 918 /* enable doorbell */ 919 tmp = 0; 920 if (ring->use_doorbell) { 921 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 922 DOORBELL_OFFSET, ring->doorbell_index); 923 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 924 DOORBELL_EN, 1); 925 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 926 DOORBELL_SOURCE, 0); 927 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 928 DOORBELL_HIT, 0); 929 } else 930 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 931 DOORBELL_EN, 0); 932 mqd->cp_hqd_pq_doorbell_control = tmp; 933 934 mqd->cp_hqd_vmid = 0; 935 /* activate the queue */ 936 mqd->cp_hqd_active = 1; 937 938 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 939 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 940 PRELOAD_SIZE, 0x55); 941 mqd->cp_hqd_persistent_state = tmp; 942 943 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 944 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 945 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 946 947 amdgpu_device_flush_hdp(ring->adev, NULL); 948 return 0; 949 } 950 951 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 952 { 953 struct v11_compute_mqd *mqd = ring->mqd_ptr; 954 struct amdgpu_device *adev = ring->adev; 955 uint32_t data = 0; 956 957 mutex_lock(&adev->srbm_mutex); 958 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 959 960 /* set CP_HQD_VMID.VMID = 0. */ 961 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 962 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 963 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 964 965 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 966 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 967 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 968 DOORBELL_EN, 0); 969 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 970 971 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 972 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 973 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 974 975 /* set CP_MQD_CONTROL.VMID=0 */ 976 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 977 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 978 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 979 980 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 981 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 982 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 983 984 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 985 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 986 mqd->cp_hqd_pq_rptr_report_addr_lo); 987 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 988 mqd->cp_hqd_pq_rptr_report_addr_hi); 989 990 /* set CP_HQD_PQ_CONTROL */ 991 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 992 993 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 994 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 995 mqd->cp_hqd_pq_wptr_poll_addr_lo); 996 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 997 mqd->cp_hqd_pq_wptr_poll_addr_hi); 998 999 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1000 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1001 mqd->cp_hqd_pq_doorbell_control); 1002 1003 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1004 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1005 1006 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1007 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1008 1009 soc21_grbm_select(adev, 0, 0, 0, 0); 1010 mutex_unlock(&adev->srbm_mutex); 1011 } 1012 1013 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1014 { 1015 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1016 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1017 int r; 1018 1019 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1020 return -EINVAL; 1021 1022 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1023 if (r) { 1024 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1025 return r; 1026 } 1027 1028 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1029 1030 return amdgpu_ring_test_helper(kiq_ring); 1031 } 1032 1033 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1034 enum admgpu_mes_pipe pipe) 1035 { 1036 struct amdgpu_ring *ring; 1037 int r; 1038 1039 if (pipe == AMDGPU_MES_KIQ_PIPE) 1040 ring = &adev->gfx.kiq[0].ring; 1041 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1042 ring = &adev->mes.ring[0]; 1043 else 1044 BUG(); 1045 1046 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1047 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1048 *(ring->wptr_cpu_addr) = 0; 1049 *(ring->rptr_cpu_addr) = 0; 1050 amdgpu_ring_clear_ring(ring); 1051 } 1052 1053 r = mes_v11_0_mqd_init(ring); 1054 if (r) 1055 return r; 1056 1057 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1058 r = mes_v11_0_kiq_enable_queue(adev); 1059 if (r) 1060 return r; 1061 } else { 1062 mes_v11_0_queue_init_register(ring); 1063 } 1064 1065 /* get MES scheduler/KIQ versions */ 1066 mutex_lock(&adev->srbm_mutex); 1067 soc21_grbm_select(adev, 3, pipe, 0, 0); 1068 1069 if (pipe == AMDGPU_MES_SCHED_PIPE) 1070 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1071 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1072 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1073 1074 soc21_grbm_select(adev, 0, 0, 0, 0); 1075 mutex_unlock(&adev->srbm_mutex); 1076 1077 return 0; 1078 } 1079 1080 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1081 { 1082 struct amdgpu_ring *ring; 1083 1084 ring = &adev->mes.ring[0]; 1085 1086 ring->funcs = &mes_v11_0_ring_funcs; 1087 1088 ring->me = 3; 1089 ring->pipe = 0; 1090 ring->queue = 0; 1091 1092 ring->ring_obj = NULL; 1093 ring->use_doorbell = true; 1094 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1095 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1096 ring->no_scheduler = true; 1097 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1098 1099 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1100 AMDGPU_RING_PRIO_DEFAULT, NULL); 1101 } 1102 1103 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1104 { 1105 struct amdgpu_ring *ring; 1106 1107 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1108 1109 ring = &adev->gfx.kiq[0].ring; 1110 1111 ring->me = 3; 1112 ring->pipe = 1; 1113 ring->queue = 0; 1114 1115 ring->adev = NULL; 1116 ring->ring_obj = NULL; 1117 ring->use_doorbell = true; 1118 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1119 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1120 ring->no_scheduler = true; 1121 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1122 ring->me, ring->pipe, ring->queue); 1123 1124 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1125 AMDGPU_RING_PRIO_DEFAULT, NULL); 1126 } 1127 1128 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1129 enum admgpu_mes_pipe pipe) 1130 { 1131 int r, mqd_size = sizeof(struct v11_compute_mqd); 1132 struct amdgpu_ring *ring; 1133 1134 if (pipe == AMDGPU_MES_KIQ_PIPE) 1135 ring = &adev->gfx.kiq[0].ring; 1136 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1137 ring = &adev->mes.ring[0]; 1138 else 1139 BUG(); 1140 1141 if (ring->mqd_obj) 1142 return 0; 1143 1144 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1145 AMDGPU_GEM_DOMAIN_VRAM | 1146 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1147 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1148 if (r) { 1149 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1150 return r; 1151 } 1152 1153 memset(ring->mqd_ptr, 0, mqd_size); 1154 1155 /* prepare MQD backup */ 1156 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1157 if (!adev->mes.mqd_backup[pipe]) { 1158 dev_warn(adev->dev, 1159 "no memory to create MQD backup for ring %s\n", 1160 ring->name); 1161 return -ENOMEM; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int mes_v11_0_sw_init(void *handle) 1168 { 1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1170 int pipe, r; 1171 1172 adev->mes.funcs = &mes_v11_0_funcs; 1173 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1174 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1175 1176 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; 1177 1178 r = amdgpu_mes_init(adev); 1179 if (r) 1180 return r; 1181 1182 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1183 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1184 continue; 1185 1186 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1187 if (r) 1188 return r; 1189 1190 r = mes_v11_0_mqd_sw_init(adev, pipe); 1191 if (r) 1192 return r; 1193 } 1194 1195 if (adev->enable_mes_kiq) { 1196 r = mes_v11_0_kiq_ring_init(adev); 1197 if (r) 1198 return r; 1199 } 1200 1201 r = mes_v11_0_ring_init(adev); 1202 if (r) 1203 return r; 1204 1205 return 0; 1206 } 1207 1208 static int mes_v11_0_sw_fini(void *handle) 1209 { 1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1211 int pipe; 1212 1213 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1214 kfree(adev->mes.mqd_backup[pipe]); 1215 1216 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1217 &adev->mes.eop_gpu_addr[pipe], 1218 NULL); 1219 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1220 } 1221 1222 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1223 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1224 &adev->gfx.kiq[0].ring.mqd_ptr); 1225 1226 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1227 &adev->mes.ring[0].mqd_gpu_addr, 1228 &adev->mes.ring[0].mqd_ptr); 1229 1230 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1231 amdgpu_ring_fini(&adev->mes.ring[0]); 1232 1233 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1234 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1235 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1236 } 1237 1238 amdgpu_mes_fini(adev); 1239 return 0; 1240 } 1241 1242 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1243 { 1244 uint32_t data; 1245 int i; 1246 struct amdgpu_device *adev = ring->adev; 1247 1248 mutex_lock(&adev->srbm_mutex); 1249 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1250 1251 /* disable the queue if it's active */ 1252 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1253 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1254 for (i = 0; i < adev->usec_timeout; i++) { 1255 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1256 break; 1257 udelay(1); 1258 } 1259 } 1260 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1261 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1262 DOORBELL_EN, 0); 1263 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1264 DOORBELL_HIT, 1); 1265 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1266 1267 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1268 1269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1270 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1271 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1272 1273 soc21_grbm_select(adev, 0, 0, 0, 0); 1274 mutex_unlock(&adev->srbm_mutex); 1275 } 1276 1277 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1278 { 1279 uint32_t tmp; 1280 struct amdgpu_device *adev = ring->adev; 1281 1282 /* tell RLC which is KIQ queue */ 1283 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1284 tmp &= 0xffffff00; 1285 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1286 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1287 tmp |= 0x80; 1288 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1289 } 1290 1291 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1292 { 1293 uint32_t tmp; 1294 1295 /* tell RLC which is KIQ dequeue */ 1296 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1297 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1298 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1299 } 1300 1301 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1302 { 1303 int r = 0; 1304 1305 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1306 1307 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1308 if (r) { 1309 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1310 return r; 1311 } 1312 1313 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1314 if (r) { 1315 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1316 return r; 1317 } 1318 1319 } 1320 1321 mes_v11_0_enable(adev, true); 1322 1323 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1324 1325 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1326 if (r) 1327 goto failure; 1328 1329 r = mes_v11_0_hw_init(adev); 1330 if (r) 1331 goto failure; 1332 1333 return r; 1334 1335 failure: 1336 mes_v11_0_hw_fini(adev); 1337 return r; 1338 } 1339 1340 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1341 { 1342 if (adev->mes.ring[0].sched.ready) { 1343 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1344 adev->mes.ring[0].sched.ready = false; 1345 } 1346 1347 if (amdgpu_sriov_vf(adev)) { 1348 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1349 mes_v11_0_kiq_clear(adev); 1350 } 1351 1352 mes_v11_0_enable(adev, false); 1353 1354 return 0; 1355 } 1356 1357 static int mes_v11_0_hw_init(void *handle) 1358 { 1359 int r; 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1361 1362 if (adev->mes.ring[0].sched.ready) 1363 goto out; 1364 1365 if (!adev->enable_mes_kiq) { 1366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1367 r = mes_v11_0_load_microcode(adev, 1368 AMDGPU_MES_SCHED_PIPE, true); 1369 if (r) { 1370 DRM_ERROR("failed to MES fw, r=%d\n", r); 1371 return r; 1372 } 1373 } 1374 1375 mes_v11_0_enable(adev, true); 1376 } 1377 1378 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1379 if (r) 1380 goto failure; 1381 1382 r = mes_v11_0_set_hw_resources(&adev->mes); 1383 if (r) 1384 goto failure; 1385 1386 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1387 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1388 if (r) { 1389 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1390 goto failure; 1391 } 1392 } 1393 1394 r = mes_v11_0_query_sched_status(&adev->mes); 1395 if (r) { 1396 DRM_ERROR("MES is busy\n"); 1397 goto failure; 1398 } 1399 1400 out: 1401 /* 1402 * Disable KIQ ring usage from the driver once MES is enabled. 1403 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1404 * with MES enabled. 1405 */ 1406 adev->gfx.kiq[0].ring.sched.ready = false; 1407 adev->mes.ring[0].sched.ready = true; 1408 1409 return 0; 1410 1411 failure: 1412 mes_v11_0_hw_fini(adev); 1413 return r; 1414 } 1415 1416 static int mes_v11_0_hw_fini(void *handle) 1417 { 1418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1419 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1420 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1421 &adev->mes.resource_1_addr); 1422 } 1423 return 0; 1424 } 1425 1426 static int mes_v11_0_suspend(void *handle) 1427 { 1428 int r; 1429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1430 1431 r = amdgpu_mes_suspend(adev); 1432 if (r) 1433 return r; 1434 1435 return mes_v11_0_hw_fini(adev); 1436 } 1437 1438 static int mes_v11_0_resume(void *handle) 1439 { 1440 int r; 1441 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1442 1443 r = mes_v11_0_hw_init(adev); 1444 if (r) 1445 return r; 1446 1447 return amdgpu_mes_resume(adev); 1448 } 1449 1450 static int mes_v11_0_early_init(void *handle) 1451 { 1452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1453 int pipe, r; 1454 1455 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1456 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1457 continue; 1458 r = amdgpu_mes_init_microcode(adev, pipe); 1459 if (r) 1460 return r; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int mes_v11_0_late_init(void *handle) 1467 { 1468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 1470 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1471 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1472 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1473 amdgpu_mes_self_test(adev); 1474 1475 return 0; 1476 } 1477 1478 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1479 .name = "mes_v11_0", 1480 .early_init = mes_v11_0_early_init, 1481 .late_init = mes_v11_0_late_init, 1482 .sw_init = mes_v11_0_sw_init, 1483 .sw_fini = mes_v11_0_sw_fini, 1484 .hw_init = mes_v11_0_hw_init, 1485 .hw_fini = mes_v11_0_hw_fini, 1486 .suspend = mes_v11_0_suspend, 1487 .resume = mes_v11_0_resume, 1488 .dump_ip_state = NULL, 1489 .print_ip_state = NULL, 1490 }; 1491 1492 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1493 .type = AMD_IP_BLOCK_TYPE_MES, 1494 .major = 11, 1495 .minor = 0, 1496 .rev = 0, 1497 .funcs = &mes_v11_0_ip_funcs, 1498 }; 1499