1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 54 55 56 static int mes_v11_0_hw_fini(void *handle); 57 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 58 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 59 60 #define MES_EOP_SIZE 2048 61 #define GFX_MES_DRAM_SIZE 0x80000 62 63 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 if (ring->use_doorbell) { 68 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 69 ring->wptr); 70 WDOORBELL64(ring->doorbell_index, ring->wptr); 71 } else { 72 BUG(); 73 } 74 } 75 76 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 77 { 78 return *ring->rptr_cpu_addr; 79 } 80 81 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 82 { 83 u64 wptr; 84 85 if (ring->use_doorbell) 86 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 87 else 88 BUG(); 89 return wptr; 90 } 91 92 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 93 .type = AMDGPU_RING_TYPE_MES, 94 .align_mask = 1, 95 .nop = 0, 96 .support_64bit_ptrs = true, 97 .get_rptr = mes_v11_0_ring_get_rptr, 98 .get_wptr = mes_v11_0_ring_get_wptr, 99 .set_wptr = mes_v11_0_ring_set_wptr, 100 .insert_nop = amdgpu_ring_insert_nop, 101 }; 102 103 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 104 void *pkt, int size, 105 int api_status_off) 106 { 107 int ndw = size / 4; 108 signed long r; 109 union MESAPI__ADD_QUEUE *x_pkt = pkt; 110 struct MES_API_STATUS *api_status; 111 struct amdgpu_device *adev = mes->adev; 112 struct amdgpu_ring *ring = &mes->ring; 113 unsigned long flags; 114 signed long timeout = adev->usec_timeout; 115 116 if (amdgpu_emu_mode) { 117 timeout *= 100; 118 } else if (amdgpu_sriov_vf(adev)) { 119 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 120 timeout = 15 * 600 * 1000; 121 } 122 BUG_ON(size % 4 != 0); 123 124 spin_lock_irqsave(&mes->ring_lock, flags); 125 if (amdgpu_ring_alloc(ring, ndw)) { 126 spin_unlock_irqrestore(&mes->ring_lock, flags); 127 return -ENOMEM; 128 } 129 130 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 131 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 132 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 133 134 amdgpu_ring_write_multiple(ring, pkt, ndw); 135 amdgpu_ring_commit(ring); 136 spin_unlock_irqrestore(&mes->ring_lock, flags); 137 138 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 139 140 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 141 timeout); 142 if (r < 1) { 143 DRM_ERROR("MES failed to response msg=%d\n", 144 x_pkt->header.opcode); 145 146 while (halt_if_hws_hang) 147 schedule(); 148 149 return -ETIMEDOUT; 150 } 151 152 return 0; 153 } 154 155 static int convert_to_mes_queue_type(int queue_type) 156 { 157 if (queue_type == AMDGPU_RING_TYPE_GFX) 158 return MES_QUEUE_TYPE_GFX; 159 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 160 return MES_QUEUE_TYPE_COMPUTE; 161 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 162 return MES_QUEUE_TYPE_SDMA; 163 else 164 BUG(); 165 return -1; 166 } 167 168 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 169 struct mes_add_queue_input *input) 170 { 171 struct amdgpu_device *adev = mes->adev; 172 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 173 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 174 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 175 176 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 177 178 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 179 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 180 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 181 182 mes_add_queue_pkt.process_id = input->process_id; 183 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 184 mes_add_queue_pkt.process_va_start = input->process_va_start; 185 mes_add_queue_pkt.process_va_end = input->process_va_end; 186 mes_add_queue_pkt.process_quantum = input->process_quantum; 187 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 188 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 189 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 190 mes_add_queue_pkt.inprocess_gang_priority = 191 input->inprocess_gang_priority; 192 mes_add_queue_pkt.gang_global_priority_level = 193 input->gang_global_priority_level; 194 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 195 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 196 197 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 198 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 199 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 200 else 201 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 202 203 mes_add_queue_pkt.queue_type = 204 convert_to_mes_queue_type(input->queue_type); 205 mes_add_queue_pkt.paging = input->paging; 206 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 207 mes_add_queue_pkt.gws_base = input->gws_base; 208 mes_add_queue_pkt.gws_size = input->gws_size; 209 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 210 mes_add_queue_pkt.tma_addr = input->tma_addr; 211 mes_add_queue_pkt.trap_en = input->trap_en; 212 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 213 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 214 215 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 216 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 217 mes_add_queue_pkt.gds_size = input->queue_size; 218 219 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 220 221 return mes_v11_0_submit_pkt_and_poll_completion(mes, 222 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 223 offsetof(union MESAPI__ADD_QUEUE, api_status)); 224 } 225 226 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 227 struct mes_remove_queue_input *input) 228 { 229 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 230 231 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 232 233 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 234 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 235 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 236 237 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 238 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 239 240 return mes_v11_0_submit_pkt_and_poll_completion(mes, 241 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 242 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 243 } 244 245 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 246 struct mes_unmap_legacy_queue_input *input) 247 { 248 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 249 250 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 251 252 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 253 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 254 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 255 256 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 257 mes_remove_queue_pkt.gang_context_addr = 0; 258 259 mes_remove_queue_pkt.pipe_id = input->pipe_id; 260 mes_remove_queue_pkt.queue_id = input->queue_id; 261 262 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 263 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 264 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 265 mes_remove_queue_pkt.tf_data = 266 lower_32_bits(input->trail_fence_data); 267 } else { 268 mes_remove_queue_pkt.unmap_legacy_queue = 1; 269 mes_remove_queue_pkt.queue_type = 270 convert_to_mes_queue_type(input->queue_type); 271 } 272 273 return mes_v11_0_submit_pkt_and_poll_completion(mes, 274 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 275 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 276 } 277 278 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 279 struct mes_suspend_gang_input *input) 280 { 281 return 0; 282 } 283 284 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 285 struct mes_resume_gang_input *input) 286 { 287 return 0; 288 } 289 290 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 291 { 292 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 293 294 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 295 296 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 297 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 298 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 299 300 return mes_v11_0_submit_pkt_and_poll_completion(mes, 301 &mes_status_pkt, sizeof(mes_status_pkt), 302 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 303 } 304 305 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 306 struct mes_misc_op_input *input) 307 { 308 union MESAPI__MISC misc_pkt; 309 310 memset(&misc_pkt, 0, sizeof(misc_pkt)); 311 312 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 313 misc_pkt.header.opcode = MES_SCH_API_MISC; 314 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 315 316 switch (input->op) { 317 case MES_MISC_OP_READ_REG: 318 misc_pkt.opcode = MESAPI_MISC__READ_REG; 319 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 320 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 321 break; 322 case MES_MISC_OP_WRITE_REG: 323 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 324 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 325 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 326 break; 327 case MES_MISC_OP_WRM_REG_WAIT: 328 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 329 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 330 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 331 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 332 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 333 misc_pkt.wait_reg_mem.reg_offset2 = 0; 334 break; 335 case MES_MISC_OP_WRM_REG_WR_WAIT: 336 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 337 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 338 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 339 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 340 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 341 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 342 break; 343 case MES_MISC_OP_SET_SHADER_DEBUGGER: 344 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 345 misc_pkt.set_shader_debugger.process_context_addr = 346 input->set_shader_debugger.process_context_addr; 347 misc_pkt.set_shader_debugger.flags.u32all = 348 input->set_shader_debugger.flags.u32all; 349 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 350 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 351 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 352 input->set_shader_debugger.tcp_watch_cntl, 353 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 354 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 355 break; 356 default: 357 DRM_ERROR("unsupported misc op (%d) \n", input->op); 358 return -EINVAL; 359 } 360 361 return mes_v11_0_submit_pkt_and_poll_completion(mes, 362 &misc_pkt, sizeof(misc_pkt), 363 offsetof(union MESAPI__MISC, api_status)); 364 } 365 366 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 367 { 368 int i; 369 struct amdgpu_device *adev = mes->adev; 370 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 371 372 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 373 374 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 375 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 376 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 377 378 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 379 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 380 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 381 mes_set_hw_res_pkt.paging_vmid = 0; 382 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 383 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 384 mes->query_status_fence_gpu_addr; 385 386 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 387 mes_set_hw_res_pkt.compute_hqd_mask[i] = 388 mes->compute_hqd_mask[i]; 389 390 for (i = 0; i < MAX_GFX_PIPES; i++) 391 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 392 393 for (i = 0; i < MAX_SDMA_PIPES; i++) 394 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 395 396 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 397 mes_set_hw_res_pkt.aggregated_doorbells[i] = 398 mes->aggregated_doorbells[i]; 399 400 for (i = 0; i < 5; i++) { 401 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 402 mes_set_hw_res_pkt.mmhub_base[i] = 403 adev->reg_offset[MMHUB_HWIP][0][i]; 404 mes_set_hw_res_pkt.osssys_base[i] = 405 adev->reg_offset[OSSSYS_HWIP][0][i]; 406 } 407 408 mes_set_hw_res_pkt.disable_reset = 1; 409 mes_set_hw_res_pkt.disable_mes_log = 1; 410 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 411 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 412 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 413 mes_set_hw_res_pkt.oversubscription_timer = 50; 414 if (amdgpu_mes_log_enable) { 415 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 416 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 417 mes->event_log_gpu_addr; 418 } 419 420 return mes_v11_0_submit_pkt_and_poll_completion(mes, 421 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 422 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 423 } 424 425 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 426 { 427 int size = 128 * PAGE_SIZE; 428 int ret = 0; 429 struct amdgpu_device *adev = mes->adev; 430 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 431 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 432 433 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 434 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 435 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 436 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 437 438 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 439 AMDGPU_GEM_DOMAIN_VRAM, 440 &mes->resource_1, 441 &mes->resource_1_gpu_addr, 442 &mes->resource_1_addr); 443 if (ret) { 444 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret); 445 return ret; 446 } 447 448 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; 449 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; 450 return mes_v11_0_submit_pkt_and_poll_completion(mes, 451 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 452 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 453 } 454 455 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 456 .add_hw_queue = mes_v11_0_add_hw_queue, 457 .remove_hw_queue = mes_v11_0_remove_hw_queue, 458 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 459 .suspend_gang = mes_v11_0_suspend_gang, 460 .resume_gang = mes_v11_0_resume_gang, 461 .misc_op = mes_v11_0_misc_op, 462 }; 463 464 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 465 enum admgpu_mes_pipe pipe) 466 { 467 int r; 468 const struct mes_firmware_header_v1_0 *mes_hdr; 469 const __le32 *fw_data; 470 unsigned fw_size; 471 472 mes_hdr = (const struct mes_firmware_header_v1_0 *) 473 adev->mes.fw[pipe]->data; 474 475 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 476 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 477 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 478 479 r = amdgpu_bo_create_reserved(adev, fw_size, 480 PAGE_SIZE, 481 AMDGPU_GEM_DOMAIN_VRAM | 482 AMDGPU_GEM_DOMAIN_GTT, 483 &adev->mes.ucode_fw_obj[pipe], 484 &adev->mes.ucode_fw_gpu_addr[pipe], 485 (void **)&adev->mes.ucode_fw_ptr[pipe]); 486 if (r) { 487 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 488 return r; 489 } 490 491 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 492 493 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 494 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 495 496 return 0; 497 } 498 499 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 500 enum admgpu_mes_pipe pipe) 501 { 502 int r; 503 const struct mes_firmware_header_v1_0 *mes_hdr; 504 const __le32 *fw_data; 505 unsigned fw_size; 506 507 mes_hdr = (const struct mes_firmware_header_v1_0 *) 508 adev->mes.fw[pipe]->data; 509 510 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 511 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 512 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 513 514 if (fw_size > GFX_MES_DRAM_SIZE) { 515 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 516 pipe, fw_size, GFX_MES_DRAM_SIZE); 517 return -EINVAL; 518 } 519 520 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 521 64 * 1024, 522 AMDGPU_GEM_DOMAIN_VRAM | 523 AMDGPU_GEM_DOMAIN_GTT, 524 &adev->mes.data_fw_obj[pipe], 525 &adev->mes.data_fw_gpu_addr[pipe], 526 (void **)&adev->mes.data_fw_ptr[pipe]); 527 if (r) { 528 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 529 return r; 530 } 531 532 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 533 534 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 535 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 536 537 return 0; 538 } 539 540 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 541 enum admgpu_mes_pipe pipe) 542 { 543 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 544 &adev->mes.data_fw_gpu_addr[pipe], 545 (void **)&adev->mes.data_fw_ptr[pipe]); 546 547 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 548 &adev->mes.ucode_fw_gpu_addr[pipe], 549 (void **)&adev->mes.ucode_fw_ptr[pipe]); 550 } 551 552 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 553 { 554 uint64_t ucode_addr; 555 uint32_t pipe, data = 0; 556 557 if (enable) { 558 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 559 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 560 data = REG_SET_FIELD(data, CP_MES_CNTL, 561 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 562 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 563 564 mutex_lock(&adev->srbm_mutex); 565 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 566 if (!adev->enable_mes_kiq && 567 pipe == AMDGPU_MES_KIQ_PIPE) 568 continue; 569 570 soc21_grbm_select(adev, 3, pipe, 0, 0); 571 572 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 573 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 574 lower_32_bits(ucode_addr)); 575 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 576 upper_32_bits(ucode_addr)); 577 } 578 soc21_grbm_select(adev, 0, 0, 0, 0); 579 mutex_unlock(&adev->srbm_mutex); 580 581 /* unhalt MES and activate pipe0 */ 582 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 583 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 584 adev->enable_mes_kiq ? 1 : 0); 585 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 586 587 if (amdgpu_emu_mode) 588 msleep(100); 589 else 590 udelay(50); 591 } else { 592 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 593 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 594 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 595 data = REG_SET_FIELD(data, CP_MES_CNTL, 596 MES_INVALIDATE_ICACHE, 1); 597 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 598 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 599 adev->enable_mes_kiq ? 1 : 0); 600 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 601 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 602 } 603 } 604 605 /* This function is for backdoor MES firmware */ 606 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 607 enum admgpu_mes_pipe pipe, bool prime_icache) 608 { 609 int r; 610 uint32_t data; 611 uint64_t ucode_addr; 612 613 mes_v11_0_enable(adev, false); 614 615 if (!adev->mes.fw[pipe]) 616 return -EINVAL; 617 618 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 619 if (r) 620 return r; 621 622 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 623 if (r) { 624 mes_v11_0_free_ucode_buffers(adev, pipe); 625 return r; 626 } 627 628 mutex_lock(&adev->srbm_mutex); 629 /* me=3, pipe=0, queue=0 */ 630 soc21_grbm_select(adev, 3, pipe, 0, 0); 631 632 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 633 634 /* set ucode start address */ 635 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 636 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 637 lower_32_bits(ucode_addr)); 638 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 639 upper_32_bits(ucode_addr)); 640 641 /* set ucode fimrware address */ 642 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 643 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 644 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 645 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 646 647 /* set ucode instruction cache boundary to 2M-1 */ 648 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 649 650 /* set ucode data firmware address */ 651 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 652 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 653 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 654 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 655 656 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 657 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 658 659 if (prime_icache) { 660 /* invalidate ICACHE */ 661 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 662 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 663 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 664 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 665 666 /* prime the ICACHE. */ 667 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 668 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 669 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 670 } 671 672 soc21_grbm_select(adev, 0, 0, 0, 0); 673 mutex_unlock(&adev->srbm_mutex); 674 675 return 0; 676 } 677 678 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 679 enum admgpu_mes_pipe pipe) 680 { 681 int r; 682 u32 *eop; 683 684 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 685 AMDGPU_GEM_DOMAIN_GTT, 686 &adev->mes.eop_gpu_obj[pipe], 687 &adev->mes.eop_gpu_addr[pipe], 688 (void **)&eop); 689 if (r) { 690 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 691 return r; 692 } 693 694 memset(eop, 0, 695 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 696 697 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 698 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 699 700 return 0; 701 } 702 703 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 704 { 705 struct v11_compute_mqd *mqd = ring->mqd_ptr; 706 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 707 uint32_t tmp; 708 709 memset(mqd, 0, sizeof(*mqd)); 710 711 mqd->header = 0xC0310800; 712 mqd->compute_pipelinestat_enable = 0x00000001; 713 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 714 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 715 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 716 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 717 mqd->compute_misc_reserved = 0x00000007; 718 719 eop_base_addr = ring->eop_gpu_addr >> 8; 720 721 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 722 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 723 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 724 (order_base_2(MES_EOP_SIZE / 4) - 1)); 725 726 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 727 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 728 mqd->cp_hqd_eop_control = tmp; 729 730 /* disable the queue if it's active */ 731 ring->wptr = 0; 732 mqd->cp_hqd_pq_rptr = 0; 733 mqd->cp_hqd_pq_wptr_lo = 0; 734 mqd->cp_hqd_pq_wptr_hi = 0; 735 736 /* set the pointer to the MQD */ 737 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 738 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 739 740 /* set MQD vmid to 0 */ 741 tmp = regCP_MQD_CONTROL_DEFAULT; 742 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 743 mqd->cp_mqd_control = tmp; 744 745 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 746 hqd_gpu_addr = ring->gpu_addr >> 8; 747 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 748 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 749 750 /* set the wb address whether it's enabled or not */ 751 wb_gpu_addr = ring->rptr_gpu_addr; 752 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 753 mqd->cp_hqd_pq_rptr_report_addr_hi = 754 upper_32_bits(wb_gpu_addr) & 0xffff; 755 756 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 757 wb_gpu_addr = ring->wptr_gpu_addr; 758 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 759 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 760 761 /* set up the HQD, this is similar to CP_RB0_CNTL */ 762 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 763 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 764 (order_base_2(ring->ring_size / 4) - 1)); 765 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 766 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 767 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 768 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 769 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 770 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 771 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 772 mqd->cp_hqd_pq_control = tmp; 773 774 /* enable doorbell */ 775 tmp = 0; 776 if (ring->use_doorbell) { 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 778 DOORBELL_OFFSET, ring->doorbell_index); 779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 780 DOORBELL_EN, 1); 781 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 782 DOORBELL_SOURCE, 0); 783 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 784 DOORBELL_HIT, 0); 785 } else 786 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 787 DOORBELL_EN, 0); 788 mqd->cp_hqd_pq_doorbell_control = tmp; 789 790 mqd->cp_hqd_vmid = 0; 791 /* activate the queue */ 792 mqd->cp_hqd_active = 1; 793 794 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 795 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 796 PRELOAD_SIZE, 0x55); 797 mqd->cp_hqd_persistent_state = tmp; 798 799 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 800 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 801 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 802 803 amdgpu_device_flush_hdp(ring->adev, NULL); 804 return 0; 805 } 806 807 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 808 { 809 struct v11_compute_mqd *mqd = ring->mqd_ptr; 810 struct amdgpu_device *adev = ring->adev; 811 uint32_t data = 0; 812 813 mutex_lock(&adev->srbm_mutex); 814 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 815 816 /* set CP_HQD_VMID.VMID = 0. */ 817 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 818 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 819 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 820 821 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 822 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 823 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 824 DOORBELL_EN, 0); 825 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 826 827 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 828 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 829 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 830 831 /* set CP_MQD_CONTROL.VMID=0 */ 832 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 833 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 834 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 835 836 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 837 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 838 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 839 840 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 841 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 842 mqd->cp_hqd_pq_rptr_report_addr_lo); 843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 844 mqd->cp_hqd_pq_rptr_report_addr_hi); 845 846 /* set CP_HQD_PQ_CONTROL */ 847 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 848 849 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 850 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 851 mqd->cp_hqd_pq_wptr_poll_addr_lo); 852 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 853 mqd->cp_hqd_pq_wptr_poll_addr_hi); 854 855 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 856 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 857 mqd->cp_hqd_pq_doorbell_control); 858 859 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 860 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 861 862 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 863 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 864 865 soc21_grbm_select(adev, 0, 0, 0, 0); 866 mutex_unlock(&adev->srbm_mutex); 867 } 868 869 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 870 { 871 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 872 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 873 int r; 874 875 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 876 return -EINVAL; 877 878 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 879 if (r) { 880 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 881 return r; 882 } 883 884 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 885 886 return amdgpu_ring_test_helper(kiq_ring); 887 } 888 889 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 890 enum admgpu_mes_pipe pipe) 891 { 892 struct amdgpu_ring *ring; 893 int r; 894 895 if (pipe == AMDGPU_MES_KIQ_PIPE) 896 ring = &adev->gfx.kiq[0].ring; 897 else if (pipe == AMDGPU_MES_SCHED_PIPE) 898 ring = &adev->mes.ring; 899 else 900 BUG(); 901 902 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 903 (amdgpu_in_reset(adev) || adev->in_suspend)) { 904 *(ring->wptr_cpu_addr) = 0; 905 *(ring->rptr_cpu_addr) = 0; 906 amdgpu_ring_clear_ring(ring); 907 } 908 909 r = mes_v11_0_mqd_init(ring); 910 if (r) 911 return r; 912 913 if (pipe == AMDGPU_MES_SCHED_PIPE) { 914 r = mes_v11_0_kiq_enable_queue(adev); 915 if (r) 916 return r; 917 } else { 918 mes_v11_0_queue_init_register(ring); 919 } 920 921 /* get MES scheduler/KIQ versions */ 922 mutex_lock(&adev->srbm_mutex); 923 soc21_grbm_select(adev, 3, pipe, 0, 0); 924 925 if (pipe == AMDGPU_MES_SCHED_PIPE) 926 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 927 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 928 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 929 930 soc21_grbm_select(adev, 0, 0, 0, 0); 931 mutex_unlock(&adev->srbm_mutex); 932 933 return 0; 934 } 935 936 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 937 { 938 struct amdgpu_ring *ring; 939 940 ring = &adev->mes.ring; 941 942 ring->funcs = &mes_v11_0_ring_funcs; 943 944 ring->me = 3; 945 ring->pipe = 0; 946 ring->queue = 0; 947 948 ring->ring_obj = NULL; 949 ring->use_doorbell = true; 950 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 951 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 952 ring->no_scheduler = true; 953 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 954 955 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 956 AMDGPU_RING_PRIO_DEFAULT, NULL); 957 } 958 959 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 960 { 961 struct amdgpu_ring *ring; 962 963 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 964 965 ring = &adev->gfx.kiq[0].ring; 966 967 ring->me = 3; 968 ring->pipe = 1; 969 ring->queue = 0; 970 971 ring->adev = NULL; 972 ring->ring_obj = NULL; 973 ring->use_doorbell = true; 974 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 975 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 976 ring->no_scheduler = true; 977 sprintf(ring->name, "mes_kiq_%d.%d.%d", 978 ring->me, ring->pipe, ring->queue); 979 980 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 981 AMDGPU_RING_PRIO_DEFAULT, NULL); 982 } 983 984 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 985 enum admgpu_mes_pipe pipe) 986 { 987 int r, mqd_size = sizeof(struct v11_compute_mqd); 988 struct amdgpu_ring *ring; 989 990 if (pipe == AMDGPU_MES_KIQ_PIPE) 991 ring = &adev->gfx.kiq[0].ring; 992 else if (pipe == AMDGPU_MES_SCHED_PIPE) 993 ring = &adev->mes.ring; 994 else 995 BUG(); 996 997 if (ring->mqd_obj) 998 return 0; 999 1000 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1001 AMDGPU_GEM_DOMAIN_VRAM | 1002 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1003 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1004 if (r) { 1005 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1006 return r; 1007 } 1008 1009 memset(ring->mqd_ptr, 0, mqd_size); 1010 1011 /* prepare MQD backup */ 1012 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1013 if (!adev->mes.mqd_backup[pipe]) { 1014 dev_warn(adev->dev, 1015 "no memory to create MQD backup for ring %s\n", 1016 ring->name); 1017 return -ENOMEM; 1018 } 1019 1020 return 0; 1021 } 1022 1023 static int mes_v11_0_sw_init(void *handle) 1024 { 1025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1026 int pipe, r; 1027 1028 adev->mes.funcs = &mes_v11_0_funcs; 1029 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1030 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1031 1032 r = amdgpu_mes_init(adev); 1033 if (r) 1034 return r; 1035 1036 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1037 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1038 continue; 1039 1040 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1041 if (r) 1042 return r; 1043 1044 r = mes_v11_0_mqd_sw_init(adev, pipe); 1045 if (r) 1046 return r; 1047 } 1048 1049 if (adev->enable_mes_kiq) { 1050 r = mes_v11_0_kiq_ring_init(adev); 1051 if (r) 1052 return r; 1053 } 1054 1055 r = mes_v11_0_ring_init(adev); 1056 if (r) 1057 return r; 1058 1059 return 0; 1060 } 1061 1062 static int mes_v11_0_sw_fini(void *handle) 1063 { 1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1065 int pipe; 1066 1067 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1068 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1069 1070 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1071 kfree(adev->mes.mqd_backup[pipe]); 1072 1073 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1074 &adev->mes.eop_gpu_addr[pipe], 1075 NULL); 1076 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1077 } 1078 1079 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1080 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1081 &adev->gfx.kiq[0].ring.mqd_ptr); 1082 1083 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1084 &adev->mes.ring.mqd_gpu_addr, 1085 &adev->mes.ring.mqd_ptr); 1086 1087 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1088 amdgpu_ring_fini(&adev->mes.ring); 1089 1090 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1091 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1092 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1093 } 1094 1095 amdgpu_mes_fini(adev); 1096 return 0; 1097 } 1098 1099 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1100 { 1101 uint32_t data; 1102 int i; 1103 struct amdgpu_device *adev = ring->adev; 1104 1105 mutex_lock(&adev->srbm_mutex); 1106 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1107 1108 /* disable the queue if it's active */ 1109 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1110 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1111 for (i = 0; i < adev->usec_timeout; i++) { 1112 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1113 break; 1114 udelay(1); 1115 } 1116 } 1117 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1118 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1119 DOORBELL_EN, 0); 1120 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1121 DOORBELL_HIT, 1); 1122 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1123 1124 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1125 1126 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1127 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1128 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1129 1130 soc21_grbm_select(adev, 0, 0, 0, 0); 1131 mutex_unlock(&adev->srbm_mutex); 1132 } 1133 1134 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1135 { 1136 uint32_t tmp; 1137 struct amdgpu_device *adev = ring->adev; 1138 1139 /* tell RLC which is KIQ queue */ 1140 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1141 tmp &= 0xffffff00; 1142 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1143 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1144 tmp |= 0x80; 1145 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1146 } 1147 1148 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1149 { 1150 uint32_t tmp; 1151 1152 /* tell RLC which is KIQ dequeue */ 1153 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1154 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1155 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1156 } 1157 1158 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1159 { 1160 int r = 0; 1161 1162 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1163 1164 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1165 if (r) { 1166 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1167 return r; 1168 } 1169 1170 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1171 if (r) { 1172 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1173 return r; 1174 } 1175 1176 } 1177 1178 mes_v11_0_enable(adev, true); 1179 1180 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1181 1182 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1183 if (r) 1184 goto failure; 1185 1186 return r; 1187 1188 failure: 1189 mes_v11_0_hw_fini(adev); 1190 return r; 1191 } 1192 1193 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1194 { 1195 if (adev->mes.ring.sched.ready) { 1196 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1197 adev->mes.ring.sched.ready = false; 1198 } 1199 1200 if (amdgpu_sriov_vf(adev)) { 1201 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1202 mes_v11_0_kiq_clear(adev); 1203 } 1204 1205 mes_v11_0_enable(adev, false); 1206 1207 return 0; 1208 } 1209 1210 static int mes_v11_0_hw_init(void *handle) 1211 { 1212 int r; 1213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1214 1215 if (!adev->enable_mes_kiq) { 1216 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1217 r = mes_v11_0_load_microcode(adev, 1218 AMDGPU_MES_SCHED_PIPE, true); 1219 if (r) { 1220 DRM_ERROR("failed to MES fw, r=%d\n", r); 1221 return r; 1222 } 1223 } 1224 1225 mes_v11_0_enable(adev, true); 1226 } 1227 1228 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1229 if (r) 1230 goto failure; 1231 1232 r = mes_v11_0_set_hw_resources(&adev->mes); 1233 if (r) 1234 goto failure; 1235 1236 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1237 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1238 if (r) { 1239 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1240 goto failure; 1241 } 1242 } 1243 1244 r = mes_v11_0_query_sched_status(&adev->mes); 1245 if (r) { 1246 DRM_ERROR("MES is busy\n"); 1247 goto failure; 1248 } 1249 1250 /* 1251 * Disable KIQ ring usage from the driver once MES is enabled. 1252 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1253 * with MES enabled. 1254 */ 1255 adev->gfx.kiq[0].ring.sched.ready = false; 1256 adev->mes.ring.sched.ready = true; 1257 1258 return 0; 1259 1260 failure: 1261 mes_v11_0_hw_fini(adev); 1262 return r; 1263 } 1264 1265 static int mes_v11_0_hw_fini(void *handle) 1266 { 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 if (amdgpu_sriov_is_mes_info_enable(adev)) { 1269 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, 1270 &adev->mes.resource_1_addr); 1271 } 1272 return 0; 1273 } 1274 1275 static int mes_v11_0_suspend(void *handle) 1276 { 1277 int r; 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 1280 r = amdgpu_mes_suspend(adev); 1281 if (r) 1282 return r; 1283 1284 return mes_v11_0_hw_fini(adev); 1285 } 1286 1287 static int mes_v11_0_resume(void *handle) 1288 { 1289 int r; 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 r = mes_v11_0_hw_init(adev); 1293 if (r) 1294 return r; 1295 1296 return amdgpu_mes_resume(adev); 1297 } 1298 1299 static int mes_v11_0_early_init(void *handle) 1300 { 1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1302 int pipe, r; 1303 1304 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1305 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1306 continue; 1307 r = amdgpu_mes_init_microcode(adev, pipe); 1308 if (r) 1309 return r; 1310 } 1311 1312 return 0; 1313 } 1314 1315 static int mes_v11_0_late_init(void *handle) 1316 { 1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1318 1319 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1320 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1321 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3))) 1322 amdgpu_mes_self_test(adev); 1323 1324 return 0; 1325 } 1326 1327 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1328 .name = "mes_v11_0", 1329 .early_init = mes_v11_0_early_init, 1330 .late_init = mes_v11_0_late_init, 1331 .sw_init = mes_v11_0_sw_init, 1332 .sw_fini = mes_v11_0_sw_fini, 1333 .hw_init = mes_v11_0_hw_init, 1334 .hw_fini = mes_v11_0_hw_fini, 1335 .suspend = mes_v11_0_suspend, 1336 .resume = mes_v11_0_resume, 1337 }; 1338 1339 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1340 .type = AMD_IP_BLOCK_TYPE_MES, 1341 .major = 11, 1342 .minor = 0, 1343 .rev = 0, 1344 .funcs = &mes_v11_0_ip_funcs, 1345 }; 1346