1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 62 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 63 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 64 65 #define MES_EOP_SIZE 2048 66 #define GFX_MES_DRAM_SIZE 0x80000 67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 68 69 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 70 #define MES11_HUNG_HQD_INFO_OFFSET 4 71 72 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 73 { 74 struct amdgpu_device *adev = ring->adev; 75 76 if (ring->use_doorbell) { 77 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 78 ring->wptr); 79 WDOORBELL64(ring->doorbell_index, ring->wptr); 80 } else { 81 BUG(); 82 } 83 } 84 85 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 86 { 87 return *ring->rptr_cpu_addr; 88 } 89 90 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 91 { 92 u64 wptr; 93 94 if (ring->use_doorbell) 95 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 96 else 97 BUG(); 98 return wptr; 99 } 100 101 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 102 .type = AMDGPU_RING_TYPE_MES, 103 .align_mask = 1, 104 .nop = 0, 105 .support_64bit_ptrs = true, 106 .get_rptr = mes_v11_0_ring_get_rptr, 107 .get_wptr = mes_v11_0_ring_get_wptr, 108 .set_wptr = mes_v11_0_ring_set_wptr, 109 .insert_nop = amdgpu_ring_insert_nop, 110 }; 111 112 static const char *mes_v11_0_opcodes[] = { 113 "SET_HW_RSRC", 114 "SET_SCHEDULING_CONFIG", 115 "ADD_QUEUE", 116 "REMOVE_QUEUE", 117 "PERFORM_YIELD", 118 "SET_GANG_PRIORITY_LEVEL", 119 "SUSPEND", 120 "RESUME", 121 "RESET", 122 "SET_LOG_BUFFER", 123 "CHANGE_GANG_PRORITY", 124 "QUERY_SCHEDULER_STATUS", 125 "PROGRAM_GDS", 126 "SET_DEBUG_VMID", 127 "MISC", 128 "UPDATE_ROOT_PAGE_TABLE", 129 "AMD_LOG", 130 "unused", 131 "unused", 132 "SET_HW_RSRC_1", 133 }; 134 135 static const char *mes_v11_0_misc_opcodes[] = { 136 "WRITE_REG", 137 "INV_GART", 138 "QUERY_STATUS", 139 "READ_REG", 140 "WAIT_REG_MEM", 141 "SET_SHADER_DEBUGGER", 142 }; 143 144 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 145 { 146 const char *op_str = NULL; 147 148 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 149 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 150 151 return op_str; 152 } 153 154 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 155 { 156 const char *op_str = NULL; 157 158 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 159 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 160 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 161 162 return op_str; 163 } 164 165 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 166 void *pkt, int size, 167 int api_status_off) 168 { 169 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 170 signed long timeout = 2100000; /* 2100 ms */ 171 struct amdgpu_device *adev = mes->adev; 172 struct amdgpu_ring *ring = &mes->ring[0]; 173 struct MES_API_STATUS *api_status; 174 union MESAPI__MISC *x_pkt = pkt; 175 const char *op_str, *misc_op_str; 176 unsigned long flags; 177 u64 status_gpu_addr; 178 u32 seq, status_offset; 179 u64 *status_ptr; 180 signed long r; 181 int ret; 182 183 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 184 return -EINVAL; 185 186 if (amdgpu_emu_mode) { 187 timeout *= 100; 188 } else if (amdgpu_sriov_vf(adev)) { 189 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 190 timeout = 15 * 600 * 1000; 191 } 192 193 ret = amdgpu_device_wb_get(adev, &status_offset); 194 if (ret) 195 return ret; 196 197 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 198 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 199 *status_ptr = 0; 200 201 spin_lock_irqsave(&mes->ring_lock[0], flags); 202 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 203 if (r) 204 goto error_unlock_free; 205 206 seq = ++ring->fence_drv.sync_seq; 207 r = amdgpu_fence_wait_polling(ring, 208 seq - ring->fence_drv.num_fences_mask, 209 timeout); 210 if (r < 1) 211 goto error_undo; 212 213 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 214 api_status->api_completion_fence_addr = status_gpu_addr; 215 api_status->api_completion_fence_value = 1; 216 217 amdgpu_ring_write_multiple(ring, pkt, size / 4); 218 219 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 220 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 221 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 222 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 223 mes_status_pkt.api_status.api_completion_fence_addr = 224 ring->fence_drv.gpu_addr; 225 mes_status_pkt.api_status.api_completion_fence_value = seq; 226 227 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 228 sizeof(mes_status_pkt) / 4); 229 230 amdgpu_ring_commit(ring); 231 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 232 233 op_str = mes_v11_0_get_op_string(x_pkt); 234 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 235 236 if (misc_op_str) 237 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 238 misc_op_str); 239 else if (op_str) 240 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 241 else 242 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 243 x_pkt->header.opcode); 244 245 r = amdgpu_fence_wait_polling(ring, seq, timeout); 246 if (r < 1 || !*status_ptr) { 247 248 if (misc_op_str) 249 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 250 op_str, misc_op_str); 251 else if (op_str) 252 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 253 op_str); 254 else 255 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 256 x_pkt->header.opcode); 257 258 while (halt_if_hws_hang) 259 schedule(); 260 261 r = -ETIMEDOUT; 262 goto error_wb_free; 263 } 264 265 amdgpu_device_wb_free(adev, status_offset); 266 return 0; 267 268 error_undo: 269 dev_err(adev->dev, "MES ring buffer is full.\n"); 270 amdgpu_ring_undo(ring); 271 272 error_unlock_free: 273 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 274 275 error_wb_free: 276 amdgpu_device_wb_free(adev, status_offset); 277 return r; 278 } 279 280 static int convert_to_mes_queue_type(int queue_type) 281 { 282 if (queue_type == AMDGPU_RING_TYPE_GFX) 283 return MES_QUEUE_TYPE_GFX; 284 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 285 return MES_QUEUE_TYPE_COMPUTE; 286 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 287 return MES_QUEUE_TYPE_SDMA; 288 else 289 BUG(); 290 return -1; 291 } 292 293 static int convert_to_mes_priority_level(int priority_level) 294 { 295 switch (priority_level) { 296 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 297 return AMD_PRIORITY_LEVEL_LOW; 298 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 299 default: 300 return AMD_PRIORITY_LEVEL_NORMAL; 301 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 302 return AMD_PRIORITY_LEVEL_MEDIUM; 303 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 304 return AMD_PRIORITY_LEVEL_HIGH; 305 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 306 return AMD_PRIORITY_LEVEL_REALTIME; 307 } 308 } 309 310 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 311 struct mes_add_queue_input *input) 312 { 313 struct amdgpu_device *adev = mes->adev; 314 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 315 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 316 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 317 318 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 319 320 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 321 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 322 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 323 324 mes_add_queue_pkt.process_id = input->process_id; 325 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 326 mes_add_queue_pkt.process_va_start = input->process_va_start; 327 mes_add_queue_pkt.process_va_end = input->process_va_end; 328 mes_add_queue_pkt.process_quantum = input->process_quantum; 329 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 330 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 331 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 332 mes_add_queue_pkt.inprocess_gang_priority = 333 convert_to_mes_priority_level(input->inprocess_gang_priority); 334 mes_add_queue_pkt.gang_global_priority_level = 335 convert_to_mes_priority_level(input->gang_global_priority_level); 336 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 337 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 338 339 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 340 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 341 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 342 else 343 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 344 345 mes_add_queue_pkt.queue_type = 346 convert_to_mes_queue_type(input->queue_type); 347 mes_add_queue_pkt.paging = input->paging; 348 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 349 mes_add_queue_pkt.gws_base = input->gws_base; 350 mes_add_queue_pkt.gws_size = input->gws_size; 351 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 352 mes_add_queue_pkt.tma_addr = input->tma_addr; 353 mes_add_queue_pkt.trap_en = input->trap_en; 354 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 355 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 356 357 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 358 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 359 mes_add_queue_pkt.gds_size = input->queue_size; 360 361 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 362 363 return mes_v11_0_submit_pkt_and_poll_completion(mes, 364 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 365 offsetof(union MESAPI__ADD_QUEUE, api_status)); 366 } 367 368 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 369 struct mes_remove_queue_input *input) 370 { 371 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 372 373 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 374 375 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 376 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 377 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 378 379 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 380 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 381 382 return mes_v11_0_submit_pkt_and_poll_completion(mes, 383 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 384 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 385 } 386 387 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 388 uint32_t me_id, uint32_t pipe_id, 389 uint32_t queue_id, uint32_t vmid) 390 { 391 struct amdgpu_device *adev = mes->adev; 392 uint32_t value, reg; 393 int i, r = 0; 394 395 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 396 397 if (queue_type == AMDGPU_RING_TYPE_GFX) { 398 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 399 me_id, pipe_id, queue_id, vmid); 400 401 mutex_lock(&adev->gfx.reset_sem_mutex); 402 gfx_v11_0_request_gfx_index_mutex(adev, true); 403 /* all se allow writes */ 404 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 405 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 406 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 407 if (pipe_id == 0) 408 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 409 else 410 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 411 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 412 gfx_v11_0_request_gfx_index_mutex(adev, false); 413 mutex_unlock(&adev->gfx.reset_sem_mutex); 414 415 mutex_lock(&adev->srbm_mutex); 416 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 417 /* wait till dequeue take effects */ 418 for (i = 0; i < adev->usec_timeout; i++) { 419 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 420 break; 421 udelay(1); 422 } 423 if (i >= adev->usec_timeout) { 424 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 425 r = -ETIMEDOUT; 426 } 427 428 soc21_grbm_select(adev, 0, 0, 0, 0); 429 mutex_unlock(&adev->srbm_mutex); 430 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 431 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 432 me_id, pipe_id, queue_id); 433 mutex_lock(&adev->srbm_mutex); 434 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 435 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 436 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 437 438 /* wait till dequeue take effects */ 439 for (i = 0; i < adev->usec_timeout; i++) { 440 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 441 break; 442 udelay(1); 443 } 444 if (i >= adev->usec_timeout) { 445 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 446 r = -ETIMEDOUT; 447 } 448 soc21_grbm_select(adev, 0, 0, 0, 0); 449 mutex_unlock(&adev->srbm_mutex); 450 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 451 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 452 me_id, pipe_id, queue_id); 453 switch (me_id) { 454 case 1: 455 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 456 break; 457 case 0: 458 default: 459 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 460 break; 461 } 462 463 value = 1 << queue_id; 464 WREG32(reg, value); 465 /* wait for queue reset done */ 466 for (i = 0; i < adev->usec_timeout; i++) { 467 if (!(RREG32(reg) & value)) 468 break; 469 udelay(1); 470 } 471 if (i >= adev->usec_timeout) { 472 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 473 r = -ETIMEDOUT; 474 } 475 } 476 477 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 478 return r; 479 } 480 481 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 482 struct mes_map_legacy_queue_input *input) 483 { 484 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 485 486 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 487 488 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 489 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 490 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 491 492 mes_add_queue_pkt.pipe_id = input->pipe_id; 493 mes_add_queue_pkt.queue_id = input->queue_id; 494 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 495 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 496 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 497 mes_add_queue_pkt.queue_type = 498 convert_to_mes_queue_type(input->queue_type); 499 mes_add_queue_pkt.map_legacy_kq = 1; 500 501 return mes_v11_0_submit_pkt_and_poll_completion(mes, 502 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 503 offsetof(union MESAPI__ADD_QUEUE, api_status)); 504 } 505 506 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 507 struct mes_unmap_legacy_queue_input *input) 508 { 509 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 510 511 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 512 513 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 514 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 515 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 516 517 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 518 mes_remove_queue_pkt.gang_context_addr = 0; 519 520 mes_remove_queue_pkt.pipe_id = input->pipe_id; 521 mes_remove_queue_pkt.queue_id = input->queue_id; 522 523 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 524 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 525 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 526 mes_remove_queue_pkt.tf_data = 527 lower_32_bits(input->trail_fence_data); 528 } else { 529 mes_remove_queue_pkt.unmap_legacy_queue = 1; 530 mes_remove_queue_pkt.queue_type = 531 convert_to_mes_queue_type(input->queue_type); 532 } 533 534 return mes_v11_0_submit_pkt_and_poll_completion(mes, 535 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 536 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 537 } 538 539 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 540 struct mes_suspend_gang_input *input) 541 { 542 union MESAPI__SUSPEND mes_suspend_gang_pkt; 543 544 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 545 546 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 547 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 548 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 549 550 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 551 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 552 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 553 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 554 555 return mes_v11_0_submit_pkt_and_poll_completion(mes, 556 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 557 offsetof(union MESAPI__SUSPEND, api_status)); 558 } 559 560 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 561 struct mes_resume_gang_input *input) 562 { 563 union MESAPI__RESUME mes_resume_gang_pkt; 564 565 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 566 567 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 568 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 569 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 570 571 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 572 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 573 574 return mes_v11_0_submit_pkt_and_poll_completion(mes, 575 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 576 offsetof(union MESAPI__RESUME, api_status)); 577 } 578 579 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 580 { 581 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 582 583 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 584 585 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 586 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 587 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 588 589 return mes_v11_0_submit_pkt_and_poll_completion(mes, 590 &mes_status_pkt, sizeof(mes_status_pkt), 591 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 592 } 593 594 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 595 struct mes_misc_op_input *input) 596 { 597 union MESAPI__MISC misc_pkt; 598 599 memset(&misc_pkt, 0, sizeof(misc_pkt)); 600 601 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 602 misc_pkt.header.opcode = MES_SCH_API_MISC; 603 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 604 605 switch (input->op) { 606 case MES_MISC_OP_READ_REG: 607 misc_pkt.opcode = MESAPI_MISC__READ_REG; 608 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 609 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 610 break; 611 case MES_MISC_OP_WRITE_REG: 612 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 613 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 614 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 615 break; 616 case MES_MISC_OP_WRM_REG_WAIT: 617 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 618 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 619 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 620 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 621 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 622 misc_pkt.wait_reg_mem.reg_offset2 = 0; 623 break; 624 case MES_MISC_OP_WRM_REG_WR_WAIT: 625 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 626 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 627 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 628 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 629 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 630 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 631 break; 632 case MES_MISC_OP_SET_SHADER_DEBUGGER: 633 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 634 misc_pkt.set_shader_debugger.process_context_addr = 635 input->set_shader_debugger.process_context_addr; 636 misc_pkt.set_shader_debugger.flags.u32all = 637 input->set_shader_debugger.flags.u32all; 638 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 639 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 640 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 641 input->set_shader_debugger.tcp_watch_cntl, 642 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 643 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 644 break; 645 case MES_MISC_OP_CHANGE_CONFIG: 646 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 647 dev_warn_once(mes->adev->dev, 648 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 649 return 0; 650 } 651 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 652 misc_pkt.change_config.opcode = 653 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 654 misc_pkt.change_config.option.bits.limit_single_process = 655 input->change_config.option.limit_single_process; 656 break; 657 658 default: 659 DRM_ERROR("unsupported misc op (%d) \n", input->op); 660 return -EINVAL; 661 } 662 663 return mes_v11_0_submit_pkt_and_poll_completion(mes, 664 &misc_pkt, sizeof(misc_pkt), 665 offsetof(union MESAPI__MISC, api_status)); 666 } 667 668 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 669 { 670 int i; 671 struct amdgpu_device *adev = mes->adev; 672 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 673 674 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 675 676 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 677 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 678 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 679 680 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 681 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 682 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 683 mes_set_hw_res_pkt.paging_vmid = 0; 684 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 685 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 686 mes->query_status_fence_gpu_addr[0]; 687 688 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 689 mes_set_hw_res_pkt.compute_hqd_mask[i] = 690 mes->compute_hqd_mask[i]; 691 692 for (i = 0; i < MAX_GFX_PIPES; i++) 693 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 694 mes->gfx_hqd_mask[i]; 695 696 for (i = 0; i < MAX_SDMA_PIPES; i++) 697 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 698 699 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 700 mes_set_hw_res_pkt.aggregated_doorbells[i] = 701 mes->aggregated_doorbells[i]; 702 703 for (i = 0; i < 5; i++) { 704 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 705 mes_set_hw_res_pkt.mmhub_base[i] = 706 adev->reg_offset[MMHUB_HWIP][0][i]; 707 mes_set_hw_res_pkt.osssys_base[i] = 708 adev->reg_offset[OSSSYS_HWIP][0][i]; 709 } 710 711 mes_set_hw_res_pkt.disable_reset = 1; 712 mes_set_hw_res_pkt.disable_mes_log = 1; 713 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 714 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 715 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 716 mes_set_hw_res_pkt.oversubscription_timer = 50; 717 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) 718 mes_set_hw_res_pkt.enable_lr_compute_wa = 1; 719 else 720 dev_info_once(mes->adev->dev, 721 "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); 722 723 if (amdgpu_mes_log_enable) { 724 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 725 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 726 mes->event_log_gpu_addr; 727 } 728 729 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 730 mes_set_hw_res_pkt.limit_single_process = 1; 731 732 return mes_v11_0_submit_pkt_and_poll_completion(mes, 733 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 734 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 735 } 736 737 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 738 { 739 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 740 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 741 742 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 743 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 744 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 745 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 746 747 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 748 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 749 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 750 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 751 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 752 } 753 754 return mes_v11_0_submit_pkt_and_poll_completion(mes, 755 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 756 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 757 } 758 759 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 760 struct mes_reset_queue_input *input) 761 { 762 union MESAPI__RESET mes_reset_queue_pkt; 763 764 if (input->use_mmio) 765 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 766 input->me_id, input->pipe_id, 767 input->queue_id, input->vmid); 768 769 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 770 771 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 772 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 773 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 774 775 mes_reset_queue_pkt.queue_type = 776 convert_to_mes_queue_type(input->queue_type); 777 778 if (input->legacy_gfx) { 779 mes_reset_queue_pkt.reset_legacy_gfx = 1; 780 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 781 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 782 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 783 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 784 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 785 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 786 } else { 787 mes_reset_queue_pkt.reset_queue_only = 1; 788 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 789 } 790 791 return mes_v11_0_submit_pkt_and_poll_completion(mes, 792 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 793 offsetof(union MESAPI__RESET, api_status)); 794 } 795 796 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 797 struct mes_detect_and_reset_queue_input *input) 798 { 799 union MESAPI__RESET mes_reset_queue_pkt; 800 801 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 802 803 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 804 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 805 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 806 807 mes_reset_queue_pkt.queue_type = 808 convert_to_mes_queue_type(input->queue_type); 809 mes_reset_queue_pkt.doorbell_offset_addr = 810 mes->hung_queue_db_array_gpu_addr; 811 812 if (input->detect_only) 813 mes_reset_queue_pkt.hang_detect_only = 1; 814 else 815 mes_reset_queue_pkt.hang_detect_then_reset = 1; 816 817 return mes_v11_0_submit_pkt_and_poll_completion(mes, 818 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 819 offsetof(union MESAPI__RESET, api_status)); 820 } 821 822 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 823 .add_hw_queue = mes_v11_0_add_hw_queue, 824 .remove_hw_queue = mes_v11_0_remove_hw_queue, 825 .map_legacy_queue = mes_v11_0_map_legacy_queue, 826 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 827 .suspend_gang = mes_v11_0_suspend_gang, 828 .resume_gang = mes_v11_0_resume_gang, 829 .misc_op = mes_v11_0_misc_op, 830 .reset_hw_queue = mes_v11_0_reset_hw_queue, 831 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 832 }; 833 834 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 835 enum amdgpu_mes_pipe pipe) 836 { 837 int r; 838 const struct mes_firmware_header_v1_0 *mes_hdr; 839 const __le32 *fw_data; 840 unsigned fw_size; 841 842 mes_hdr = (const struct mes_firmware_header_v1_0 *) 843 adev->mes.fw[pipe]->data; 844 845 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 846 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 847 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 848 849 r = amdgpu_bo_create_reserved(adev, fw_size, 850 PAGE_SIZE, 851 AMDGPU_GEM_DOMAIN_VRAM | 852 AMDGPU_GEM_DOMAIN_GTT, 853 &adev->mes.ucode_fw_obj[pipe], 854 &adev->mes.ucode_fw_gpu_addr[pipe], 855 (void **)&adev->mes.ucode_fw_ptr[pipe]); 856 if (r) { 857 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 858 return r; 859 } 860 861 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 862 863 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 864 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 865 866 return 0; 867 } 868 869 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 870 enum amdgpu_mes_pipe pipe) 871 { 872 int r; 873 const struct mes_firmware_header_v1_0 *mes_hdr; 874 const __le32 *fw_data; 875 unsigned fw_size; 876 877 mes_hdr = (const struct mes_firmware_header_v1_0 *) 878 adev->mes.fw[pipe]->data; 879 880 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 881 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 882 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 883 884 if (fw_size > GFX_MES_DRAM_SIZE) { 885 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 886 pipe, fw_size, GFX_MES_DRAM_SIZE); 887 return -EINVAL; 888 } 889 890 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 891 64 * 1024, 892 AMDGPU_GEM_DOMAIN_VRAM | 893 AMDGPU_GEM_DOMAIN_GTT, 894 &adev->mes.data_fw_obj[pipe], 895 &adev->mes.data_fw_gpu_addr[pipe], 896 (void **)&adev->mes.data_fw_ptr[pipe]); 897 if (r) { 898 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 899 return r; 900 } 901 902 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 903 904 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 905 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 906 907 return 0; 908 } 909 910 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 911 enum amdgpu_mes_pipe pipe) 912 { 913 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 914 &adev->mes.data_fw_gpu_addr[pipe], 915 (void **)&adev->mes.data_fw_ptr[pipe]); 916 917 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 918 &adev->mes.ucode_fw_gpu_addr[pipe], 919 (void **)&adev->mes.ucode_fw_ptr[pipe]); 920 } 921 922 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 923 { 924 int pipe; 925 926 /* return early if we have already fetched these */ 927 if (adev->mes.sched_version && adev->mes.kiq_version) 928 return; 929 930 /* get MES scheduler/KIQ versions */ 931 mutex_lock(&adev->srbm_mutex); 932 933 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 934 soc21_grbm_select(adev, 3, pipe, 0, 0); 935 936 if (pipe == AMDGPU_MES_SCHED_PIPE) 937 adev->mes.sched_version = 938 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 939 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 940 adev->mes.kiq_version = 941 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 942 } 943 944 soc21_grbm_select(adev, 0, 0, 0, 0); 945 mutex_unlock(&adev->srbm_mutex); 946 } 947 948 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 949 { 950 uint64_t ucode_addr; 951 uint32_t pipe, data = 0; 952 953 if (enable) { 954 if (amdgpu_mes_log_enable) { 955 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 956 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 957 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 958 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 959 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 960 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 961 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 962 } 963 964 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 965 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 966 data = REG_SET_FIELD(data, CP_MES_CNTL, 967 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 968 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 969 970 mutex_lock(&adev->srbm_mutex); 971 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 972 if (!adev->enable_mes_kiq && 973 pipe == AMDGPU_MES_KIQ_PIPE) 974 continue; 975 976 soc21_grbm_select(adev, 3, pipe, 0, 0); 977 978 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 979 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 980 lower_32_bits(ucode_addr)); 981 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 982 upper_32_bits(ucode_addr)); 983 } 984 soc21_grbm_select(adev, 0, 0, 0, 0); 985 mutex_unlock(&adev->srbm_mutex); 986 987 /* unhalt MES and activate pipe0 */ 988 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 989 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 990 adev->enable_mes_kiq ? 1 : 0); 991 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 992 993 if (amdgpu_emu_mode) 994 msleep(100); 995 else 996 udelay(500); 997 } else { 998 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 999 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1000 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1001 data = REG_SET_FIELD(data, CP_MES_CNTL, 1002 MES_INVALIDATE_ICACHE, 1); 1003 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1004 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1005 adev->enable_mes_kiq ? 1 : 0); 1006 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1007 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1008 } 1009 } 1010 1011 /* This function is for backdoor MES firmware */ 1012 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1013 enum amdgpu_mes_pipe pipe, bool prime_icache) 1014 { 1015 int r; 1016 uint32_t data; 1017 uint64_t ucode_addr; 1018 1019 mes_v11_0_enable(adev, false); 1020 1021 if (!adev->mes.fw[pipe]) 1022 return -EINVAL; 1023 1024 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1025 if (r) 1026 return r; 1027 1028 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1029 if (r) { 1030 mes_v11_0_free_ucode_buffers(adev, pipe); 1031 return r; 1032 } 1033 1034 mutex_lock(&adev->srbm_mutex); 1035 /* me=3, pipe=0, queue=0 */ 1036 soc21_grbm_select(adev, 3, pipe, 0, 0); 1037 1038 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1039 1040 /* set ucode start address */ 1041 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1042 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1043 lower_32_bits(ucode_addr)); 1044 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1045 upper_32_bits(ucode_addr)); 1046 1047 /* set ucode fimrware address */ 1048 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1049 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1050 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1051 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1052 1053 /* set ucode instruction cache boundary to 2M-1 */ 1054 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1055 1056 /* set ucode data firmware address */ 1057 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1058 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1059 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1060 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1061 1062 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1063 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1064 1065 if (prime_icache) { 1066 /* invalidate ICACHE */ 1067 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1068 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1069 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1070 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1071 1072 /* prime the ICACHE. */ 1073 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1074 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1075 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1076 } 1077 1078 soc21_grbm_select(adev, 0, 0, 0, 0); 1079 mutex_unlock(&adev->srbm_mutex); 1080 1081 return 0; 1082 } 1083 1084 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1085 enum amdgpu_mes_pipe pipe) 1086 { 1087 int r; 1088 u32 *eop; 1089 1090 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1091 AMDGPU_GEM_DOMAIN_GTT, 1092 &adev->mes.eop_gpu_obj[pipe], 1093 &adev->mes.eop_gpu_addr[pipe], 1094 (void **)&eop); 1095 if (r) { 1096 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1097 return r; 1098 } 1099 1100 memset(eop, 0, 1101 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1102 1103 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1104 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1105 1106 return 0; 1107 } 1108 1109 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1110 { 1111 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1112 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1113 uint32_t tmp; 1114 1115 memset(mqd, 0, sizeof(*mqd)); 1116 1117 mqd->header = 0xC0310800; 1118 mqd->compute_pipelinestat_enable = 0x00000001; 1119 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1120 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1121 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1122 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1123 mqd->compute_misc_reserved = 0x00000007; 1124 1125 eop_base_addr = ring->eop_gpu_addr >> 8; 1126 1127 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1128 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1129 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1130 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1131 1132 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1133 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1134 mqd->cp_hqd_eop_control = tmp; 1135 1136 /* disable the queue if it's active */ 1137 ring->wptr = 0; 1138 mqd->cp_hqd_pq_rptr = 0; 1139 mqd->cp_hqd_pq_wptr_lo = 0; 1140 mqd->cp_hqd_pq_wptr_hi = 0; 1141 1142 /* set the pointer to the MQD */ 1143 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1144 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1145 1146 /* set MQD vmid to 0 */ 1147 tmp = regCP_MQD_CONTROL_DEFAULT; 1148 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1149 mqd->cp_mqd_control = tmp; 1150 1151 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1152 hqd_gpu_addr = ring->gpu_addr >> 8; 1153 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1154 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1155 1156 /* set the wb address whether it's enabled or not */ 1157 wb_gpu_addr = ring->rptr_gpu_addr; 1158 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1159 mqd->cp_hqd_pq_rptr_report_addr_hi = 1160 upper_32_bits(wb_gpu_addr) & 0xffff; 1161 1162 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1163 wb_gpu_addr = ring->wptr_gpu_addr; 1164 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1165 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1166 1167 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1168 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1169 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1170 (order_base_2(ring->ring_size / 4) - 1)); 1171 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1172 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1173 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1175 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1178 mqd->cp_hqd_pq_control = tmp; 1179 1180 /* enable doorbell */ 1181 tmp = 0; 1182 if (ring->use_doorbell) { 1183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1184 DOORBELL_OFFSET, ring->doorbell_index); 1185 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1186 DOORBELL_EN, 1); 1187 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1188 DOORBELL_SOURCE, 0); 1189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1190 DOORBELL_HIT, 0); 1191 } else 1192 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1193 DOORBELL_EN, 0); 1194 mqd->cp_hqd_pq_doorbell_control = tmp; 1195 1196 mqd->cp_hqd_vmid = 0; 1197 /* activate the queue */ 1198 mqd->cp_hqd_active = 1; 1199 1200 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1201 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1202 PRELOAD_SIZE, 0x55); 1203 mqd->cp_hqd_persistent_state = tmp; 1204 1205 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1206 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1207 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1208 1209 amdgpu_device_flush_hdp(ring->adev, NULL); 1210 return 0; 1211 } 1212 1213 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1214 { 1215 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1216 struct amdgpu_device *adev = ring->adev; 1217 uint32_t data = 0; 1218 1219 mutex_lock(&adev->srbm_mutex); 1220 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1221 1222 /* set CP_HQD_VMID.VMID = 0. */ 1223 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1224 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1225 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1226 1227 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1228 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1229 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1230 DOORBELL_EN, 0); 1231 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1232 1233 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1234 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1235 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1236 1237 /* set CP_MQD_CONTROL.VMID=0 */ 1238 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1239 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1240 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1241 1242 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1243 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1244 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1245 1246 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1247 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1248 mqd->cp_hqd_pq_rptr_report_addr_lo); 1249 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1250 mqd->cp_hqd_pq_rptr_report_addr_hi); 1251 1252 /* set CP_HQD_PQ_CONTROL */ 1253 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1254 1255 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1256 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1257 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1258 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1259 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1260 1261 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1262 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1263 mqd->cp_hqd_pq_doorbell_control); 1264 1265 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1266 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1267 1268 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1269 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1270 1271 soc21_grbm_select(adev, 0, 0, 0, 0); 1272 mutex_unlock(&adev->srbm_mutex); 1273 } 1274 1275 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1276 { 1277 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1278 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1279 int r; 1280 1281 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1282 return -EINVAL; 1283 1284 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1285 if (r) { 1286 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1287 return r; 1288 } 1289 1290 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1291 1292 return amdgpu_ring_test_helper(kiq_ring); 1293 } 1294 1295 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1296 enum amdgpu_mes_pipe pipe) 1297 { 1298 struct amdgpu_ring *ring; 1299 int r; 1300 1301 if (pipe == AMDGPU_MES_KIQ_PIPE) 1302 ring = &adev->gfx.kiq[0].ring; 1303 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1304 ring = &adev->mes.ring[0]; 1305 else 1306 BUG(); 1307 1308 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1309 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1310 *(ring->wptr_cpu_addr) = 0; 1311 *(ring->rptr_cpu_addr) = 0; 1312 amdgpu_ring_clear_ring(ring); 1313 } 1314 1315 r = mes_v11_0_mqd_init(ring); 1316 if (r) 1317 return r; 1318 1319 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1320 r = mes_v11_0_kiq_enable_queue(adev); 1321 if (r) 1322 return r; 1323 } else { 1324 mes_v11_0_queue_init_register(ring); 1325 } 1326 1327 return 0; 1328 } 1329 1330 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1331 { 1332 struct amdgpu_ring *ring; 1333 1334 ring = &adev->mes.ring[0]; 1335 1336 ring->funcs = &mes_v11_0_ring_funcs; 1337 1338 ring->me = 3; 1339 ring->pipe = 0; 1340 ring->queue = 0; 1341 1342 ring->ring_obj = NULL; 1343 ring->use_doorbell = true; 1344 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1345 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1346 ring->no_scheduler = true; 1347 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1348 1349 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1350 AMDGPU_RING_PRIO_DEFAULT, NULL); 1351 } 1352 1353 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1354 { 1355 struct amdgpu_ring *ring; 1356 1357 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1358 1359 ring = &adev->gfx.kiq[0].ring; 1360 1361 ring->me = 3; 1362 ring->pipe = 1; 1363 ring->queue = 0; 1364 1365 ring->adev = NULL; 1366 ring->ring_obj = NULL; 1367 ring->use_doorbell = true; 1368 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1369 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1370 ring->no_scheduler = true; 1371 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1372 ring->me, ring->pipe, ring->queue); 1373 1374 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1375 AMDGPU_RING_PRIO_DEFAULT, NULL); 1376 } 1377 1378 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1379 enum amdgpu_mes_pipe pipe) 1380 { 1381 int r, mqd_size = sizeof(struct v11_compute_mqd); 1382 struct amdgpu_ring *ring; 1383 1384 if (pipe == AMDGPU_MES_KIQ_PIPE) 1385 ring = &adev->gfx.kiq[0].ring; 1386 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1387 ring = &adev->mes.ring[0]; 1388 else 1389 BUG(); 1390 1391 if (ring->mqd_obj) 1392 return 0; 1393 1394 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1395 AMDGPU_GEM_DOMAIN_VRAM | 1396 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1397 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1398 if (r) { 1399 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1400 return r; 1401 } 1402 1403 memset(ring->mqd_ptr, 0, mqd_size); 1404 1405 /* prepare MQD backup */ 1406 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1407 if (!adev->mes.mqd_backup[pipe]) { 1408 dev_warn(adev->dev, 1409 "no memory to create MQD backup for ring %s\n", 1410 ring->name); 1411 return -ENOMEM; 1412 } 1413 1414 return 0; 1415 } 1416 1417 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1418 { 1419 struct amdgpu_device *adev = ip_block->adev; 1420 int pipe, r, bo_size; 1421 1422 adev->mes.funcs = &mes_v11_0_funcs; 1423 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1424 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1425 1426 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1427 1428 r = amdgpu_mes_init(adev); 1429 if (r) 1430 return r; 1431 1432 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1433 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1434 continue; 1435 1436 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1437 if (r) 1438 return r; 1439 1440 r = mes_v11_0_mqd_sw_init(adev, pipe); 1441 if (r) 1442 return r; 1443 } 1444 1445 if (adev->enable_mes_kiq) { 1446 r = mes_v11_0_kiq_ring_init(adev); 1447 if (r) 1448 return r; 1449 } 1450 1451 r = mes_v11_0_ring_init(adev); 1452 if (r) 1453 return r; 1454 1455 bo_size = AMDGPU_GPU_PAGE_SIZE; 1456 if (amdgpu_sriov_is_mes_info_enable(adev)) 1457 bo_size += MES11_HW_RESOURCE_1_SIZE; 1458 1459 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1460 r = amdgpu_bo_create_kernel(adev, 1461 bo_size, 1462 PAGE_SIZE, 1463 AMDGPU_GEM_DOMAIN_VRAM, 1464 &adev->mes.resource_1[0], 1465 &adev->mes.resource_1_gpu_addr[0], 1466 &adev->mes.resource_1_addr[0]); 1467 if (r) { 1468 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1469 return r; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1476 { 1477 struct amdgpu_device *adev = ip_block->adev; 1478 int pipe; 1479 1480 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1481 &adev->mes.resource_1_addr[0]); 1482 1483 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1484 kfree(adev->mes.mqd_backup[pipe]); 1485 1486 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1487 &adev->mes.eop_gpu_addr[pipe], 1488 NULL); 1489 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1490 } 1491 1492 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1493 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1494 &adev->gfx.kiq[0].ring.mqd_ptr); 1495 1496 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1497 &adev->mes.ring[0].mqd_gpu_addr, 1498 &adev->mes.ring[0].mqd_ptr); 1499 1500 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1501 amdgpu_ring_fini(&adev->mes.ring[0]); 1502 1503 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1504 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1505 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1506 } 1507 1508 amdgpu_mes_fini(adev); 1509 return 0; 1510 } 1511 1512 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1513 { 1514 uint32_t data; 1515 int i; 1516 struct amdgpu_device *adev = ring->adev; 1517 1518 mutex_lock(&adev->srbm_mutex); 1519 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1520 1521 /* disable the queue if it's active */ 1522 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1523 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1524 for (i = 0; i < adev->usec_timeout; i++) { 1525 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1526 break; 1527 udelay(1); 1528 } 1529 } 1530 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1531 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1532 DOORBELL_EN, 0); 1533 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1534 DOORBELL_HIT, 1); 1535 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1536 1537 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1538 1539 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1540 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1541 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1542 1543 soc21_grbm_select(adev, 0, 0, 0, 0); 1544 mutex_unlock(&adev->srbm_mutex); 1545 } 1546 1547 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1548 { 1549 uint32_t tmp; 1550 struct amdgpu_device *adev = ring->adev; 1551 1552 /* tell RLC which is KIQ queue */ 1553 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1554 tmp &= 0xffffff00; 1555 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1556 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1557 } 1558 1559 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1560 { 1561 uint32_t tmp; 1562 1563 /* tell RLC which is KIQ dequeue */ 1564 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1565 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1566 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1567 } 1568 1569 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1570 { 1571 int r = 0; 1572 struct amdgpu_ip_block *ip_block; 1573 1574 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1575 1576 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1577 if (r) { 1578 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1579 return r; 1580 } 1581 1582 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1583 if (r) { 1584 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1585 return r; 1586 } 1587 1588 } 1589 1590 mes_v11_0_enable(adev, true); 1591 1592 mes_v11_0_get_fw_version(adev); 1593 1594 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1595 1596 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1597 if (unlikely(!ip_block)) { 1598 dev_err(adev->dev, "Failed to get MES handle\n"); 1599 return -EINVAL; 1600 } 1601 1602 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1603 if (r) 1604 goto failure; 1605 1606 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1607 adev->mes.enable_legacy_queue_map = true; 1608 else 1609 adev->mes.enable_legacy_queue_map = false; 1610 1611 if (adev->mes.enable_legacy_queue_map) { 1612 r = mes_v11_0_hw_init(ip_block); 1613 if (r) 1614 goto failure; 1615 } 1616 1617 return r; 1618 1619 failure: 1620 mes_v11_0_hw_fini(ip_block); 1621 return r; 1622 } 1623 1624 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1625 { 1626 if (adev->mes.ring[0].sched.ready) { 1627 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1628 adev->mes.ring[0].sched.ready = false; 1629 } 1630 1631 if (amdgpu_sriov_vf(adev)) { 1632 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1633 mes_v11_0_kiq_clear(adev); 1634 } 1635 1636 mes_v11_0_enable(adev, false); 1637 1638 return 0; 1639 } 1640 1641 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1642 { 1643 int r; 1644 struct amdgpu_device *adev = ip_block->adev; 1645 1646 if (adev->mes.ring[0].sched.ready) 1647 goto out; 1648 1649 if (!adev->enable_mes_kiq) { 1650 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1651 r = mes_v11_0_load_microcode(adev, 1652 AMDGPU_MES_SCHED_PIPE, true); 1653 if (r) { 1654 DRM_ERROR("failed to MES fw, r=%d\n", r); 1655 return r; 1656 } 1657 } 1658 1659 mes_v11_0_enable(adev, true); 1660 } 1661 1662 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1663 if (r) 1664 goto failure; 1665 1666 r = mes_v11_0_set_hw_resources(&adev->mes); 1667 if (r) 1668 goto failure; 1669 1670 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) { 1671 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1672 if (r) { 1673 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1674 goto failure; 1675 } 1676 } 1677 1678 r = mes_v11_0_query_sched_status(&adev->mes); 1679 if (r) { 1680 DRM_ERROR("MES is busy\n"); 1681 goto failure; 1682 } 1683 1684 r = amdgpu_mes_update_enforce_isolation(adev); 1685 if (r) 1686 goto failure; 1687 1688 out: 1689 /* 1690 * Disable KIQ ring usage from the driver once MES is enabled. 1691 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1692 * with MES enabled. 1693 */ 1694 adev->gfx.kiq[0].ring.sched.ready = false; 1695 adev->mes.ring[0].sched.ready = true; 1696 1697 return 0; 1698 1699 failure: 1700 mes_v11_0_hw_fini(ip_block); 1701 return r; 1702 } 1703 1704 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1705 { 1706 return 0; 1707 } 1708 1709 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1710 { 1711 return mes_v11_0_hw_fini(ip_block); 1712 } 1713 1714 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1715 { 1716 return mes_v11_0_hw_init(ip_block); 1717 } 1718 1719 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1720 { 1721 struct amdgpu_device *adev = ip_block->adev; 1722 int pipe, r; 1723 1724 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1725 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1726 1727 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1728 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1729 continue; 1730 r = amdgpu_mes_init_microcode(adev, pipe); 1731 if (r) 1732 return r; 1733 } 1734 1735 return 0; 1736 } 1737 1738 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1739 .name = "mes_v11_0", 1740 .early_init = mes_v11_0_early_init, 1741 .late_init = NULL, 1742 .sw_init = mes_v11_0_sw_init, 1743 .sw_fini = mes_v11_0_sw_fini, 1744 .hw_init = mes_v11_0_hw_init, 1745 .hw_fini = mes_v11_0_hw_fini, 1746 .suspend = mes_v11_0_suspend, 1747 .resume = mes_v11_0_resume, 1748 }; 1749 1750 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1751 .type = AMD_IP_BLOCK_TYPE_MES, 1752 .major = 11, 1753 .minor = 0, 1754 .rev = 0, 1755 .funcs = &mes_v11_0_ip_funcs, 1756 }; 1757