1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 30 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 31 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 32 33 static int 34 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 35 struct amdgpu_userq_mgr *uq_mgr, 36 struct amdgpu_usermode_queue *queue, 37 uint64_t wptr) 38 { 39 struct amdgpu_bo_va_mapping *wptr_mapping; 40 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 41 struct amdgpu_bo *obj; 42 struct amdgpu_vm *vm = queue->vm; 43 struct drm_exec exec; 44 int ret; 45 46 wptr &= AMDGPU_GMC_HOLE_MASK; 47 48 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); 49 drm_exec_until_all_locked(&exec) { 50 ret = amdgpu_vm_lock_pd(vm, &exec, 1); 51 drm_exec_retry_on_contention(&exec); 52 if (unlikely(ret)) 53 goto fail_lock; 54 55 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); 56 if (!wptr_mapping) { 57 ret = -EINVAL; 58 goto fail_lock; 59 } 60 61 obj = wptr_mapping->bo_va->base.bo; 62 ret = drm_exec_lock_obj(&exec, &obj->tbo.base); 63 drm_exec_retry_on_contention(&exec); 64 if (unlikely(ret)) 65 goto fail_lock; 66 } 67 68 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); 69 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 70 ret = -EINVAL; 71 goto fail_map; 72 } 73 74 /* TODO use eviction fence instead of pinning. */ 75 ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); 76 if (ret) { 77 DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); 78 goto fail_map; 79 } 80 81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); 82 if (ret) { 83 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); 84 goto fail_alloc_gart; 85 } 86 87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); 88 89 drm_exec_fini(&exec); 90 return 0; 91 92 fail_alloc_gart: 93 amdgpu_bo_unpin(wptr_obj->obj); 94 fail_map: 95 amdgpu_bo_unref(&wptr_obj->obj); 96 fail_lock: 97 drm_exec_fini(&exec); 98 return ret; 99 100 } 101 102 static int convert_to_mes_priority(int priority) 103 { 104 switch (priority) { 105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 106 default: 107 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 108 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 109 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 110 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 111 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 112 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 113 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 114 } 115 } 116 117 static int mes_userq_map(struct amdgpu_usermode_queue *queue) 118 { 119 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 120 struct amdgpu_device *adev = uq_mgr->adev; 121 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 122 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 123 struct mes_add_queue_input queue_input; 124 struct amdgpu_mes *mes = &adev->mes; 125 int r; 126 127 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 128 129 queue_input.process_va_start = 0; 130 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 131 132 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 133 queue_input.process_quantum = 100000; 134 queue_input.gang_quantum = 10000; 135 queue_input.paging = false; 136 137 queue_input.process_context_addr = uq_mgr->proc_ctx_obj.gpu_addr; 138 queue_input.gang_context_addr = ctx->gpu_addr; 139 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 140 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 141 142 queue_input.process_id = queue->vm->pasid; 143 queue_input.queue_type = queue->queue_type; 144 queue_input.mqd_addr = queue->mqd.gpu_addr; 145 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 146 queue_input.queue_size = userq_props->queue_size >> 2; 147 queue_input.doorbell_offset = userq_props->doorbell_index; 148 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 149 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 150 if (mes->use_rs64mem) { 151 amdgpu_mes_alloc_proc_ctx_index(mes, queue); 152 queue_input.process_context_array_index = queue->proc_ctx_array_index; 153 amdgpu_mes_alloc_gang_ctx_index(mes, queue); 154 queue_input.gang_context_array_index = queue->gang_ctx_array_index; 155 } 156 amdgpu_mes_lock(&adev->mes); 157 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 158 amdgpu_mes_unlock(&adev->mes); 159 if (r) { 160 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 161 return r; 162 } 163 164 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 165 return 0; 166 } 167 168 static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) 169 { 170 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 171 struct amdgpu_device *adev = uq_mgr->adev; 172 struct mes_remove_queue_input queue_input; 173 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 174 struct amdgpu_mes *mes = &adev->mes; 175 int r; 176 177 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 178 queue_input.gang_context_array_index = queue->gang_ctx_array_index; 179 queue_input.doorbell_offset = queue->doorbell_index; 180 queue_input.gang_context_addr = ctx->gpu_addr; 181 queue_input.queue_type = queue->queue_type; 182 183 amdgpu_mes_lock(&adev->mes); 184 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 185 amdgpu_mes_unlock(&adev->mes); 186 if (mes->use_rs64mem) { 187 amdgpu_mes_free_proc_ctx_index(mes, queue); 188 amdgpu_mes_free_gang_ctx_index(mes, queue); 189 } 190 if (r) 191 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 192 return r; 193 } 194 195 int mes_userq_reset(struct amdgpu_usermode_queue *queue) 196 { 197 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 198 struct amdgpu_device *adev = uq_mgr->adev; 199 struct mes_reset_queue_input queue_input; 200 int r; 201 202 /* XXX: add a FW version check for SDMA per queue reset */ 203 memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input)); 204 queue_input.doorbell_offset = queue->doorbell_index; 205 queue_input.queue_type = queue->queue_type; 206 207 amdgpu_mes_lock(&adev->mes); 208 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 209 amdgpu_mes_unlock(&adev->mes); 210 if (r) 211 return r; 212 return mes_userq_unmap(queue); 213 } 214 215 int mes_userq_reset_queue(struct amdgpu_device *adev, 216 struct amdgpu_usermode_queue *guilty_uq, 217 int queue_type, 218 unsigned int pipe, 219 unsigned int queue, 220 unsigned int db) 221 { 222 struct amdgpu_usermode_queue *uq; 223 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 224 unsigned long uq_id; 225 int r; 226 227 xa_for_each(&adev->userq_doorbell_xa, uq_id, uq) { 228 if (uq->queue_type == queue_type) { 229 if (uq == guilty_uq) 230 continue; 231 if (uq->doorbell_index == db) { 232 uq->state = AMDGPU_USERQ_STATE_HUNG; 233 if (use_mmio) 234 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 0); 235 else 236 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 0); 237 if (r) 238 return r; 239 r = mes_userq_unmap(uq); 240 if (r) 241 return r; 242 atomic_inc(&adev->gpu_reset_counter); 243 amdgpu_userq_fence_driver_force_completion(uq); 244 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 245 break; 246 } 247 } 248 } 249 return 0; 250 } 251 252 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 253 struct amdgpu_usermode_queue *queue, 254 struct drm_amdgpu_userq_in *mqd_user) 255 { 256 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 257 int r, size; 258 259 /* The FW expects at least one page space allocated for gang ctx. */ 260 size = AMDGPU_USERQ_GANG_CTX_SZ; 261 r = amdgpu_bo_create_kernel(uq_mgr->adev, size, 0, 262 AMDGPU_GEM_DOMAIN_GTT, 263 &ctx->obj, &ctx->gpu_addr, 264 &ctx->cpu_ptr); 265 if (r) { 266 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 267 return r; 268 } 269 270 memset(ctx->cpu_ptr, 0, size); 271 return 0; 272 } 273 274 static int mes_userq_create_proc_ctx_space(struct amdgpu_userq_mgr *uq_mgr) 275 { 276 int r = 0; 277 278 mutex_lock(&uq_mgr->proc_ctx_lock); 279 /* This check is a necessary because amdgpu_bo_create_kernel() 280 * calls helpers like amdgpu_bo_pin() and memset() unconditionally 281 */ 282 if (!uq_mgr->proc_ctx_obj.obj) { 283 r = amdgpu_bo_create_kernel(uq_mgr->adev, AMDGPU_USERQ_PROC_CTX_SZ, 284 0, AMDGPU_GEM_DOMAIN_GTT, 285 &uq_mgr->proc_ctx_obj.obj, 286 &uq_mgr->proc_ctx_obj.gpu_addr, 287 &uq_mgr->proc_ctx_obj.cpu_ptr); 288 289 if (!r) 290 memset(uq_mgr->proc_ctx_obj.cpu_ptr, 0, AMDGPU_USERQ_PROC_CTX_SZ); 291 } 292 293 mutex_unlock(&uq_mgr->proc_ctx_lock); 294 295 return r; 296 } 297 298 static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 299 struct drm_amdgpu_userq_in *args_in) 300 { 301 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 302 struct amdgpu_device *adev = uq_mgr->adev; 303 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 304 struct drm_amdgpu_userq_in *mqd_user = args_in; 305 struct amdgpu_mqd_prop *userq_props; 306 int r; 307 308 /* Structure to initialize MQD for userqueue using generic MQD init function */ 309 userq_props = kzalloc_obj(struct amdgpu_mqd_prop); 310 if (!userq_props) { 311 DRM_ERROR("Failed to allocate memory for userq_props\n"); 312 return -ENOMEM; 313 } 314 315 r = amdgpu_bo_create_kernel(adev, 316 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size), 317 0, AMDGPU_GEM_DOMAIN_GTT, 318 &queue->mqd.obj, &queue->mqd.gpu_addr, 319 &queue->mqd.cpu_ptr); 320 if (r) { 321 DRM_ERROR("Failed to create MQD object for userqueue\n"); 322 goto free_props; 323 } 324 325 memset(queue->mqd.cpu_ptr, 0, 326 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 327 328 /* Initialize the MQD BO with user given values */ 329 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 330 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 331 userq_props->queue_size = mqd_user->queue_size; 332 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 333 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 334 userq_props->use_doorbell = true; 335 userq_props->doorbell_index = queue->doorbell_index; 336 userq_props->fence_address = queue->fence_drv->gpu_addr; 337 338 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 339 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 340 341 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 342 DRM_ERROR("Invalid compute IP MQD size\n"); 343 r = -EINVAL; 344 goto free_mqd; 345 } 346 347 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 348 if (IS_ERR(compute_mqd)) { 349 DRM_ERROR("Failed to read user MQD\n"); 350 r = -ENOMEM; 351 goto free_mqd; 352 } 353 354 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 355 if (r) { 356 kfree(compute_mqd); 357 goto free_mqd; 358 } 359 r = amdgpu_userq_input_va_validate(adev, queue, 360 compute_mqd->eop_va, 2048, 361 &queue->userq_vas.va.eop); 362 amdgpu_bo_unreserve(queue->vm->root.bo); 363 if (r) { 364 kfree(compute_mqd); 365 goto free_mqd; 366 } 367 368 userq_props->eop_gpu_addr = compute_mqd->eop_va; 369 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 370 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 371 userq_props->hqd_active = false; 372 userq_props->tmz_queue = 373 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 374 kfree(compute_mqd); 375 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 376 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 377 struct amdgpu_gfx_shadow_info shadow_info; 378 379 if (adev->gfx.funcs->get_gfx_shadow_info) { 380 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 381 } else { 382 r = -EINVAL; 383 goto free_mqd; 384 } 385 386 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 387 DRM_ERROR("Invalid GFX MQD\n"); 388 r = -EINVAL; 389 goto free_mqd; 390 } 391 392 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 393 if (IS_ERR(mqd_gfx_v11)) { 394 DRM_ERROR("Failed to read user MQD\n"); 395 r = -ENOMEM; 396 goto free_mqd; 397 } 398 399 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 400 userq_props->csa_addr = mqd_gfx_v11->csa_va; 401 userq_props->tmz_queue = 402 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 403 404 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 405 if (r) { 406 kfree(mqd_gfx_v11); 407 goto free_mqd; 408 } 409 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 410 shadow_info.shadow_size, 411 &queue->userq_vas.va.shadow); 412 if (r) { 413 amdgpu_bo_unreserve(queue->vm->root.bo); 414 kfree(mqd_gfx_v11); 415 goto free_mqd; 416 } 417 418 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 419 shadow_info.csa_size, 420 &queue->userq_vas.va.csa); 421 amdgpu_bo_unreserve(queue->vm->root.bo); 422 if (r) { 423 kfree(mqd_gfx_v11); 424 goto free_mqd; 425 } 426 427 kfree(mqd_gfx_v11); 428 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 429 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 430 431 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 432 DRM_ERROR("Invalid SDMA MQD\n"); 433 r = -EINVAL; 434 goto free_mqd; 435 } 436 437 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 438 if (IS_ERR(mqd_sdma_v11)) { 439 DRM_ERROR("Failed to read sdma user MQD\n"); 440 r = -ENOMEM; 441 goto free_mqd; 442 } 443 444 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 445 if (r) { 446 kfree(mqd_sdma_v11); 447 goto free_mqd; 448 } 449 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 450 32, 451 &queue->userq_vas.va.csa); 452 amdgpu_bo_unreserve(queue->vm->root.bo); 453 if (r) { 454 kfree(mqd_sdma_v11); 455 goto free_mqd; 456 } 457 458 userq_props->csa_addr = mqd_sdma_v11->csa_va; 459 kfree(mqd_sdma_v11); 460 } 461 462 queue->userq_prop = userq_props; 463 464 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 465 if (r) { 466 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 467 goto free_mqd; 468 } 469 470 /* Create per-process MES process context BO */ 471 r = mes_userq_create_proc_ctx_space(uq_mgr); 472 if (r) { 473 DRM_ERROR("Failed to allocate MES process context space bo, error: %d\n", r); 474 goto free_mqd; 475 } 476 477 /* Create BO of a gang for FW operations */ 478 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 479 if (r) { 480 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 481 goto free_mqd; 482 } 483 484 /* FW expects WPTR BOs to be mapped into GART */ 485 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 486 if (r) { 487 DRM_ERROR("Failed to create WPTR mapping\n"); 488 goto free_ctx; 489 } 490 491 return 0; 492 493 free_ctx: 494 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 495 &queue->fw_obj.cpu_ptr); 496 497 free_mqd: 498 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 499 &queue->mqd.cpu_ptr); 500 501 free_props: 502 kfree(userq_props); 503 504 return r; 505 } 506 507 static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) 508 { 509 510 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 511 &queue->fw_obj.cpu_ptr); 512 kfree(queue->userq_prop); 513 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 514 &queue->mqd.cpu_ptr); 515 516 amdgpu_bo_reserve(queue->wptr_obj.obj, true); 517 amdgpu_bo_unpin(queue->wptr_obj.obj); 518 amdgpu_bo_unreserve(queue->wptr_obj.obj); 519 amdgpu_bo_unref(&queue->wptr_obj.obj); 520 } 521 522 static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) 523 { 524 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 525 struct amdgpu_device *adev = uq_mgr->adev; 526 struct mes_suspend_gang_input queue_input; 527 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 528 signed long timeout = 2100000; /* 2100 ms */ 529 u64 fence_gpu_addr; 530 u32 fence_offset; 531 u64 *fence_ptr; 532 int i, r; 533 534 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 535 return 0; 536 r = amdgpu_wb_get(adev, &fence_offset); 537 if (r) 538 return r; 539 540 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 541 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 542 *fence_ptr = 0; 543 544 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 545 queue_input.gang_context_addr = ctx->gpu_addr; 546 queue_input.suspend_fence_addr = fence_gpu_addr; 547 queue_input.suspend_fence_value = 1; 548 amdgpu_mes_lock(&adev->mes); 549 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 550 amdgpu_mes_unlock(&adev->mes); 551 if (r) { 552 DRM_ERROR("Failed to suspend gang: %d\n", r); 553 goto out; 554 } 555 556 for (i = 0; i < timeout; i++) { 557 if (*fence_ptr == 1) 558 goto out; 559 udelay(1); 560 } 561 r = -ETIMEDOUT; 562 563 out: 564 amdgpu_wb_free(adev, fence_offset); 565 return r; 566 } 567 568 static int mes_userq_restore(struct amdgpu_usermode_queue *queue) 569 { 570 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 571 struct amdgpu_device *adev = uq_mgr->adev; 572 struct mes_resume_gang_input queue_input; 573 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 574 int r; 575 576 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 577 return -EINVAL; 578 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 579 return 0; 580 581 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 582 queue_input.gang_context_addr = ctx->gpu_addr; 583 584 amdgpu_mes_lock(&adev->mes); 585 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 586 amdgpu_mes_unlock(&adev->mes); 587 if (r) 588 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 589 return r; 590 } 591 592 const struct amdgpu_userq_funcs userq_mes_funcs = { 593 .mqd_create = mes_userq_mqd_create, 594 .mqd_destroy = mes_userq_mqd_destroy, 595 .unmap = mes_userq_unmap, 596 .map = mes_userq_map, 597 .preempt = mes_userq_preempt, 598 .restore = mes_userq_restore, 599 .reset = mes_userq_reset, 600 }; 601