1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 30 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 31 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 32 33 static int 34 mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo) 35 { 36 int ret; 37 38 ret = amdgpu_bo_reserve(bo, true); 39 if (ret) { 40 DRM_ERROR("Failed to reserve bo. ret %d\n", ret); 41 goto err_reserve_bo_failed; 42 } 43 44 ret = amdgpu_ttm_alloc_gart(&bo->tbo); 45 if (ret) { 46 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); 47 goto err_map_bo_gart_failed; 48 } 49 50 amdgpu_bo_unreserve(bo); 51 bo = amdgpu_bo_ref(bo); 52 53 return 0; 54 55 err_map_bo_gart_failed: 56 amdgpu_bo_unreserve(bo); 57 err_reserve_bo_failed: 58 return ret; 59 } 60 61 static int 62 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 63 struct amdgpu_userq_mgr *uq_mgr, 64 struct amdgpu_usermode_queue *queue, 65 uint64_t wptr) 66 { 67 struct amdgpu_bo_va_mapping *wptr_mapping; 68 struct amdgpu_vm *wptr_vm; 69 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 70 int ret; 71 72 wptr_vm = queue->vm; 73 ret = amdgpu_bo_reserve(wptr_vm->root.bo, false); 74 if (ret) 75 return ret; 76 77 wptr &= AMDGPU_GMC_HOLE_MASK; 78 wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT); 79 amdgpu_bo_unreserve(wptr_vm->root.bo); 80 if (!wptr_mapping) { 81 DRM_ERROR("Failed to lookup wptr bo\n"); 82 return -EINVAL; 83 } 84 85 wptr_obj->obj = wptr_mapping->bo_va->base.bo; 86 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 87 DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n"); 88 return -EINVAL; 89 } 90 91 ret = mes_userq_map_gtt_bo_to_gart(wptr_obj->obj); 92 if (ret) { 93 DRM_ERROR("Failed to map wptr bo to GART\n"); 94 return ret; 95 } 96 97 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj); 98 return 0; 99 } 100 101 static int convert_to_mes_priority(int priority) 102 { 103 switch (priority) { 104 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 105 default: 106 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 107 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 108 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 109 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 110 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 111 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 112 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 113 } 114 } 115 116 static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr, 117 struct amdgpu_usermode_queue *queue) 118 { 119 struct amdgpu_device *adev = uq_mgr->adev; 120 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 121 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 122 struct mes_add_queue_input queue_input; 123 int r; 124 125 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 126 127 queue_input.process_va_start = 0; 128 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 129 130 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 131 queue_input.process_quantum = 100000; 132 queue_input.gang_quantum = 10000; 133 queue_input.paging = false; 134 135 queue_input.process_context_addr = ctx->gpu_addr; 136 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 137 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 138 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 139 140 queue_input.process_id = queue->vm->pasid; 141 queue_input.queue_type = queue->queue_type; 142 queue_input.mqd_addr = queue->mqd.gpu_addr; 143 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 144 queue_input.queue_size = userq_props->queue_size >> 2; 145 queue_input.doorbell_offset = userq_props->doorbell_index; 146 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 147 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 148 149 amdgpu_mes_lock(&adev->mes); 150 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 151 amdgpu_mes_unlock(&adev->mes); 152 if (r) { 153 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 154 return r; 155 } 156 157 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 158 return 0; 159 } 160 161 static int mes_userq_unmap(struct amdgpu_userq_mgr *uq_mgr, 162 struct amdgpu_usermode_queue *queue) 163 { 164 struct amdgpu_device *adev = uq_mgr->adev; 165 struct mes_remove_queue_input queue_input; 166 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 167 int r; 168 169 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 170 queue_input.doorbell_offset = queue->doorbell_index; 171 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 172 173 amdgpu_mes_lock(&adev->mes); 174 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 175 amdgpu_mes_unlock(&adev->mes); 176 if (r) 177 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 178 return r; 179 } 180 181 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 182 struct amdgpu_usermode_queue *queue, 183 struct drm_amdgpu_userq_in *mqd_user) 184 { 185 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 186 int r, size; 187 188 /* 189 * The FW expects at least one page space allocated for 190 * process ctx and gang ctx each. Create an object 191 * for the same. 192 */ 193 size = AMDGPU_USERQ_PROC_CTX_SZ + AMDGPU_USERQ_GANG_CTX_SZ; 194 r = amdgpu_userq_create_object(uq_mgr, ctx, size); 195 if (r) { 196 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 197 return r; 198 } 199 200 return 0; 201 } 202 203 static int mes_userq_detect_and_reset(struct amdgpu_device *adev, 204 int queue_type) 205 { 206 int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); 207 struct mes_detect_and_reset_queue_input input; 208 struct amdgpu_usermode_queue *queue; 209 unsigned int hung_db_num = 0; 210 unsigned long queue_id; 211 u32 db_array[8]; 212 bool found_hung_queue = false; 213 int r, i; 214 215 if (db_array_size > 8) { 216 dev_err(adev->dev, "DB array size (%d vs 8) too small\n", 217 db_array_size); 218 return -EINVAL; 219 } 220 221 memset(&input, 0x0, sizeof(struct mes_detect_and_reset_queue_input)); 222 223 input.queue_type = queue_type; 224 225 amdgpu_mes_lock(&adev->mes); 226 r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, 227 &hung_db_num, db_array, 0); 228 amdgpu_mes_unlock(&adev->mes); 229 if (r) { 230 dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); 231 } else if (hung_db_num) { 232 xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 233 if (queue->queue_type == queue_type) { 234 for (i = 0; i < hung_db_num; i++) { 235 if (queue->doorbell_index == db_array[i]) { 236 queue->state = AMDGPU_USERQ_STATE_HUNG; 237 found_hung_queue = true; 238 atomic_inc(&adev->gpu_reset_counter); 239 amdgpu_userq_fence_driver_force_completion(queue); 240 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 241 } 242 } 243 } 244 } 245 } 246 247 if (found_hung_queue) { 248 /* Resume scheduling after hang recovery */ 249 r = amdgpu_mes_resume(adev); 250 } 251 252 return r; 253 } 254 255 static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 256 struct drm_amdgpu_userq_in *args_in, 257 struct amdgpu_usermode_queue *queue) 258 { 259 struct amdgpu_device *adev = uq_mgr->adev; 260 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 261 struct drm_amdgpu_userq_in *mqd_user = args_in; 262 struct amdgpu_mqd_prop *userq_props; 263 int r; 264 265 /* Structure to initialize MQD for userqueue using generic MQD init function */ 266 userq_props = kzalloc(sizeof(struct amdgpu_mqd_prop), GFP_KERNEL); 267 if (!userq_props) { 268 DRM_ERROR("Failed to allocate memory for userq_props\n"); 269 return -ENOMEM; 270 } 271 272 r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size); 273 if (r) { 274 DRM_ERROR("Failed to create MQD object for userqueue\n"); 275 goto free_props; 276 } 277 278 /* Initialize the MQD BO with user given values */ 279 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 280 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 281 userq_props->queue_size = mqd_user->queue_size; 282 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 283 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 284 userq_props->use_doorbell = true; 285 userq_props->doorbell_index = queue->doorbell_index; 286 userq_props->fence_address = queue->fence_drv->gpu_addr; 287 288 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 289 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 290 291 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 292 DRM_ERROR("Invalid compute IP MQD size\n"); 293 r = -EINVAL; 294 goto free_mqd; 295 } 296 297 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 298 if (IS_ERR(compute_mqd)) { 299 DRM_ERROR("Failed to read user MQD\n"); 300 r = -ENOMEM; 301 goto free_mqd; 302 } 303 304 r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va, 305 2048); 306 if (r) 307 goto free_mqd; 308 309 userq_props->eop_gpu_addr = compute_mqd->eop_va; 310 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 311 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 312 userq_props->hqd_active = false; 313 userq_props->tmz_queue = 314 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 315 kfree(compute_mqd); 316 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 317 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 318 struct amdgpu_gfx_shadow_info shadow_info; 319 320 if (adev->gfx.funcs->get_gfx_shadow_info) { 321 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 322 } else { 323 r = -EINVAL; 324 goto free_mqd; 325 } 326 327 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 328 DRM_ERROR("Invalid GFX MQD\n"); 329 r = -EINVAL; 330 goto free_mqd; 331 } 332 333 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 334 if (IS_ERR(mqd_gfx_v11)) { 335 DRM_ERROR("Failed to read user MQD\n"); 336 r = -ENOMEM; 337 goto free_mqd; 338 } 339 340 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 341 userq_props->csa_addr = mqd_gfx_v11->csa_va; 342 userq_props->tmz_queue = 343 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 344 345 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 346 shadow_info.shadow_size); 347 if (r) 348 goto free_mqd; 349 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 350 shadow_info.csa_size); 351 if (r) 352 goto free_mqd; 353 354 kfree(mqd_gfx_v11); 355 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 356 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 357 358 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 359 DRM_ERROR("Invalid SDMA MQD\n"); 360 r = -EINVAL; 361 goto free_mqd; 362 } 363 364 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 365 if (IS_ERR(mqd_sdma_v11)) { 366 DRM_ERROR("Failed to read sdma user MQD\n"); 367 r = -ENOMEM; 368 goto free_mqd; 369 } 370 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 371 32); 372 if (r) 373 goto free_mqd; 374 375 userq_props->csa_addr = mqd_sdma_v11->csa_va; 376 kfree(mqd_sdma_v11); 377 } 378 379 queue->userq_prop = userq_props; 380 381 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 382 if (r) { 383 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 384 goto free_mqd; 385 } 386 387 /* Create BO for FW operations */ 388 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 389 if (r) { 390 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 391 goto free_mqd; 392 } 393 394 /* FW expects WPTR BOs to be mapped into GART */ 395 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 396 if (r) { 397 DRM_ERROR("Failed to create WPTR mapping\n"); 398 goto free_ctx; 399 } 400 401 return 0; 402 403 free_ctx: 404 amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); 405 406 free_mqd: 407 amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); 408 409 free_props: 410 kfree(userq_props); 411 412 return r; 413 } 414 415 static void 416 mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr, 417 struct amdgpu_usermode_queue *queue) 418 { 419 amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); 420 kfree(queue->userq_prop); 421 amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); 422 } 423 424 static int mes_userq_preempt(struct amdgpu_userq_mgr *uq_mgr, 425 struct amdgpu_usermode_queue *queue) 426 { 427 struct amdgpu_device *adev = uq_mgr->adev; 428 struct mes_suspend_gang_input queue_input; 429 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 430 signed long timeout = 2100000; /* 2100 ms */ 431 u64 fence_gpu_addr; 432 u32 fence_offset; 433 u64 *fence_ptr; 434 int i, r; 435 436 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 437 return 0; 438 r = amdgpu_device_wb_get(adev, &fence_offset); 439 if (r) 440 return r; 441 442 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 443 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 444 *fence_ptr = 0; 445 446 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 447 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 448 queue_input.suspend_fence_addr = fence_gpu_addr; 449 queue_input.suspend_fence_value = 1; 450 amdgpu_mes_lock(&adev->mes); 451 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 452 amdgpu_mes_unlock(&adev->mes); 453 if (r) { 454 DRM_ERROR("Failed to suspend gang: %d\n", r); 455 goto out; 456 } 457 458 for (i = 0; i < timeout; i++) { 459 if (*fence_ptr == 1) 460 goto out; 461 udelay(1); 462 } 463 r = -ETIMEDOUT; 464 465 out: 466 amdgpu_device_wb_free(adev, fence_offset); 467 return r; 468 } 469 470 static int mes_userq_restore(struct amdgpu_userq_mgr *uq_mgr, 471 struct amdgpu_usermode_queue *queue) 472 { 473 struct amdgpu_device *adev = uq_mgr->adev; 474 struct mes_resume_gang_input queue_input; 475 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 476 int r; 477 478 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 479 return -EINVAL; 480 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 481 return 0; 482 483 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 484 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 485 486 amdgpu_mes_lock(&adev->mes); 487 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 488 amdgpu_mes_unlock(&adev->mes); 489 if (r) 490 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 491 return r; 492 } 493 494 const struct amdgpu_userq_funcs userq_mes_funcs = { 495 .mqd_create = mes_userq_mqd_create, 496 .mqd_destroy = mes_userq_mqd_destroy, 497 .unmap = mes_userq_unmap, 498 .map = mes_userq_map, 499 .detect_and_reset = mes_userq_detect_and_reset, 500 .preempt = mes_userq_preempt, 501 .restore = mes_userq_restore, 502 }; 503