1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 30 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 31 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 32 33 static int 34 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 35 struct amdgpu_userq_mgr *uq_mgr, 36 struct amdgpu_usermode_queue *queue, 37 uint64_t wptr) 38 { 39 struct amdgpu_bo_va_mapping *wptr_mapping; 40 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 41 struct amdgpu_bo *obj; 42 struct amdgpu_vm *vm = queue->vm; 43 struct drm_exec exec; 44 int ret; 45 46 wptr &= AMDGPU_GMC_HOLE_MASK; 47 48 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); 49 drm_exec_until_all_locked(&exec) { 50 ret = amdgpu_vm_lock_pd(vm, &exec, 1); 51 drm_exec_retry_on_contention(&exec); 52 if (unlikely(ret)) 53 goto fail_lock; 54 55 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); 56 if (!wptr_mapping) { 57 ret = -EINVAL; 58 goto fail_lock; 59 } 60 61 obj = wptr_mapping->bo_va->base.bo; 62 ret = drm_exec_lock_obj(&exec, &obj->tbo.base); 63 drm_exec_retry_on_contention(&exec); 64 if (unlikely(ret)) 65 goto fail_lock; 66 } 67 68 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); 69 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 70 ret = -EINVAL; 71 goto fail_map; 72 } 73 74 /* TODO use eviction fence instead of pinning. */ 75 ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); 76 if (ret) { 77 DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); 78 goto fail_map; 79 } 80 81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); 82 if (ret) { 83 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); 84 goto fail_alloc_gart; 85 } 86 87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); 88 89 drm_exec_fini(&exec); 90 return 0; 91 92 fail_alloc_gart: 93 amdgpu_bo_unpin(wptr_obj->obj); 94 fail_map: 95 amdgpu_bo_unref(&wptr_obj->obj); 96 fail_lock: 97 drm_exec_fini(&exec); 98 return ret; 99 100 } 101 102 static int convert_to_mes_priority(int priority) 103 { 104 switch (priority) { 105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 106 default: 107 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 108 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 109 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 110 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 111 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 112 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 113 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 114 } 115 } 116 117 static int mes_userq_map(struct amdgpu_usermode_queue *queue) 118 { 119 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 120 struct amdgpu_device *adev = uq_mgr->adev; 121 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 122 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 123 struct mes_add_queue_input queue_input; 124 int r; 125 126 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 127 128 queue_input.process_va_start = 0; 129 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 130 131 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 132 queue_input.process_quantum = 100000; 133 queue_input.gang_quantum = 10000; 134 queue_input.paging = false; 135 136 queue_input.process_context_addr = uq_mgr->proc_ctx_obj.gpu_addr; 137 queue_input.gang_context_addr = ctx->gpu_addr; 138 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 139 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 140 141 queue_input.process_id = queue->vm->pasid; 142 queue_input.queue_type = queue->queue_type; 143 queue_input.mqd_addr = queue->mqd.gpu_addr; 144 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 145 queue_input.queue_size = userq_props->queue_size >> 2; 146 queue_input.doorbell_offset = userq_props->doorbell_index; 147 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 148 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 149 150 amdgpu_mes_lock(&adev->mes); 151 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 152 amdgpu_mes_unlock(&adev->mes); 153 if (r) { 154 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 155 return r; 156 } 157 158 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 159 return 0; 160 } 161 162 static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) 163 { 164 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 165 struct amdgpu_device *adev = uq_mgr->adev; 166 struct mes_remove_queue_input queue_input; 167 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 168 int r; 169 170 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 171 queue_input.doorbell_offset = queue->doorbell_index; 172 queue_input.gang_context_addr = ctx->gpu_addr; 173 queue_input.queue_type = queue->queue_type; 174 175 amdgpu_mes_lock(&adev->mes); 176 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 177 amdgpu_mes_unlock(&adev->mes); 178 if (r) 179 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 180 return r; 181 } 182 183 int mes_userq_reset(struct amdgpu_usermode_queue *queue) 184 { 185 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 186 struct amdgpu_device *adev = uq_mgr->adev; 187 struct mes_reset_queue_input queue_input; 188 int r; 189 190 /* XXX: add a FW version check for SDMA per queue reset */ 191 memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input)); 192 queue_input.doorbell_offset = queue->doorbell_index; 193 queue_input.queue_type = queue->queue_type; 194 195 amdgpu_mes_lock(&adev->mes); 196 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 197 amdgpu_mes_unlock(&adev->mes); 198 if (r) 199 return r; 200 return mes_userq_unmap(queue); 201 } 202 203 int mes_userq_reset_queue(struct amdgpu_device *adev, 204 struct amdgpu_usermode_queue *guilty_uq, 205 int queue_type, 206 unsigned int pipe, 207 unsigned int queue, 208 unsigned int db) 209 { 210 struct amdgpu_usermode_queue *uq; 211 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 212 unsigned long uq_id; 213 int r; 214 215 xa_for_each(&adev->userq_doorbell_xa, uq_id, uq) { 216 if (uq->queue_type == queue_type) { 217 if (uq == guilty_uq) 218 continue; 219 if (uq->doorbell_index == db) { 220 uq->state = AMDGPU_USERQ_STATE_HUNG; 221 if (use_mmio) 222 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 0); 223 else 224 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 0); 225 if (r) 226 return r; 227 r = mes_userq_unmap(uq); 228 if (r) 229 return r; 230 atomic_inc(&adev->gpu_reset_counter); 231 amdgpu_userq_fence_driver_force_completion(uq); 232 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 233 break; 234 } 235 } 236 } 237 return 0; 238 } 239 240 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 241 struct amdgpu_usermode_queue *queue, 242 struct drm_amdgpu_userq_in *mqd_user) 243 { 244 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 245 int r, size; 246 247 /* The FW expects at least one page space allocated for gang ctx. */ 248 size = AMDGPU_USERQ_GANG_CTX_SZ; 249 r = amdgpu_bo_create_kernel(uq_mgr->adev, size, 0, 250 AMDGPU_GEM_DOMAIN_GTT, 251 &ctx->obj, &ctx->gpu_addr, 252 &ctx->cpu_ptr); 253 if (r) { 254 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 255 return r; 256 } 257 258 memset(ctx->cpu_ptr, 0, size); 259 return 0; 260 } 261 262 static int mes_userq_create_proc_ctx_space(struct amdgpu_userq_mgr *uq_mgr) 263 { 264 int r = 0; 265 266 mutex_lock(&uq_mgr->proc_ctx_lock); 267 /* This check is a necessary because amdgpu_bo_create_kernel() 268 * calls helpers like amdgpu_bo_pin() and memset() unconditionally 269 */ 270 if (!uq_mgr->proc_ctx_obj.obj) { 271 r = amdgpu_bo_create_kernel(uq_mgr->adev, AMDGPU_USERQ_PROC_CTX_SZ, 272 0, AMDGPU_GEM_DOMAIN_GTT, 273 &uq_mgr->proc_ctx_obj.obj, 274 &uq_mgr->proc_ctx_obj.gpu_addr, 275 &uq_mgr->proc_ctx_obj.cpu_ptr); 276 277 if (!r) 278 memset(uq_mgr->proc_ctx_obj.cpu_ptr, 0, AMDGPU_USERQ_PROC_CTX_SZ); 279 } 280 281 mutex_unlock(&uq_mgr->proc_ctx_lock); 282 283 return r; 284 } 285 286 static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 287 struct drm_amdgpu_userq_in *args_in) 288 { 289 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 290 struct amdgpu_device *adev = uq_mgr->adev; 291 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 292 struct drm_amdgpu_userq_in *mqd_user = args_in; 293 struct amdgpu_mqd_prop *userq_props; 294 int r; 295 296 /* Structure to initialize MQD for userqueue using generic MQD init function */ 297 userq_props = kzalloc_obj(struct amdgpu_mqd_prop); 298 if (!userq_props) { 299 DRM_ERROR("Failed to allocate memory for userq_props\n"); 300 return -ENOMEM; 301 } 302 303 r = amdgpu_bo_create_kernel(adev, 304 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size), 305 0, AMDGPU_GEM_DOMAIN_GTT, 306 &queue->mqd.obj, &queue->mqd.gpu_addr, 307 &queue->mqd.cpu_ptr); 308 if (r) { 309 DRM_ERROR("Failed to create MQD object for userqueue\n"); 310 goto free_props; 311 } 312 313 memset(queue->mqd.cpu_ptr, 0, 314 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 315 316 /* Initialize the MQD BO with user given values */ 317 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 318 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 319 userq_props->queue_size = mqd_user->queue_size; 320 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 321 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 322 userq_props->use_doorbell = true; 323 userq_props->doorbell_index = queue->doorbell_index; 324 userq_props->fence_address = queue->fence_drv->gpu_addr; 325 326 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 327 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 328 329 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 330 DRM_ERROR("Invalid compute IP MQD size\n"); 331 r = -EINVAL; 332 goto free_mqd; 333 } 334 335 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 336 if (IS_ERR(compute_mqd)) { 337 DRM_ERROR("Failed to read user MQD\n"); 338 r = -ENOMEM; 339 goto free_mqd; 340 } 341 342 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 343 if (r) { 344 kfree(compute_mqd); 345 goto free_mqd; 346 } 347 r = amdgpu_userq_input_va_validate(adev, queue, 348 compute_mqd->eop_va, 2048, 349 &queue->userq_vas.va.eop); 350 amdgpu_bo_unreserve(queue->vm->root.bo); 351 if (r) { 352 kfree(compute_mqd); 353 goto free_mqd; 354 } 355 356 userq_props->eop_gpu_addr = compute_mqd->eop_va; 357 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 358 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 359 userq_props->hqd_active = false; 360 userq_props->tmz_queue = 361 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 362 kfree(compute_mqd); 363 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 364 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 365 struct amdgpu_gfx_shadow_info shadow_info; 366 367 if (adev->gfx.funcs->get_gfx_shadow_info) { 368 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 369 } else { 370 r = -EINVAL; 371 goto free_mqd; 372 } 373 374 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 375 DRM_ERROR("Invalid GFX MQD\n"); 376 r = -EINVAL; 377 goto free_mqd; 378 } 379 380 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 381 if (IS_ERR(mqd_gfx_v11)) { 382 DRM_ERROR("Failed to read user MQD\n"); 383 r = -ENOMEM; 384 goto free_mqd; 385 } 386 387 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 388 userq_props->csa_addr = mqd_gfx_v11->csa_va; 389 userq_props->tmz_queue = 390 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 391 392 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 393 if (r) { 394 kfree(mqd_gfx_v11); 395 goto free_mqd; 396 } 397 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 398 shadow_info.shadow_size, 399 &queue->userq_vas.va.shadow); 400 if (r) { 401 amdgpu_bo_unreserve(queue->vm->root.bo); 402 kfree(mqd_gfx_v11); 403 goto free_mqd; 404 } 405 406 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 407 shadow_info.csa_size, 408 &queue->userq_vas.va.csa); 409 amdgpu_bo_unreserve(queue->vm->root.bo); 410 if (r) { 411 kfree(mqd_gfx_v11); 412 goto free_mqd; 413 } 414 415 kfree(mqd_gfx_v11); 416 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 417 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 418 419 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 420 DRM_ERROR("Invalid SDMA MQD\n"); 421 r = -EINVAL; 422 goto free_mqd; 423 } 424 425 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 426 if (IS_ERR(mqd_sdma_v11)) { 427 DRM_ERROR("Failed to read sdma user MQD\n"); 428 r = -ENOMEM; 429 goto free_mqd; 430 } 431 432 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 433 if (r) { 434 kfree(mqd_sdma_v11); 435 goto free_mqd; 436 } 437 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 438 32, 439 &queue->userq_vas.va.csa); 440 amdgpu_bo_unreserve(queue->vm->root.bo); 441 if (r) { 442 kfree(mqd_sdma_v11); 443 goto free_mqd; 444 } 445 446 userq_props->csa_addr = mqd_sdma_v11->csa_va; 447 kfree(mqd_sdma_v11); 448 } 449 450 queue->userq_prop = userq_props; 451 452 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 453 if (r) { 454 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 455 goto free_mqd; 456 } 457 458 /* Create per-process MES process context BO */ 459 r = mes_userq_create_proc_ctx_space(uq_mgr); 460 if (r) { 461 DRM_ERROR("Failed to allocate MES process context space bo, error: %d\n", r); 462 goto free_mqd; 463 } 464 465 /* Create BO of a gang for FW operations */ 466 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 467 if (r) { 468 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 469 goto free_mqd; 470 } 471 472 /* FW expects WPTR BOs to be mapped into GART */ 473 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 474 if (r) { 475 DRM_ERROR("Failed to create WPTR mapping\n"); 476 goto free_ctx; 477 } 478 479 return 0; 480 481 free_ctx: 482 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 483 &queue->fw_obj.cpu_ptr); 484 485 free_mqd: 486 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 487 &queue->mqd.cpu_ptr); 488 489 free_props: 490 kfree(userq_props); 491 492 return r; 493 } 494 495 static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) 496 { 497 498 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 499 &queue->fw_obj.cpu_ptr); 500 kfree(queue->userq_prop); 501 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 502 &queue->mqd.cpu_ptr); 503 504 amdgpu_bo_reserve(queue->wptr_obj.obj, true); 505 amdgpu_bo_unpin(queue->wptr_obj.obj); 506 amdgpu_bo_unreserve(queue->wptr_obj.obj); 507 amdgpu_bo_unref(&queue->wptr_obj.obj); 508 } 509 510 static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) 511 { 512 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 513 struct amdgpu_device *adev = uq_mgr->adev; 514 struct mes_suspend_gang_input queue_input; 515 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 516 signed long timeout = 2100000; /* 2100 ms */ 517 u64 fence_gpu_addr; 518 u32 fence_offset; 519 u64 *fence_ptr; 520 int i, r; 521 522 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 523 return 0; 524 r = amdgpu_wb_get(adev, &fence_offset); 525 if (r) 526 return r; 527 528 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 529 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 530 *fence_ptr = 0; 531 532 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 533 queue_input.gang_context_addr = ctx->gpu_addr; 534 queue_input.suspend_fence_addr = fence_gpu_addr; 535 queue_input.suspend_fence_value = 1; 536 amdgpu_mes_lock(&adev->mes); 537 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 538 amdgpu_mes_unlock(&adev->mes); 539 if (r) { 540 DRM_ERROR("Failed to suspend gang: %d\n", r); 541 goto out; 542 } 543 544 for (i = 0; i < timeout; i++) { 545 if (*fence_ptr == 1) 546 goto out; 547 udelay(1); 548 } 549 r = -ETIMEDOUT; 550 551 out: 552 amdgpu_wb_free(adev, fence_offset); 553 return r; 554 } 555 556 static int mes_userq_restore(struct amdgpu_usermode_queue *queue) 557 { 558 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 559 struct amdgpu_device *adev = uq_mgr->adev; 560 struct mes_resume_gang_input queue_input; 561 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 562 int r; 563 564 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 565 return -EINVAL; 566 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 567 return 0; 568 569 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 570 queue_input.gang_context_addr = ctx->gpu_addr; 571 572 amdgpu_mes_lock(&adev->mes); 573 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 574 amdgpu_mes_unlock(&adev->mes); 575 if (r) 576 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 577 return r; 578 } 579 580 const struct amdgpu_userq_funcs userq_mes_funcs = { 581 .mqd_create = mes_userq_mqd_create, 582 .mqd_destroy = mes_userq_mqd_destroy, 583 .unmap = mes_userq_unmap, 584 .map = mes_userq_map, 585 .preempt = mes_userq_preempt, 586 .restore = mes_userq_restore, 587 .reset = mes_userq_reset, 588 }; 589